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| r intel ? 915g/915gv/915GL/915p/ 915pl/910gl express chipset datasheet for the intel ? 82915g/82915gv/82915GL/82910gl graphics and memory controller hub (gmch) and the intel ? 82915p/82915pl memory controller hub (mch) february 2005 document number: 301467-005
r 2 datasheet information in this document is provided in connection with intel ? products. no license, express or implied, by estoppel or otherwise, to any intellect ual property rights is granted by th is document. except as provided in intel?s terms and conditions of sale for such product s, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sal e and/or use of intel products including liability or warranties relating to fitness for a particular purpo se, merchantability, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, or life sustai ning applications. intel may make changes to specif ications and product descriptions at any time, without notice. designers must not rely on the abs ence or characteristics of any features or instructions mark ed "reserved" or "undefined." int el reserves these for future definition and shall have no responsib ility whatsoever for conflicts or incompatibilities aris ing from future changes to them. the intel ? 82915g,82915gv,82915GL,82910gl gmch and 82915p/82915pl m ch may contain design def ects or errors known as errata, which may cause the product to deviate from published specificat ions. current characterized e rrata are available on request. contact your local intel sales o ffice or your distributor to obtain the latest specifications and before placing your product o rder. 1 hyper-threading technology requires a computer system with an in tel? pentium? 4 processor supporting ht technology and a hyper- threading technology enabled chipset, bios and operating system. perform ance will vary depending on the spec ific hardware and software yo u use. see http://www.intel.com/pr oducts/ht/hyperthreading_more.htm for more information including details on whic h processors support ht technology. intel, pentium, celeron and the intel logo are trademarks or regi stered trademarks of intel corporat ion or its subsidiaries in the united states and other countries. *other names and brands may be clai med as the property of others. copyright? 2004?2005, intel corporation. all rights reserved r datasheet 3 contents 1 introduc tion ................................................................................................................... .... 17 1.1 terminol ogy.......................................................................................................... 24 1.2 reference do cuments.......................................................................................... 26 1.3 gmch (mch) ov erview....................................................................................... 26 1.3.1 host inte rface........................................................................................ 26 1.3.2 system memory interfac e..................................................................... 27 1.3.3 direct media inte rface (d mi)................................................................. 28 1.3.4 pci express* graphics interface (intel ? 82915g/82915p/ and 82915pl on ly) ............................................................................... 28 1.3.5 integrated graphics (intel ? 82915g/82915gv/82910gl/82915GL gmch only ) ......................................................................................... 29 1.3.6 analog and intel ? sdvo displays (intel ? 82915g/82915gv/82910gl/82915GL gmch only ) ........................... 31 1.3.7 system inte rrupts.................................................................................. 31 1.3.8 (g)mch clo cking.................................................................................. 31 1.3.9 power m anagement .............................................................................. 32 2 signal descr iption ............................................................................................................. 33 2.1 host interfac e signal s .......................................................................................... 35 2.2 ddr/ddr2 dram channel a interface .............................................................. 38 2.3 ddr/ddr2 dram channel b interface .............................................................. 39 2.4 ddr/ddr2 dram reference and compensat ion .............................................. 40 2.5 pci express* x16 graphics port signals (intel ? 82915g, 82915p, 82915pl only )...................................................................................................... 41 2.6 analog display signals (intel ? 82915g/82915gv/82915GL/82910gl gmch only ) ......................................................................................................... 42 2.7 clocks, reset, and miscell aneous ....................................................................... 43 2.8 direct media inte rface (d mi) ................................................................................ 43 2.9 intel ? serial dvo (sdvo) interface (82915g/82915gv/82915GL/82910gl gmch only ) ......................................................................................................... 44 2.10 power and ground ............................................................................................... 45 2.11 reset states and pu ll-up/pull- downs ................................................................... 46 3 register de scription.......................................................................................................... 5 3 3.1 register te rminol ogy ........................................................................................... 53 3.2 platform conf iguratio n.......................................................................................... 55 3.3 general routing confi guration a ccesses ............................................................ 58 3.3.1 standard pci bus confi guration me chanism ....................................... 58 3.3.2 logical pci bus 0 confi guration me chanism ....................................... 58 3.3.3 primary pci and downstream configuration mechani sm .................... 59 3.3.4 pci express* enhanced conf iguration me chanism ............................. 60 3.3.5 intel ? 915x gmch configurati on cycle flow chart ............................... 62 3.4 i/o mapped regi sters .......................................................................................... 63 3.4.1 config_address?configurati on address r egister ...................... 63 r 4 datasheet 3.4.2 config_data?configurat ion data r egister .................................... 64 4 host bridge/dram controlle r registers (d0:f0 ) ............................................................. 65 4.1 host bridge/dram controller pci register details (d0:f0) ............................... 68 4.1.1 vid?vendor identific ation (d0: f0) ...................................................... 68 4.1.2 did?device identific ation (d0: f0) ...................................................... 68 4.1.3 pcicmd?pci comm and (d0:f0 ) ....................................................... 69 4.1.4 pcists?pci stat us (d0: f0)............................................................... 70 4.1.5 rid?revision identific ation (d0: f0).................................................... 71 4.1.6 cc?class code (d0:f0 ) ..................................................................... 71 4.1.7 mlt?master latency timer (d0: f0)................................................... 72 4.1.8 hdr?header type (d0:f0) ................................................................ 72 4.1.9 svid?subsystem vendor ident ification (d 0:f0)................................. 72 4.1.10 sid?subsystem identif ication (d 0:f0)................................................ 73 4.1.11 capptr?capabilities po inter (d0: f0) ............................................... 73 4.1.12 epbar?egress port base address (d 0:f0) ...................................... 74 4.1.13 mchbar?(g)mch memory mapped register range base address (d0:f0).................................................................................................. 75 4.1.14 pciexbar?pci express* register range base address (d0:f0) (intel ? 82915g/82915p/82915p l only)................................................ 76 4.1.15 dmibar?root complex register range base address (d0:f0) ...... 77 4.1.16 ggc?gmch graphics control register (d0:f0) (82915g/82915gv/82915GL/82910g l gmch onl y)........................... 78 4.1.17 deven?device enabl e (d0:f0 ) ......................................................... 79 4.1.18 pam0?programmable attri bute map 0 (d 0:f0) .................................. 81 4.1.19 pam1?programmable attri bute map 1 (d 0:f0) .................................. 82 4.1.20 pam2?programmable attri bute map 2 (d 0:f0) .................................. 83 4.1.21 pam3?programmable attri bute map 3 (d 0:f0) .................................. 84 4.1.22 pam4?programmable attri bute map 4 (d 0:f0) .................................. 85 4.1.23 pam5?programmable attri bute map 5 (d 0:f0) .................................. 86 4.1.24 pam6?programmable attri bute map 6 (d 0:f0) .................................. 87 4.1.25 lac?legacy access cont rol (d0: f0) ................................................. 88 4.1.26 tolud?top of low us able dram (d 0:f0) ....................................... 89 4.1.27 smram?system management ra m control (d 0:f0)........................ 90 4.1.28 esmramc?extended system management ram control (d0:f0) .. 91 4.1.29 errsts?error stat us (d0: f0) ........................................................... 92 4.1.30 errcmd?error comm and (d0:f0 ) ................................................... 93 4.1.31 skpd?scratchpad data (d0:f0 ) ........................................................ 94 4.1.32 capid0?capability ident ifier (d0: f0) ................................................. 94 5 mchbar regi sters .......................................................................................................... 95 5.1 mchbar regist er deta ils ................................................................................... 96 5.1.1 c0drb0?channel a dram rank boundary addr ess 0 .................... 96 5.1.2 c0drb1?channel a dram rank boundary addr ess 1 .................... 98 5.1.3 c0drb2?channel a dram rank boundary addr ess 2 .................... 98 5.1.4 c0drb3?channel a dram rank boundary addr ess 3 .................... 98 5.1.5 c0dra0?channel a dram rank 0,1 attribute ................................. 99 5.1.6 c0dra2?channel a dram rank 2,3 attribute ................................. 99 5.1.7 c0dclkdis?channel a dram clock dis able ................................ 100 5.1.8 c0bnkarc?channel a dram b ank archit ecture .......................... 101 5.1.9 c0drt1?channel a dram timing regi ster ................................... 102 5.1.10 c0drc0?channel a dram c ontroller m ode 0 ............................... 104 5.1.11 c1drb0?channel b dram rank boundary addr ess 0 .................. 106 r datasheet 5 5.1.12 c1drb1?channel b dram rank boundary addr ess 1 .................. 106 5.1.13 c1drb2?channel b dram rank boundary addr ess 2 .................. 106 5.1.14 c1drb3?channel b dram rank boundary addr ess 3 .................. 106 5.1.15 c1dra0?channel b dram rank 0,1 attr ibute ............................... 106 5.1.16 c1dra2?channel b dram rank 2,3 attr ibute ............................... 107 5.1.17 c1dclkdis?channel b dram clock dis able ................................ 107 5.1.18 c1bnkarc?channel b bank architec ture ...................................... 107 5.1.19 c1drt1?channel b dram ti ming regist er 1 ................................ 107 5.1.20 c1drc0?channel b dram c ontroller m ode 0 ............................... 107 5.1.21 pmcfg?power management configurat ion .................................... 108 5.1.22 pmsts?power managem ent status ................................................ 108 6 epbar registers?egress port register summary ...................................................... 109 6.1 ep rcrb configuration register details .......................................................... 109 6.1.1 epesd?ep element self descrip tion............................................... 110 6.1.2 eple1d?ep link entr y 1 descrip tion .............................................. 111 6.1.3 eple1a?ep link entr y 1 addr ess.................................................... 111 6.1.4 eple2d?ep link entr y 2 descrip tion .............................................. 112 6.1.5 eple2a?ep link entr y 2 addr ess.................................................... 113 7 dmibar registers?direct m edia interface (dmi) rcrb ............................................. 115 7.1 direct media interface (dmi ) rcrb register details ........................................ 116 7.1.1 dmivcech?dmi virtual channel enhanced capability header ..... 116 7.1.2 dmipvccap1?dmi port vc capability regi ster 1 .......................... 116 7.1.3 dmipvccap2?dmi port vc capability regi ster 2 .......................... 117 7.1.4 dmipvcctl?dmi port vc cont rol .................................................. 117 7.1.5 dmivc0rcap?dmi vc0 re source c apability ................................ 118 7.1.6 dmivc0rctl0?dmi vc0 re source c ontrol ................................... 119 7.1.7 dmivc0rsts?dmi vc0 resource status....................................... 120 7.1.8 dmivc1rcap?dmi vc1 re source c apability ................................ 120 7.1.9 dmivc1rctl1?dmi vc1 re source c ontrol ................................... 121 7.1.10 dmivc1rsts?dmi vc1 resource status....................................... 121 7.1.11 dmilcap?dmi link capabilit ies ...................................................... 122 7.1.12 dmilctl?dmi link contro l .............................................................. 122 7.1.13 dmilsts?dmi li nk status ............................................................... 123 8 host-pci express* bridge registers (d1:f0) (intel ? 82915g/82915p/82915pl only) 125 8.1 host-pci express* bridge pci register details (d1:f0 ) ................................... 128 8.1.1 vid1?vendor identific ation (d1: f0) .................................................. 128 8.1.2 did1?device identific ation (d1: f0) .................................................. 128 8.1.3 pcicmd1?pci comm and (d1:f0 ) ................................................... 129 8.1.4 pcists1?pci stat us (d1: f0)........................................................... 130 8.1.5 rid1?revision identif ication (d 1:f0)................................................ 132 8.1.6 cc1?class code (d1:f0 ) ................................................................. 132 8.1.7 cl1?cache line si ze (d1: f0) .......................................................... 133 8.1.8 hdr1?header type (d1:f0 ) ............................................................ 133 8.1.9 pbusn1?primary bus nu mber (d1: f0) ........................................... 133 8.1.10 sbusn1?secondary bus nu mber (d1: f0) ...................................... 134 8.1.11 subusn1?subordinate bus number (d 1:f0) ................................. 134 8.1.12 iobase1?i/o base a ddress (d1: f0) ............................................... 135 8.1.13 iolimit1?i/o limit address (d 1:f0) ................................................ 135 8.1.14 ssts1?secondary stat us (d1: f0) ................................................... 136 8.1.15 mbase1?memory base a ddress (d1: f0)........................................ 137 r 6 datasheet 8.1.16 mlimit1?memory limit address (d 1:f0)......................................... 138 8.1.17 pmbase1?prefetchable memory ba se address (d1:f0) ................ 139 8.1.18 pmlimit1?prefetchable memory limit address (d1:f0) ................. 140 8.1.19 capptr1?capabilities po inter (d1: f0) ........................................... 140 8.1.20 intrline1?interrupt line (d1: f0) ................................................... 141 8.1.21 intrpin1?interrupt pin (d1: f0) ....................................................... 141 8.1.22 bctrl1?bridge cont rol (d1: f0) ...................................................... 142 8.1.23 pm_capid1?power management capabilities (d 1:f0) .................. 144 8.1.24 pm_cs1?power management cont rol/status (d1:f0) .................... 145 8.1.25 ss_capid?subsystem id and vendor id capabilities (d1:f0) ...... 146 8.1.26 ss?subsystem id and subsyste m vendor id (d1:f0) .................... 146 8.1.27 msi_capid?message signaled interrupts capability id (d1:f0).... 147 8.1.28 mc?message contro l (d1:f0 ) .......................................................... 148 8.1.29 ma?message addre ss (d1:f0 )......................................................... 149 8.1.30 md?message data (d1:f0 ) .............................................................. 149 8.1.31 peg_capl?pci express* c apability list (d1:f0 ) ........................... 150 8.1.32 peg_cap?pci express*-g capabilities (d 1:f0)............................. 150 8.1.33 dcap?device capabilit ies (d1: f0) .................................................. 151 8.1.34 dctl?device cont rol (d1: f0) .......................................................... 152 8.1.35 dsts?device stat us (d1: f0) ........................................................... 153 8.1.36 lcap?link capabilit ies (d1: f0) ....................................................... 154 8.1.37 lctl?link contro l (d1:f0 ) ............................................................... 155 8.1.38 lsts?link status (d1:f0 ) ................................................................ 156 8.1.39 slotcap?slot capab ilities (d1: f0) ................................................ 157 8.1.40 slotctl?slot cont rol (d1: f0) ........................................................ 158 8.1.41 slotsts?slot stat us (d1: f0) ......................................................... 159 8.1.42 rctl?root contro l (d1:f0 ) ............................................................. 160 8.1.43 rsts?root status (d1:f0 )............................................................... 161 8.1.44 peglc?pci express*-g legacy cont rol ......................................... 162 8.1.45 vcech?virtual channel enhanced capability header (d1:f0) ...... 163 8.1.46 pvccap1?port vc capability register 1 (d1:f0 ) ........................... 163 8.1.47 pvccap2?port vc capability register 2 (d1:f0 ) ........................... 164 8.1.48 pvcctl?port vc c ontrol (d1: f0) ................................................... 164 8.1.49 vc0rcap?vc0 resource capability (d 1:f0) ................................. 165 8.1.50 vc0rctl?vc0 resource control (d 1:f0) ...................................... 165 8.1.51 vc0rsts?vc0 resource status (d 1:f0)........................................ 166 8.1.52 vc1rcap?vc1 resource capability (d 1:f0) ................................. 166 8.1.53 vc1rctl?vc1 resource control (d 1:f0) ...................................... 167 8.1.54 vc1rsts?vc1 resource status (d 1:f0)........................................ 168 8.1.55 rcldech?root complex link declaration enhanced capability header (d1: f0) ................................................................................... 168 8.1.56 esd?element self de scription (d 1:f0) ............................................ 169 8.1.57 le1d?link entry 1 de scription (d 1:f0)............................................ 170 8.1.58 le1a?link entry 1 a ddress (d1: f0)................................................. 171 8.1.59 pegssts?pci express*-g s equence status (d1:f0).................... 171 9 integrated graphics device r egisters (d2:f0) (intel ? 82915g/82915gv/82915GL/ 82910gl gmch on ly).................................................................................................... 173 9.1 integrated graphics device pci r egister details (d2:f0)................................. 175 9.1.1 vid2?vendor identific ation (d2: f0) .................................................. 175 9.1.2 did2?device identific ation (d2: f0) .................................................. 175 9.1.3 pcicmd2?pci comm and (d2:f0 ) ................................................... 176 9.1.4 pcists2?pci stat us (d2: f0)........................................................... 177 r datasheet 7 9.1.5 rid2?revision identif ication (d 2:f0)................................................ 178 9.1.6 cc?class code (d2:f0 ) ................................................................... 178 9.1.7 cls?cache line si ze (d2: f0).......................................................... 179 9.1.8 mlt2?master latency timer (d2: f0)............................................... 179 9.1.9 hdr2?header type (d2:f0 ) ............................................................ 180 9.1.10 mmadr?memory mapped range address (d 2:f0) ........................ 180 9.1.11 iobar?i/o base a ddress (d2: f0) ................................................... 181 9.1.12 gmadr?graphics memory r ange address (d 2:f0) ....................... 182 9.1.13 gttadr?graphics translation tabl e range address (d2:f0)....... 183 9.1.14 svid2?subsystem vendor ident ification (d 2:f0)............................. 183 9.1.15 sid2?subsystem identif ication (d 2:f0)............................................ 184 9.1.16 romadr?video bios rom base address (d 2:f0) ....................... 184 9.1.17 cappoint?capabilities po inter (d2: f0) ......................................... 185 9.1.18 intrline?interrupt line (d2: f0) ..................................................... 185 9.1.19 intrpin?interrupt pin (d2: f0) ......................................................... 185 9.1.20 mingnt?minimum gr ant (d2: f0) .................................................... 186 9.1.21 maxlat?maximum lat ency (d2: f0) ............................................... 186 9.1.22 mcapptr?mirror of dev0 capability pointer (d2:f0) (mirror ed_d0_34) ............................................................................... 186 9.1.23 mcapid?mirror of dev0 capab ility identification (d2:f0) (mirrored_d 0_e0) ............................................................................... 186 9.1.24 mggc?mirror of dev0 gmch graphics control (d2:f0) (mirror ed_d0_52) ............................................................................... 187 9.1.25 mdevendev0f0?mirror of dev0 device enable (d2:f0) (mirror ed_d0_54) ............................................................................... 187 9.1.26 bsm?base of stolen me mory (d2: f0).............................................. 187 9.1.27 msac?multi size apertu re control (d2:f0 ) ..................................... 188 9.1.28 pmcapid?power management c apabilities id (d2:f0).................. 188 9.1.29 pmcap?power management c apabilities (d 2:f0) .......................... 189 9.1.30 pmcs?power management cont rol/status (d2:f0) ........................ 190 9.1.31 swsmi?software sm i (d2:f0 ) ......................................................... 191 9.1.32 asle?system display event register (d2:f0 ) ................................ 191 9.1.33 asls?asl storage (d2:f0 ) ............................................................. 192 10 device 2 function 1 (d2:f1) c onfiguration registers (intel ? 82915g/82915gv/82915GL/ 82910gl only )................................................................. 193 10.1 device 2 function 1 configurati on register deta ils (d2: f1) ............................. 194 10.1.1 vid2?vendor identific ation (d2: f1) .................................................. 194 10.1.2 did2?device identific ation (d2: f1) .................................................. 194 10.1.3 pcicmd2?pci comm and (d2:f1 ) ................................................... 195 10.1.4 pcists2?pci stat us (d2: f1)........................................................... 196 10.1.5 rid2?revision identif ication (d 2:f1)................................................ 197 10.1.6 cc?class code regist er (d2: f1)..................................................... 197 10.1.7 cls?cache line si ze (d2: f1).......................................................... 197 10.1.8 mlt2?master latency timer (d2: f1)............................................... 198 10.1.9 hdr2?header type regist er (d2: f1).............................................. 198 10.1.10 mmadr?memory mapped range address (d 2:f1) ........................ 198 10.1.11 svid2?subsystem vendor ident ification (d 2:f1)............................. 199 10.1.12 sid2?subsystem identif ication (d 2:f1)............................................ 199 10.1.13 romadr?video bios rom base address (d 2:f1) ....................... 199 10.1.14 cappoint?capabilities po inter (d2: f1) ......................................... 199 10.1.15 mingnt?minimum grant register (d 2:f1)...................................... 200 10.1.16 maxlat?maximum lat ency (d2: f1) ............................................... 200 r 8 datasheet 10.1.17 mcapptr?mirror of dev0 capability pointer (d2:f1) (mirror ed_d0_34) ............................................................................... 200 10.1.18 mcapid?mirror of dev0 capab ility identification (d2:f1) (mirrored_d 0_e0) ............................................................................... 200 10.1.19 mggc?mirror of dev0 gmch graphics control (d2:f1) (mirror ed_d0_52) ............................................................................... 200 10.1.20 mdevendev0f0?mirror of dev0 device enable (d2:f1) (mirror ed_d0_54) ............................................................................... 201 10.1.21 bsm?base of stolen memory register (d2:f1 ) ............................... 201 10.1.22 pmcapid?power management c apabilities id (d2:f1).................. 201 10.1.23 pmcap?power management c apabilities (d 2:f1) .......................... 201 10.1.24 pmcs?power management cont rol/status (d2:f1) ........................ 202 10.1.25 swsmi?software sm i (d2:f1 ) ......................................................... 202 10.1.26 asls?asl storage (d2:f1 ) ............................................................. 203 10.2 device 2 ? pci i/o regist ers ............................................................................. 204 10.2.1 mmio_index?mmio addr ess regi ster........................................... 204 10.2.2 mmio_data?mmio da ta regi ster .................................................. 204 11 system addr ess ma p ...................................................................................................... 205 11.1 legacy addre ss range ...................................................................................... 207 11.1.1 dos range (0h ? 9_ffffh ) .............................................................. 208 11.1.2 legacy video area (a _0000h?b_ffffh ) .......................................... 208 11.1.3 expansion area (c _0000h?d_ffffh )............................................... 209 11.1.4 extended system bios area (e_0000h?e_ ffffh) .......................... 210 11.1.5 system bios ar ea (f_0000h?f_ ffffh)........................................... 210 11.1.6 programmable attribute map ( pam) memory ar ea details................ 210 11.2 main memory address r ange (1 mb to tol ud) .............................................. 211 11.2.1 isa hole (15 mb?16 mb ) ................................................................... 211 11.2.2 tseg .................................................................................................. 212 11.2.3 pre-allocat ed memo ry......................................................................... 212 11.3 pci memory address r ange (tolud ? 4 gb) ................................................. 212 11.3.1 apic configuration spac e (fec0_0000h-fecf _ffffh) ................. 214 11.3.2 hseg (feda_0000h?f edb_ffffh ) ................................................ 214 11.3.3 fsb interrupt memory space (fee0_0000?f eef_ffff) ................ 214 11.3.4 high bios area .................................................................................. 214 11.3.5 pci express* configurat ion address space (intel ? 82915g/82915p only) ................................................................................................... 215 11.3.6 pci express* graphics attach (intel ? 82915g/82915p only)............ 215 11.3.7 agp dram graphics apertu re .......................................................... 215 11.3.8 graphics memory address ranges (intel ? 82915g/82915gv/82915GL/82910gl gmch only ) ......................... 216 11.4 system management mode (s mm) ................................................................... 216 11.4.1 smm space de finiti on ........................................................................ 217 11.4.2 smm space rest ricti ons .................................................................... 217 11.4.3 smm space comb inati ons ................................................................. 218 11.4.4 smm control co mbinati ons................................................................ 218 11.4.5 smm space decode and tr ansaction h andling ................................ 219 11.4.6 processor wb transaction to an enabled smm address space ...... 219 11.4.7 smm access through gtt tlb (intel ? 82915g/82915gv/82910gl gmch only ) ....................................................................................... 219 11.4.8 memory s hadowing ............................................................................ 219 11.4.9 i/o address space.............................................................................. 220 r datasheet 9 11.4.10 pci express* i/o address mapping (intel ? 82915g/82915p/82915pl only) ................................................................................................... 220 11.4.11 (g)mch decode rules and cross- bridge addre ss mappi ng ............ 220 11.4.12 legacy vga and i/o range decode ru les ....................................... 221 12 functional de scripti on .................................................................................................... 223 12.1 host inte rface ..................................................................................................... 223 12.1.1 fsb gtl+ term inatio n....................................................................... 223 12.1.2 fsb dynamic bus inversio n ............................................................... 223 12.1.3 apic cluster m ode suppor t ............................................................... 224 12.2 system memory controlle r................................................................................. 224 12.2.1 memory organiza tion m odes.............................................................. 224 12.3 system memory configurat ion registers overvi ew .......................................... 226 12.3.1 dram technologies and organiza tion .............................................. 227 12.3.1.1 rules for populati ng dimm sl ots ...................................... 227 12.3.1.2 system memory support ed configur ations ...................... 228 12.3.1.3 main memory dram address translation and decoding 228 12.3.2 dram clock g eneratio n .................................................................... 231 12.3.3 suspend-to-ram and resu me........................................................... 231 12.3.4 ddr2 on-die te rminatio n.................................................................. 231 12.3.5 ddr2 off-chip driver impedance calib ration .................................... 231 12.4 pci express* (intel ? 82915g/82915p82915pl only)........................................ 232 12.4.1 transaction layer ............................................................................... 232 12.4.2 data link layer................................................................................... 232 12.4.3 physical layer..................................................................................... 232 12.5 intel ? serial digital video output (sdvo) (intel ? 82915g/82915gv/82915GL/82910gl gmch only )......................................... 233 12.5.1 intel ? sdvo capab ilities ..................................................................... 233 12.5.2 intel ? sdvo modes ............................................................................ 234 12.6 integrated graphics device (intel ? 82915g/82915gv/82915GL/82910gl gmch only ) ....................................................................................................... 235 12.6.1 3d engi ne ........................................................................................... 236 12.6.2 setup e ngine ...................................................................................... 236 12.6.2.1 3d primitives and data formats support .......................... 236 12.6.2.2 pixel accurate ?fast? scissoring and clipping operation . 237 12.6.2.3 depth bi as ......................................................................... 237 12.6.2.4 backface cu lling................................................................ 237 12.6.2.5 scan conver ter.................................................................. 237 12.6.2.6 pixel rasterizat ion rule s .................................................. 237 12.6.2.7 2d functi onality................................................................. 237 12.6.3 texture e ngine .................................................................................... 238 12.6.3.1 perspective correct texture s upport ................................ 238 12.6.3.2 texture format s and stor age ........................................... 238 12.6.3.3 texture deco mpressi on .................................................... 238 12.6.3.4 texture chro makey .......................................................... 238 12.6.3.5 anti-alia sing....................................................................... 238 12.6.3.6 texture map f ilterin g ........................................................ 238 12.6.3.7 multiple texture composit ion............................................ 239 12.6.3.8 bi-cubic filter (4x4 progra mmable texture filter) ........... 239 12.6.3.9 cubic environm ent mappi ng ............................................. 240 12.6.4 raster e ngine ..................................................................................... 240 12.6.4.1 texture map blending ....................................................... 240 r 10 datasheet 12.6.4.2 combining intrinsic and specular color components ...... 240 12.6.4.3 color shadi ng modes ........................................................ 240 12.6.4.4 color dit hering ................................................................... 241 12.6.4.5 vertex and per pi xel foggi ng............................................ 241 12.6.4.6 alpha blending (fra me buffe r).......................................... 241 12.6.4.7 microsoft directx* api and sgi opengl* api logic ops 242 12.6.4.8 color buffer formats: 8-, 16-, or 32-bits per pixel (destinati on alpha) ............................................................ 242 12.6.4.9 depth bu ffer ...................................................................... 242 12.6.4.10 stencil bu ffer ..................................................................... 243 12.6.4.11 projective textur es............................................................ 243 12.6.5 2d engi ne ........................................................................................... 243 12.6.5.1 gmch vga regi sters....................................................... 243 12.6.5.2 logical 128-bit fixed bl t and 256 fill engine.................. 243 12.6.6 video engi ne....................................................................................... 244 12.6.6.1 hardware motion compensat ion....................................... 244 12.6.6.2 sub-picture support .......................................................... 244 12.6.7 planes ................................................................................................. 245 12.6.7.1 cursor plane ...................................................................... 245 12.6.7.2 overlay plane .................................................................... 245 12.6.7.3 advanced deinterlacing and dynamic bob and weave ... 246 12.6.8 pipes ................................................................................................... 246 12.6.8.1 clock generator units (d pll) .......................................... 246 12.7 display interfaces (intel ? 82915g/82915gv/82915GL/ 82910gl gmch only)247 12.7.1 analog display port characteri stics ................................................... 249 12.7.1.1 integrated ramdac.......................................................... 249 12.7.1.2 sync si gnals ...................................................................... 249 12.7.1.3 vesa/vga mode .............................................................. 249 12.7.1.4 ddc (display da ta channel ) ............................................ 250 12.7.2 digital display interfac e ...................................................................... 250 12.7.2.1 digital display channels ? sdvob and sdvoc.............. 250 12.7.2.2 add2 ca rd ........................................................................ 250 12.7.3 multiple display configurat ions .......................................................... 252 12.8 power m anagement ........................................................................................... 253 12.9 clocki ng.............................................................................................................. 253 13 electrical char acterist ics................................................................................................. 255 13.1 absolute maxi mum rati ngs................................................................................ 255 13.2 power characte ristics ........................................................................................ 257 13.3 signal gr oups..................................................................................................... 259 13.4 dc characteri stics ............................................................................................. 262 13.4.1 general dc charac teristic s ................................................................ 262 13.4.2 rgb/crt dac display dc characteristics (intel ? 82915g/82915gv/82915GL/82910gl gmch only ) ......................... 265 14 ballout and package informat ion .................................................................................... 267 14.1 ddr2 ball out...................................................................................................... 267 14.2 ddr ball out........................................................................................................ 329 14.3 package inform ation .......................................................................................... 395 15 testab ility .................................................................................................................... .... 399 15.1 complimentar y pins ........................................................................................... 399 r datasheet 11 15.2 xor test mode initia lization fo r ddr ................................................................ 400 15.3 xor test mode initia lization fo r ddr2 .............................................................. 400 15.4 xor chain de finition ......................................................................................... 401 15.5 ddr xor c hains............................................................................................... 401 15.6 ddr2 xor c hains............................................................................................. 414 15.7 pads excluded from xor mode( s) ................................................................... 426 figures figure 1-1. intel ? 915g express chipset system block diagram example ..................... 18 figure 1-2. intel ? 915p express chipset system block diagram example ..................... 19 figure 1-3. intel ? 915gv express chipset system block diagram example................... 20 figure 1-4. intel ? 910gl express chipset system block diagram example ................... 21 figure 1-5. intel ? 915pl express chipset system block diagram example ................... 22 figure 1-6. intel ? 915GL express chipset system block diagram example ................... 23 figure 2-1. intel ? (g)mch signal inte rface di agram ........................................................ 34 figure 3-1. conceptual chipset pci configurat ion diagr am............................................ 55 figure 3-2. register organizati on (representative of the intel ? 82915g gmch) ........... 57 figure 3-3. dmi type 0 configur ation address translati on ............................................. 59 figure 3-4. dmi type 1 configur ation address translati on ............................................. 59 figure 3-5. memory map to pci expre ss* device confi guration s pace .......................... 60 figure 3-6. intel ? 915x gmch configurati on cycle flow chart ......................................... 62 figure 6-1. link de claration topology ............................................................................ 109 figure 11-1. system address ranges ............................................................................ 207 figure 11-2. microsoft ms-d os* legacy addr ess r ange ............................................. 208 figure 11-3. main memo ry addre ss range .................................................................... 211 figure 11-4. pci memo ry addre ss range ...................................................................... 213 figure 12-1. system memory st yles............................................................................... 225 figure 12-2. integrated graphi cs device blo ck diagr am ............................................... 235 figure 12-3. system clocking ex ample.......................................................................... 254 figure 14-1. intel ? 82915g gmch ballout for ddr2 (top view: columns 1?12) ......... 268 figure 14-2. intel ? 82915g gmch ballout for ddr2 (top view: columns 13?24) ....... 269 figure 14-3. intel ? 82915g gmch ballout for ddr2 (top view: columns 25?35) ....... 270 figure 14-4. intel ? 82915g gmch ballout for ddr (t op view: colu mns 1?12 ) .......... 330 figure 14-5. intel ? 82915g gmch ballout for ddr (top view: columns 13?24 ) ........ 331 figure 14-6. intel ? 82915g gmch ballout for ddr (top view: columns 25?35 ) ........ 332 figure 14-7. (g)mch pa ckage dimens ions ................................................................... 396 figure 14-8. (g)mch component keep-out rest ricti ons .............................................. 397 figure 15-1. xor test mode initializati on cycl es .......................................................... 400 r 12 datasheet tables table 2-1. host interfac e reset and s3 states ................................................................ 46 table 2-2. system memory (ddr2) reset and s3 states ............................................... 47 table 2-3. system memory (ddr) reset and s3 states ................................................. 49 table 2-4. pci express* graphics x16 port reset and s3 st ates ................................... 50 table 2-5. dmi rese t and s3 st ates ................................................................................ 50 table 2-6. clocking re set and s3 states......................................................................... 51 table 2-7. misc re set and s3 states.............................................................................. 51 table 2-8. dac reset and s3 states (intel ? 82915g/82915gv/82915GL/82910gl gmch onl y) ............................................................................................................... 51 table 3-1. device number assignment for internal (g )mch devi ces ............................. 57 table 4-1. device 0 function 0 register addre ss map su mmary.................................... 65 table 6-1. egress port r egister addr ess map ............................................................... 109 table 7-1. dmi register address m ap summa ry ........................................................... 115 table 8-1. host-pci express* graphics br idge register addre ss map (d1: f0) ........... 125 table 9-1. integrated graphics device register address map (d2: f0)......................... 173 table 10-1. device 2 function 1 register addre ss map su mmary ............................... 193 table 11-1. expansion ar ea memory s egments ............................................................ 209 table 11-2. extended system bi os area memory segments ....................................... 210 table 11-3. system bios area memory segment s ....................................................... 210 table 11-4. pre-allocated memory exam ple for 64-mb dram, 1-mb vga and 1-mb tseg ....................................................................................................................... 212 table 11-5. smm space t able ....................................................................................... 218 table 11-6. smm c ontrol t able...................................................................................... 218 table 12-1. sample system memory organization with in terleaved c hannels ............. 225 table 12-2. sample system memory or ganization with asy mmetric c hannels ............ 225 table 12-3. ddr / ddr2 dimm s upported confi gurati ons ........................................... 228 table 12-4. dram address translation (s ingle channel/dual asymmetric mode) ...... 229 table 12-5. dram address translati on (dual channel sy mmetric mode) ................... 230 table 12-6. display port characteri stics ........................................................................ 248 table 12-7. analog port characteri stics ......................................................................... 249 table 13-1. absolute maximum ratings ......................................................................... 255 table 13-2. non-memory po wer characte ristics............................................................ 257 table 13-3. ddr power characteri stics ......................................................................... 258 table 13-4. ddr2 power characteri stics ....................................................................... 258 table 13-5. si gnal gr oups .............................................................................................. 259 table 13-6. dc characteristics 3 ..................................................................................... 262 table 13-7. rgb/crt dac display dc charac teristics (functional operating range: vcca_dac = 2.5 v 5%) ....................................................................................... 265 table 14-1. gmch/mch ballout for ddr2 systems (sorted by ball number).............. 271 table 14-2. gmch/mch ballout for ddr2 systems (sorted by signal name)............. 300 table 14-3. gmch/mch ballout for ddr sy stems (sorted by ball num ber)................ 333 table 14-4. gmch/mch ballout for ddr sy stems (sorted by signal name)............... 365 table 15-1. complimentar y pins to drive ....................................................................... 399 table 15-2. xor chain ou tputs for bot h ddr and ddr2............................................. 401 table 15-3. ddr xo r chain #0..................................................................................... 402 table 15-4. ddr xo r chain #1..................................................................................... 404 table 15-5. ddr xo r chain #2..................................................................................... 406 table 15-6. ddr xo r chain #3..................................................................................... 407 table 15-7. ddr xo r chain #4..................................................................................... 408 table 15-8. ddr xo r chain #5..................................................................................... 409 table 15-9. ddr xo r chain #6..................................................................................... 410 r datasheet 13 table 15-10. ddr xo r chain #7................................................................................... 411 table 15-11. ddr xo r chain #8................................................................................... 412 table 15-12. ddr xo r chain #9................................................................................... 413 table 15-13. ddr2 xor chai n #0................................................................................. 414 table 15-14. ddr2 xor chai n #1................................................................................. 416 table 15-15. ddr2 xor chai n #2................................................................................. 418 table 15-16. ddr2 xor chai n #3................................................................................. 419 table 15-17. ddr2 xor chai n #4................................................................................. 420 table 15-18. ddr2 xor chai n #5................................................................................. 421 table 15-19. ddr2 xor chai n #6................................................................................. 422 table 15-20. ddr2 xor chai n #7................................................................................. 423 table 15-21. ddr2 xor chai n #8................................................................................. 424 table 15-22. ddr2 xor chai n #9................................................................................. 425 table 15-23. xor pad exclusion list............................................................................. 426 r 14 datasheet revision history rev description date -001 ? initial release june 2004 -002 ? added intel ? 82915gv gmch ? minor edits throughout for clarity september 2004 -003 ? added intel ? 82910gl gmch september 2004 -004 ? added intel ? 82915GL gmch ? added intel ? 82915pl gmch january 2005 -005 ? minor edits throughout for clarity february 2005 r datasheet 15 intel ? 82915g/82915gv/82915GL/ 82910gl/82915p/82915pl (g)mch features ? processor interface ? one intel ? pentium ? 4 processor or intel ? celeron ? d processor including 775-land package. ? supports pentium 4 processor fsb interrupt delivery ? 533 mt/s (133 mhz) fsb (82915g/82915gv/ 82915GL/82910gl/82915p/82915pl) and 800 mt/s (200 mhz) fsb (82915g/82915gv/ 82915GL/82915p/82915pl only) ? fsb dynamic bus inversion (dbi) ? 32-bit host bus addressing for access to 4 gb of memory space ? 12-deep in-order queue ? 1-deep defer queue ? gtl+ bus driver with integrated gtl termination resistors ? supports a cache line size of 64 bytes ? system memory ? one or two 64-bit wide ddr/ddr2 sdram data channels (82915pl and 82910gl supports ddr 400 or ddr 333, 1 dimm, 2 channels only) (82915pl supports ddr only) ? bandwidth up to 8.5 gb/s (ddr/ddr2 533) in dual-channel interleaved mode. ? non-ecc memory only. ? 256-mb, 512-mb and 1-gb ddr/ddr2 technologies ? only x8, x16, ddr/ddr2 devices with four banks and also supports eight bank, 1-gbit ddr2 devices. ? opportunistic refresh ? up to 64 simultaneously open pages (four ranks of eight bank devices* 2 channels) ? spd (serial presence detect) scheme for dimm detection support ? suspend-to-ram support using cke ? supports configurations defined in the jedec ddr/ddr2 dimm sp ecification only ? pci express* graphics interface (82915g/82915p/82915pl only) ? one x16 pci express port ? compatible with the pci express base specification revision 1.0a ? integrated graphics device (82915g/82915gv/82915GL/82910gl only) ? core frequency of 333 mhz ? high-quality 3d setup and render engine ? high-quality texture engine ? video dvd/pc-vcr ? 3d graphics rendering enhancements ? 2d graphics ? video overlay ? multiple overlay functionality ? analog display support (82915g/82915gv/82915GL/82910gl only) ? 400 mhz integrated 24-bit ramdac ? up to 2048x1536@ 85 hz refresh ? hardware color cursor support ? ddc2b compliant interface ? digital display support (82915g/82915gv/82915GL/82910gl only) ? two sdvo ports multiplexed with pci express graphics interface (82915g only) ? 200 mhz dot clock on each 12-bit interface ? can combine two channels to form one larger interface (82915g only) ? flat panels up to 2048x1536@ 85hz or digital crt/hdtv at 1920x1080@ 85hz ? dual independent display options with digital display. (82915g only) ? multiplexed digital display channels (supported with add2 card). (82915g only) ? supports tmds transmitters or tv-out encoders ? add2 card uses pci express graphics x16 connector (82915g only) ? dmi interface ? a chip-to-chip connec tion interface to intel ? ich6 ? 2 gb/s point-to-poi nt dmi to ich6 (1 gb/s each direction) ? 100 mhz reference clock (shared with pci express graphics attach). ? 32-bit downstream addressing ? messaging and error handling ? package ? 37.5 mm 37.5 mm., 1210 balls, variable ball pitch r 16 datasheet introduction r datasheet 17 1 introduction the intel ? 91x express chipset family is designed for use with the intel ? pentium ? 4 processor / intel ? celeron ? d processor (intel ? 915g/915gv/915GL/915p/915pl chipsets) or intel ? celeron ? processor (intel ? 910gl chipset) in desktop platforms. each chipset in the family contains two components: gmch (or mch) for the host bridge and i/o controller hub 6 (ich6) for the i/o subsystem. the 82915g gmch is part of the 915g express chipset, the 82915gv is part of the 915gv express chipset, the 82915GL is part of the 915GL express chipset, the 82910gl is part of the 910gl express chipset, the 82915p mch is part of the 915p express chipset, and the 82915pl is part of the 915pl express chipset. the ich6 is the sixth generation i/o controller hub and provides a multitude of i/o related functions. figure 1-1 shows an example system block diagram for the 915g express chipset, figure 1-2 shows an example system block diagram for the 915p express chipsets, figure 1-3 shows an example system block diagram for the 915gv express chipset, figure 1-4 shows an example system block diagram for the 910gl express chipsets, figure 1-5 shows an example system block diagram for the 915pl express chipsets, and figure 1-6 shows an example system block diagram for the 915GL express chipsets. this document is the datasheet for the intel ? 82915g graphics and memory controller hub (gmch), intel ? 82915gv graphics and memory controller hub (gmch), intel ? 82915GL graphics and memory controller hub (gmch), intel ? 82910gl graphics and memory controller hub (gmch), intel ? 82915p memory controller hub (mch), and the intel ? 82915pl memory controller hub (mch). topics covered include; signal description, system memory map, pci register description, a description of the (g)mch inte rfaces and major functional units, electrical characteristics, ballout defi nitions, and package characteristics. the difference between the 82915g gmch and 82915p mch is that the 82915g gmch contains an integrated graphi cs port (and associated sdvo a nd analog display ports) and the 82915p mch does not contain these items. both devices support pci express graphics. the 82915gv gmch contains an integrated graphics port (and associated sdvo and analog display ports), but does not support pci express graphics. the 82915GL gmch has the same features as the 82915gv gmch, but only supports ddr memory. the 82915pl gmch has the same features as the 82915p gmch, but only supports 2 channels of ddr dimm memory to a maximum of 1-dimm per channel. the 82910gl gmch supports only 533 mhz fsb, contains an integrated graphics port (and associated sdvo and analog display ports), does not support pci express graphics, and supports only 2 channels of ddr dimm memory to a maximum of 1- dimm per channel. note: unless otherwise specified, the information in this document applies to the 82915g graphics and memory controller hub (gmch), 82915gv graphics and memory controller hub (gmch), 82915gv graphics and memory controller hub (gmch), 82910gl graphics and memory controller hub (gmch), 82915pl memory controller hub (mch), and the 82915p memory controller hub (mch). note: references in this document to pci express are for the 82915g, 82915p, and the 82915pl only. note: references in this document to the integrated graphics device (igd) are for the 82915g, 82915gv, 82915GL, and 82910gl only. introduction r 18 datasheet note: references in this document to ddr2 memory are for the 82915g, 82915gv, and 82915p only. note: unless otherwise specified, ich6 refers to the intel ? 82801fb ich6, 82801fr ichr, 82801fw ich6w, and 82801frw ich6rw i/o controller hub 6 components. figure 1-1. intel ? 915g express chipset system block diagram example intel ? pentium ? 4 processor or intel ? celeron ? d processor intel ? 82915g gmch ddr or ddr2 ddr or ddr2 ddr or ddr2 ddr or ddr2 channel a 533/800 mhz fsb display dmi interface sys_blk_g channel b graphics card pci express x16 graphics intel ? 915g express chipset system memory display add2 card display or sdvo intel ? ich6 usb 2.0 8 ports, 480 mb/s gpio 4 serial ata ports 150 mb/s 2 ata 100 ports sio flash bios pci bus seven pci masters ac '97 3 codec support lpc interface power management clock generation system management (tco) lan connect/asf smbus 2.0/i 2 c vga analog display introduction r datasheet 19 figure 1-2. intel ? 915p express chipset system block diagram example intel ? pentium ? 4 processor or intel ? celeron ? d processor intel ? 82915p mch ddr or ddr2 ddr or ddr2 ddr or ddr2 ddr or ddr2 channel a 533/800 mhz fsb dmi interface sys_blk_p channel b graphics card pci express x16 graphics intel ? 915p express chipset system memory display intel ? ich6x usb 2.0 8 ports, 480 mb/s 4 sata ports 150 mb/s ide sio flash bios pci bus seven pci masters ac '97/intel ? high definition audio codecs lpc interface power management clock generation system management (tco) lan connect/asf smbus 2.0/i 2 c gpio pci express* x1 intel ? pci express gigabit ethernet introduction r 20 datasheet figure 1-3. intel ? 915gv express chipset system block diagram example intel ? pentium ? 4 processor or intel ? celeron ? d processor intel ? 82915gv gmch ddr or ddr2 ddr or ddr2 ddr or ddr2 ddr or ddr2 channel a 533/800 mhz system bus display dmi interface sys_blk_gv channel b intel ? 915gv express chipset system memory display add2 card sdvo intel ? ich6 usb 2.0 8 ports, 480 mb/s gpio 4 serial ata ports 150 mb/s 2 ata 100 ports sio flash bios pci bus seven pci masters ac '97 3 codec support lpc interface power management clock generation system management (tco) lan connect/asf smbus 2.0/i 2 c vga analog display introduction r datasheet 21 figure 1-4. intel ? 910gl express chipset system block diagram example intel ? celeron ? d processor intel ? 82910gl gmch ddr ddr channel a 533 mhz system bus display dmi interface sys_blk_gl channel b intel ? 910gl express chipset system memory display add2 card sdvo intel ? ich6 usb 2.0 8 ports, 480 mb/s gpio 4 serial ata ports 150 mb/s 2 ata 100 ports sio flash bios pci bus seven pci masters ac '97 3 codec support lpc interface power management clock generation system management (tco) lan connect/asf smbus 2.0/i 2 c vga analog display introduction r 22 datasheet figure 1-5. intel ? 915pl express chipset system block diagram example intel ? pentium ? 4 processor or intel ? celeron ? d processor intel ? 82915pl mch ddr ddr channel a 533/800 mhz fsb dmi interface sys_blk_p channel b graphics card pci express* x16 graphics intel ? 915pl express chipset system memory display intel ? ich6x usb 2.0 8 ports, 480 mb/s 4 sata ports 150 mb/s ide sio flash bios pci bus seven pci masters ac '97/intel ? high definition audio codecs lpc interface power management clock generation system management (tco) lan connect/asf smbus 2.0/i 2 c gpio pci express* x1 intel ? pci express gigabit ethernet introduction r datasheet 23 figure 1-6. intel ? 915GL express chipset system block diagram example intel ? pentium ? 4 processor or intel ? celeron ? d processor intel ? 82915GL gmch ddr ddr ddr ddr channel a 533/800 mhz system bus display dmi interface sys_blk_gv channel b intel ? 915GL express chipset system memory display add2 card sdvo intel ? ich6 usb 2.0 8 ports, 480 mb/s gpio 4 serial ata ports 150 mb/s 2 ata 100 ports sio flash bios pci bus seven pci masters ac '97 3 codec support lpc interface power management clock generation system management (tco) lan connect/asf smbus 2.0/i 2 c vga analog display introduction r 24 datasheet 1.1 terminology term description add2 card advanced digital display card ? 2 nd generation. provides digi tal display options for an intel graphics controller that supports add2 cards. this card plugs into a x16 pci express connector but uses the multiplexed sdvo interface. will not work with an intel graphics controller that supports dvo and add cards. core core refers to the internal base logic in the (g)mch. crt cathode ray tube. dbi dynamic bus inversion. ddr double data rate sdram memory technology. ddr2 a second generation double data rate sdram memory technology. dmi the direct media interface is the connection between the (g)mch and the intel ? ich6. dvi digital video interface. this is the specific ation that defines the connector and interface for digital displays. fsb front side bus. the fsb is synonymous with host or processor bus full reset full reset is when pwrok is de-asserted. warm reset is when both rstin# and pwrok are asserted. gmch graphics memory controller hub component that contains the processor interface, dram controller, and integrated graphics dev ice. it may also contain an x16 pci express port (typically the external graphics interface). it communicates with the i/o controller hub (ich6*) over the dmi in terconnect. throughout this document gmch refers to the intel ? 82915g gmch, 82915gv gmch, 82915GL, and 82910gl, unless otherwise specified. note that term (g)mch is used when referring to both gmch and mch components. hdmi high definition multimedia interface. hdmi supports standard, enhanced, or high- definition video, plus multi-channel digital audi o on a single cable. it transmits all atsc hdtv standards and supports 8- channel digital audio, with bandwidth to spare for future requirements and enhancements (addi tional details are available through www.hdmi.org ) host this term is used synonymously with processor. intx an interrupt request signal where x stands for interrupts a,b,c, and d. intel ? ich6 sixth generation i/o controller hub component that contains additional functionality compared to previous ich6s. the intel ? i/o controller hub component contains the primary pci interface, lpc interface, usb2, ata-100, and other i/o functions. it communicates with the gmch over a proprietary interconnect called dmi. igd internal graphics device. lcd liquid crystal display. lvds low voltage differential signaling. a high speed, low power data transmission standard used for display connections to lcd panels. introduction r datasheet 25 term description mch the memory controller hub (mch) component contains the processor interface and dram controller; however, it does not c ontain an internal graphics device like the gmch. it may also contain an x16 pci expr ess port (typically the external graphics interface). it communicates with the i/o controller hub (ich6*) and other i/o controller hubs over the dmi interconnect. throughout this document the term mch refers to the 82915p and 82915pl mch. note: (g)mch is used when referring to both gmch and mch components. msi message signaled interrupt. a transaction initia ted outside the host, conveying interrupt information to the receiving agent through the same path that normally carries read and write commands. pci express* third generation input output (pci expr ess) graphics attach called pci express graphics. a high-speed serial interface whose c onfiguration is software compatible with the existing pci specificati ons. the specific pci express implementation intended for connecting the gmch to an external graphics c ontroller is a x16 link and replaces agp. primary pci the physical pci bus that is driven dire ctly by the ich6 component. communication between primary pci and the gmch occurs over dmi. note that the primary pci bus is not pci bus 0 from a configuration standpoint. sci system control interrupt. sci is used in acpi protocol. sdvo serial digital video out (sdvo) . digital display channel that serially transmits digital display data to an external sdvo device. the sdvo device accepts this serialized format and then translates the data into the appropriate display format (i.e., tmds, lvds, tv-out). this interface is not electric ally compatible with the previous digital display channel - dvo. for the intel ? 82915g gmch, the sdvo interface is multiplexed on a portion of the x16 graphics pci express interface. sdvo device third party codec that uses sdvo as an i nput. an sdvo device may have a variety of output formats including: dvi, lvds, hdmi, tv-out, etc. serr an indication that an unrecoverabl e error has occurred on an i/o bus. smi system management interrupt. smi is used to i ndicate any of several system conditions (such as thermal sensor events, throttli ng activated, access to system management ram, chassis open, or other system state related activity). rank a unit of dram corresponding to eight x8 s dram devices in parallel or four x16 sdram devices in parallel, ignoring ecc. these devices are usually, but not always, mounted on a single side of a dimm. tmds transition minimized differential signaling. signaling interface from silicon image that is used in dvi and hdmi. tolm top of low memory. the highest address below 4 gb for which a processor-initiated memory read or write transaction will create a corresponding cycle to dram on the memory interface. vco voltage controlled oscillator. uma unified memory architecture. uma describes an igd using system memory for its frame buffers. introduction r 26 datasheet 1.2 reference documents document title document number/location intel ? 915g/915gv/910gl express chip set thermal design guide http://intel.com/design/chip sets/designex/301469.htm intel ? i/o controller hub 6 (ich6) family datasheet http://developer.intel.com/d esign/chipsets/datashts/30 1473.htm advanced configuration and powe r interface specification, version 2.0 http://www.acpi.info/ advanced configuration and powe r interface specification, version 1.0b http://www.acpi.info/ the pci local bus specification, version 2.3 http://www.pcisig.com/spe cifications pci express* specification, version 1.0a http://www.pcisig.com/spe cifications 1.3 gmch (mch) overview the (g)mch connects to the processor as shown in figure 1-1, figure 1-2, figure 1-3, figure 1-4, figure 1-5, and figure 1-6. a major role of the (g)mch in a system is to manage the flow of information between its interfaces : the processor interface (fsb), the system memory interface (dram controller), the integrated gr aphics interface ( 82915g/82915gv/82915GL/82910gl gmch only), the external graphics inte rface via pci express (82915g/82915p/82915pl mch only), and the i/o controller h ub through the dmi interface. this includes arbitrating between the interfaces when each initiates transactions. the (g)mch supports one or two channels of ddr (82915g/82915gv/82915GL/82915p/82915pl/82910gl) or ddr2 (82915g/82915gv/82915p) sdram. the (g)mch also supports the new pci express based external graphics attach. thus, the 915g/915gv/915GL/910gl/915p and 915pl express chipsets are not compatible with agp (1x, 2x, 4x, or 8x). to increase system performance, the (g)mch incorporates severa l queues and a write cache. the (g)mch also contains advanced desktop power management logic. 1.3.1 host interface the (g)mch is optimized for both the pentium 4 processors in the lga775 socket and the celeron d processor in the fc-mpga4 socket. the (g)mch can use a single lga 775 socket processor. the (g)mch supports fsb frequency of 533/800 mt/s (133/200 mhz hclk) using a scalable fsb vcc_cpu (82910gl only supports 533 mt/s, 133 mhz hclk). the (g)mch supports the pentium 4 processor subset of the extended mode scaleable bus protocol. the primary enhancements over the compatible mode p6 bus protocol are: source synchronous double-pumped (2) address and source sy nchronous quad-pumped (4x) data. the (g)mch supports 32-bit host addressing, decoding up to 4 gb of the processor?s memory address space. host-initiated i/o cycles are d ecoded to pci express, dmi, or the (g)mch introduction r datasheet 27 configuration space. host-initiated memory cycles are decoded to pci express, dmi, or system memory. pci express device accesses to non-cacheab le system memory are not snooped on the host bus. memory accesses initiated from pci expr ess using pci semantics and from dmi to system memory will be snooped on the host bus. 1.3.2 system memory interface the (g)mch integrates a system memory ddr/ddr2 controller with two, 64-bit wide interfaces (82910gl, 82915pl, and 82915GL supports ddr only). only double data rate (ddr/ddr2) memory is supported; conseque ntly, the buffers support only sstl_2/1.8 v signal interfaces. the memory controller interface is fully configurable th rough a set of control registers. features of the (g)mch memory controller include: ? the (g)mch system memory controller directly supports one or two channels of memory (each channel consisting of 64 data lines). ? supports two memory addressing organization options: ? the memory channels are asymmetric: "st acked" channels are assigned addresses serially. channel b addresses are assi gned after all channel a addresses. ? the memory channels are interleaved: addresses are ping-ponged between the channels after each cache line (64-b boundary). ? available bandwidth up to: ? 3.2 gb/s (ddr/ddr2 400) for single-channel mode ? 6.4 gb/s in dual-channel interleaved mode assuming ddr or ddr2 400 mhz. ? 8.5 gb/s in dual-channel interleaved mode assuming ddr2 533 mhz. ? supports ddr memory dimm frequencies of 333 mhz and 400 mhz or ddr2 memory dimm frequencies of 400 mhz and 533 mhz. all dimms in a system must be of the same type (e.g., all ddr or all ddr2, not mixed). the speed used in all channels is the speed of the slowest dimm in the system. ? 82910gl supports ddr memory only, dimm frequencies of 333 mhz and 400 mhz, dual channel mode, 1-dimm maximum per channel. ? i/o voltage of 2.6 v for ddr, and 1.8 v for ddr2. ? supports non-ecc memory only. ? supports 256-mb, 512-mb and 1-gb ddr/ddr2 technologies ? supports only x8, x16, ddr/ddr2 devices with four banks and also supports eight bank, 1-gbit ddr2 devices. ? supports opportunistic refresh ? in dual channel mode the (g)mch supports 64 simultaneously open pages (four ranks of eight bank devices* 2 channels) ? supports partial writes to memory using data mask (dm) signals. ? supports page sizes of 4 kb, 8 kb and 16 kb. ? supports a burst length of 8 for single-channel and dual-channel interleaved and asymmetric operating modes. ? supports unbuffered dimms. ? spd (serial presence detect) scheme for dimm detection support ? suspend-to-ram support using cke ? supports configurations defined in the jedec ddr/ddr2 dimm specification only introduction r 28 datasheet by using 256-mb technology, the smallest memory capacity possible is 128 mb, assuming single- channel mode. (16m rows * 16b/(row*device) * 4 devices/dimm-side * 1 dimm-side/channel * 1 channel *1b/8b = 128 mb). by using 1-gb technology in dual-channel interleaved mode, the largest memory capacity possible is 8 gb. (128m rows * 8b/(row*device) * 8 devices/dimm- side * 4 dimm-sides/channel * 2 channels * 1b/8b * 1g/1024m = 8 gb). this exceeds a 32-bit address limit of 4 gb. in a 32-bit system, only th e first 4 gb of memory will be accessible. the (g)mch supports a memory thermal management scheme to selectively manage reads and/or writes. memory thermal management can be triggered either by on-die thermal sensor, or by preset limits. management limits are determined by weighted sum of various commands that are scheduled on the memory interface. 1.3.3 direct media interface (dmi) direct media interface (dmi) is the chip-to-ch ip connection between the (g)mch and ich6. this high-speed interface integrat es advanced priority-based se rvicing allowing for concurrent traffic and true isochronous transfer capabilities. base functionality is completely software transparent permitting current and legacy software to operate normally. to provide for true isochronous transfers and conf igurable quality of service (qos) transactions, the ich6 supports two virtual channels on dmi: vc0 and vc1. these two channels provide a fixed arbitration scheme where vc1 is always the highest priority. vc0 is the default conduit of traffic for dmi and is always enabled. vc1 must be specifically enabled and configured at both ends of the dmi link (i.e., the ich6 and (g)mch). features of the dmi include: ? a chip-to-chip connecti on interface to ich6 ? 2 gb/s point-to- point dmi to ich6 (1 gb/s each direction) ? 100 mhz reference clock (shared with pci express graphics attach). ? 32-bit downstream addressing ? apic and msi interrupt messaging support. will send intel-defined ?end of interrupt? broadcast message when initiated by the processor. ? message signaled interrupt (msi) messages ? smi, sci and serr error indication ? legacy support for isa regime protocol (phold/pholda) required for parallel port dma, floppy drive, and lpc bus masters 1.3.4 pci express* graphics interface (intel ? 82915g/82915p/ and 82915pl only) the (g)mch (82915g, 82915p, and 82915pl only) contains a 16-lane (x16) pci express port intended for an external pci express graphics card . the pci express port is compatible with the pci express base specification revision 1.0a. the x16 port operates at a frequency of 2.5 gb/s on each lane while employing 8b/10b encoding, and supports a maximu m theoretical bandwidth of 4 gb/s each direction. the 82915g gmch multiple xes the pci express interface with two intel ? sdvo ports. introduction r datasheet 29 features of the pci express interface include: ? one x16 pci express port intended for graphics attach, compatible with the pci express base specification revision 1.0a. ? theoretical pci express transfer rate of 2.5 gb/s. ? raw bit-rate on the data pins of 2.5 gb/s, resulting in a theoretical bandwidth per pair of 250 mb/s given the 8b/10b encoding used to transmit data across this interface ? maximum theoretical realized bandwidth on the interface of 4 gb/s in each direction simultaneously, for an aggregate of 8 gb/s when (1)x16. ? pci express graphics extended configuration space. the firs t 256 bytes of configuration space alias directly to the pci compatibility configuration space. the remaining portion of the fixed 4-kb block of memo ry-mapped space above that (s tarting at 100h) is known as extended configuration space. ? pci express enhanced addressing mechanism. accessing the device configuration space in a flat memory mapped fashion. ? automatic discovery, negotiation, and training of link out of reset ? supports traditional pci style traffic (asynchronous snooped, pci ordering) ? supports traditional agp style traffic (asy nchronous non-snooped, pc i express-relaxed ordering) ? hierarchical pci-compliant configuration mechanism for downstream devices (i.e., normal pci 2.3 configuration space as a pci-to-pci bridge) ? supports ?static? lane numbering reversal. this method of lane reversal is controlled by a hardware reset strap, and reve rses both the receivers and transmitters for all lanes (e.g., tx15->tx0, rx15->rx0). this method is transparent to all external devices and is different than lane reversal as defined in the pci express specification. in particular, link initialization is not affected by static lane reversal. 1.3.5 integrated graphics (intel ? 82915g/82915gv/82910gl/82915GL gmch only) the 82915g/82915gv/82910gl/915GL gmch provides an integrated graphics device (igd) delivering cost competitive 3d, 2d and video capabilities. the gmch contains an extensive set of instructions for 3d operations, blt and stretch blt operations, motion compensation, overlay, and display control. the gmch?s vide o engines support video conferencing and other video applications. the gmch doe s not support a dedicated local graphics memory interface, it may only be used in a uma configuration. the gmch also has the capab ility to support external graphics accelerators via the pci express graphics port but cannot work concurrently with the integrated graphics devce. high bandwidth access to data is provided through the system memory port. the gmch also provides 3d hardware accelera tion for block level transfers of data (blts). 2d blts are considered a special case of 3d transfers and use the 3d acceleration. the blt engine provides the ability to copy a source block of data to a destination and perform raster operations (e.g., rop1, rop2, and rop3) on the data using a pattern, and/or another destination. performing these common tasks in hardware reduces processor load, and thus improves performance. introduction r 30 datasheet gmch graphics support includes: ? core frequency of 333 mhz ? high quality 3d setup and render engine ? setup matching processor geometry delivery rates ? triangle lists, strips and fans ? indexed vertex and flexible vertex formats ? vertex cache ? pixel accurate fast scissoring and clipping operation ? backface culling ? supports d3d and opengl pixelization rules ? anti-aliased lines ? sprite points ? zone rendering technology 3 ? shadow maps ? double-sided stencil ? high-quality texture engine ? 533 megatexel/sec performance ? 266 mpixel/sec fill rate up to 2 bilinear textures ? hardware pixel shader 2.0 ? per-pixel perspective corrected texture mapping ? 2/10/10/10 texture format ? bi-cubic filtering ? single-pass quad texture compositing ? enhanced texture blending functions ? 12 levels of detail mip map sizes from 1x1 to 2kx2k ? all texture formats including 32-bit rgba and 8-bit palettes ? alpha and luminance maps ? texture color-keying/chromakeying ? bilinear, trilinear and anisotropic mip-mapped filtering ? cubic environment reflection mapping ? embossed and dot3 bump-mapping ? dxtn and fxt1 texture decompression ? non-power of 2 texture ? render to texture ? video dvd/pc-vcr ? h/w motion compensation for mpeg2 ? dynamic bob and weave support for video streams ? source resolution up to 1920x1080 with 2 vertical taps ? software dvd at 30 fps, full screen ? supports 720x480 dvd quality encoding at low processor utilization for pc-vcr or home ? movie recording and editing ? 3d graphics rendering enhancements ? 1.3 dual texture gigapixel/sec fill rate ? flat and gouraud shading ? color alpha blending for transparency ? vertex and programmable pixel fog and atmospheric effects ? color specular lighting ? z bias support ? dithering ? anti-aliased lines ? 16- and 24-bit z buffering ? 8-bit stencil buffering ? double and triple render buffer support ? 16- and 32-bit color ? destination alpha ? maximum 3d resolution supported: 1600x1200x32@85hz ? fast clear support ? 2d graphics ? optimized 256-bit blt engine ? alpha stretch blitter ? anti-aliased lines ? 32-bit alpha blended cursor ? color space conversion ? programmable 3-color transparent cursor ? 8-, 16- and 32-bit color ? rop support ? video overlay ? advanced deinterlacing ? process amplifier color control ? single high quality scalable overlay ? multiple overlay functionality provided via stretch blitter (pip, video conferencing, etc.) ? 5-tap horizontal, 2-tap vertical filtered scaling ? independent gamma correction ? independent brightness/contrast/saturation ? independent tint/hue support ? destination color-keying ? source chroma-keying ? maximum source resolution: 720x480x32 ? maximum overlay display resolution: 2048x1536x32 ? video mixer render (vmr) introduction r datasheet 31 1.3.6 analog and intel ? sdvo displays (intel ? 82915g/82915gv/82910gl/82915GL gmch only) the gmch provides interfaces to a progressi ve scan analog monitor and two sdvo ports (multiplexed with pci express x16 graphics port signals) capable of driving an add2 card. the digital display channels are capab le of driving a variety of s dvo devices (e.g., tmds, tv-out). note that sdvo only works with the integrat ed graphics device (igd). the gmch provides two sdvo ports that are capable of dr iving up to a 200 mhz pixel clock each. the gmch sdvo ports can each support a single- channel sdvo device. if both ports are active in single-channel mode, they can have different display timing a nd data. alternatively, the sdvo ports can combine to support dual channel devi ces, supporting higher resolutions and refresh rates. the gmch is compliant with dvi specification 1.0. when combined with a dvi compliant external device and connector, the gmch has a high-speed interface to a digital display (e.g., flat panel or digital crt). the gmch supports hot-plug and display for pci express* x16 graphics. this is not supported for add2 cards. 1.3.7 system interrupts the (g)mch interrupt support includes: ? supports both 8259 and pentium 4 processor fsb interrupt delivery mechanisms. ? supports interrupts signaled as upstream memory writes from pci express and dmi ? msis routed directly to fsb ? from i/oxapics 1.3.8 (g)mch clocking the differential fsb clock (hclkp/hclkn) can be set to either 133 mhz or 200 mhz (82915g/82915gv/82915GL/82915p/82915pl only). this supports fsb transfer rates of 533 mt/s and 800 mt/s (82915g/82915gv/82915GL/82915p/82915pl only). the host pll generates 2x, 4x, and 8x versions of the host cl ock for internal optimizations. the (g)mch core clock is synchronized to the host clock. the internal and external memory clocks of 133 mhz and 200 mhz are generated from one of two (g)mch plls that use the host clock as a reference. this includes 2x and 4x for internal optimizations. for the 82915g/82915p/82915pl (g)mch, the pci express core clock of 250 mhz is generated from a separate pci express pll. this clock uses the fixed 100 mhz serial reference clock (gclkp/gclkn) for reference. for the 82915g/82915gv/82915GL/82910gl gmch, display timings are generated from display plls that use a 96 mhz differential non-spread spectrum clock as a reference. display plls can also use the sdvo_tvclkin[+/-] from an sdvo device as a reference. introduction r 32 datasheet all of the above mentioned clocks are capable of tolerating spread spectrum clocking as defined in the clock generator specification. host, me mory, and pci express* x16 graphics plls, and all associated internal clocks are disabled until pwrok is asserted. 1.3.9 power management (g)mch power management support includes: ? pc99 suspend to dram support (?str?, mapped to acpi state s3) ? smram space remapping to a0000h (128 kb) ? supports extended smram space above 256 mb, a dditional 1-mb tseg from the base of graphics stolen memory (b sm) when enabled, and cacheab le (cacheability controlled by processor) ? acpi rev 1.0 compatible power management ? supports processor states: c0, c1, c2, c3, and c4 ? supports system states: s0, s1, s3, s4, and s5 ? supports processor thermal management 2 (tm2) ? microsoft windows nt* hardware design guide v1.0 compliant signal description r datasheet 33 2 signal description this chapter provides a detailed description of (g)mch signals. the signals are arranged in functional groups according to their associated interface. the states of all of the signals during reset are provided in section 2.11. the following notations are used to describe the signal type: gtl+ open drain gtl+ interface signal. re fer to the gtl+ i/o specification for complete details. the (g)mch integrates gtl+ termination resistors, and supports vtt of from 0.83 v to 1.65 v (including guardbanding). pcie pci-express interface signals. these signals are compatible with pci express 1.0 signaling environment ac specifications and are ac coupled. the buffers are not 3.3 v tolerant. differential voltage specification = (|d+ - d-|) * 2 = 1.2 v maximum. single-ended maximum = 1.5 v. single-ended minimum = 0 v. dmi direct media interface signals. these signa ls are compatible with pci express 1.0 signaling environment ac specifications, but are dc coupled. the buffers are not 3.3 v tolerant. differential voltage specification = (|d+ - d-|) * 2 = 1.2 v maximum. single-ended maximum = 1.5 v. single-ended minimum = 0 v. cmos cmos buffers. 1.5 v tolerant. cod cmos open drain buffers. 2.5 v tolerant. hvcmos high voltage cmos buffers. 2.5 v tolerant. hvin high voltage cmos input-only buffers. 3.3 v tolerant. sstl-2 stub series termination logic. these are 2.6 v output capable buffers. 2.6 v tolerant. sstl-1.8 stub series termination logic. these are 1.8 v output capable buffers. 1.8 v tolerant. a analog reference or output. may be used as a threshold voltage or for buffer compensation. signal description r 34 datasheet figure 2-1. intel ? (g)mch signal interface diagram signal_info scs_a[3:0]# sma_a[13:0] sbs_a[2:0] sras_a# scas_a# swe_a# sdq_a[63:0] sdm_a[7:0] sdqs_a[7:0], sdqs_a[7:0]# scke_a[3:0] sclk_a[5:0], sclk_a[5:0]# sodt_a[3:0] processor system bus interface ha[31:3]# hd[63:0] hads# hbnr# hbpri# hdbsy# hdefer# hdrdy# hedrdy# hhit# hhitm# hlock# hreq[4:0]# hpcreq# htrdy# hrs[2:0]# hcpurst# hbreq0# hdinv[3:0]# hadstb[1:0]# hdstbp[3:0]#, hdstbn[3:0]# bsel[2:0] hrcomp hscomp hswing hvref system memory 2 ddr/ ddr2 channel a vcc vtt vcc_exp vccsm vcc2 vcca_exppll vcca_dplla vcca_dpllb vcca_hpll vcca_smpll vss vcca_dac vssa_dac voltage reference, and power intel ? sdvo device interface 1 sdvob_green-, sdvob_green+ sdvob_blue-, sdvob_blue+ sdvoc_red- / sdvob_alpha-, sdvoc_red+ / sdvob_alpha+ sdvoc_green-, sdvoc_green+ sdvoc_blue-, sdvoc_blue+ sdvoc_clk-, sdvoc_clk+ sdvo_tvclkin-, sdvo_tvclkin, sdvob_int-, sdvob_int+ sdvoc_int-, sdvoc_int+ sdvo_stall-, sdvo_stall+ sdvo_ctrlclk sdvo_ctrldata srcomp[1:0] socomp[1:0] sm_slewin[1:0] sm_slewout[1:0] smvref[1:0] system memory 2 ddr/ddr2 ref./ comp. analog display hsync vsync red, red# green, green# blue, blue# refset ddc_clk ddc_data pci express x16 graphics port exp_rxn[15:0], exp_rxp[15:0] exp_txn[15:0], exp_txp[15:0] exp_compo exp_compi exp_slr scs_b[3:0]# sma_b[13:0] sbs_b[2:0] sras_b# scas_b# swe_b# sdq_b[63:0] sdm_b[7:0] sdqs_b[7:0], sdqs_b[7:0]# scke_b[3:0] sclk_b[5:0], sclk_b[5:0]# sodt_b[3:0] system memory 2 ddr/ ddr2 channel b hclkp, hclkn gclkp, gclkn drefclkn, drefclkp rstin# pwrok extts# bsel[2:0] mtype ich_sync# clocks, reset, and misc. direct media interface dmi_rxp[3:0], dmi_rxn[3:0] dmi_txp[3:0], dmi_txn[3:0] intel ? 82915g/ 82915gv/ 82910gl only intel ? 82915g/ 82915gv/ 82910gl only note: 1. sdvo signals on the 82915g gmch are multiplexed with the pci express x16 graphics port signals. 2. the 82910gl gmch only supports ddr (not ddr2). intel ? 82915g/ 82915p only intel ? 82915g/ 82915gv/ 82910gl only signal description r datasheet 35 2.1 host interface signals note: unless otherwise noted, the voltage level for all signa ls in this interface is tied to the termination voltage of the host bus (vtt). signal name type description hads# i/o gtl+ address strobe: the processor bus owner asserts hads# to indicate the first of two cycles of a request phase. the (g)mch can assert this signal for snoop cycles and interrupt messages. hbnr# i/o gtl+ block next request: this signal is used to bl ock the current request bus owner from issuing new requests. this signal is used to dynamically control the processor bus pipeline depth. hbpri# o gtl+ priority agent bus request: the (g)mch is the only priority agent on the processor bus. it asserts this signal to obtain the ownership of the address bus. this signal has priority over sy mmetric bus requests and will cause the current symmetric owner to stop i ssuing new transactions unless the hlock# signal was asserted. hbreq0# i/o gtl+ bus request 0: the (g)mch pulls the proc essor?s bus hbreq0# signal low during hcpurst#. the processor sa mples this signal on the active-to- inactive transition of hcpurst#. the mi nimum setup time for this signal is 4 hclks. the minimum hold time is 2 clocks and the maximum hold time is 20 hclks. hbreq0# should be tristated after the hold time requirement has been satisfied. hcpurst# o gtl+ cpu reset: the hcpurst# pin is an output from the (g)mch. the (g)mch asserts hcpurst# while rstin# is asserted and for approximately 1 ms after rstin# is de-asserted. the hcpurst# allows the processors to begin execution in a known state. note that the intel ? ich6 must provide processor frequency select strap set- up and hold times around hcpurst#. this requires strict synchronization between (g)mch hcpurst# de-assertion and the intel? ich6 driving the straps. hdbsy# i/o gtl+ data bus busy: this signal is used by the dat a bus owner to hold the data bus for transfers requiring more than one cycle. hdefer# o gtl+ defer: signals that the (g)mch will terminate the transaction currently being snooped with either a deferred re sponse or with a retry response. hdinv[3:0]# i/o gtl+ dynamic bus inversion: driven along with the hd[63:0] signals . indicates if the associated signals are inverted or not. hdinv[3:0]# are asserted such that the number of data bits driven elec trically low (low voltage) within the corresponding 16 bit group never exceeds 8. hdinvx# data bits hdinv3# hd[63:48] hdinv2# hd[47:32] hdinv1# hd[31:16] hdinv0# hd[15:0] signal description r 36 datasheet signal name type description hdrdy# i/o gtl+ data ready : this signal is asserted for eac h cycle that data is transferred. hedrdy# o gtl+ early data ready : this signal indicates that the data phase of a read transaction will start on the bus exac tly one common clock after assertion. ha[31:3]# i/o gtl+ host address bus: ha[31:3]# connect to the processor address bus. during processor cycles, the ha[31: 3]# are inputs. the (g)mch drives ha[31:3]# during snoop cycles on behalf of dmi and pci express graphics initiators. ha[31:3]# are transferred at 2x rate. hadstb[1:0]# i/o gtl+ host address strobe: the source synchronous strobes used to transfer ha[31:3]# and hreq[4:0] at the 2x transfer rate. hd[63:0] i/o gtl+ host data: these signals are connected to t he processor data bus. data on hd[63:0] is transferred at 4x rate. note that the data signals may be inverted on the processor bus, depending on the hdinv[3:0]# signals. hdstbp[3:0]# hdstbn[3:0]# i/o gtl+ differential host data strobes: the differential source synchronous strobes are used to transfer hd[63:0] and hdinv[3:0]# at 4x transfer rate. these signals are named this way becaus e they are not level sensitive. data is captured on the falling edge of both strobes. hence, they are pseudo-differential, and not true differential. strobes data bits hdstbp3#, hdstbn3# hd[63:48] hdinv3# hdstbp2#, hdstbn2# hd[47:32] hdinv2# hdstbp1#, hdstbn1# hd[31:16] hdinv1# hdstbp0#, hdstbn0# hd[15:0] hdinv0# hhit# i/o gtl+ hit: this signal indicates that a cach ing agent holds an unmodified version of the requested line. also, driven in conjunction with hhitm# by the target to extend the snoop window. hhitm# i/o gtl+ hit modified: this signal indicates that a caching agent holds a modified version of the requested line and that this agent assumes responsibility for providing the line. this signal is also driven in conjunction with hhit# to extend the snoop window. hlock# i/o gtl+ host lock: all processor bus cycles sampled with the assertion of hlock# and hads#, until the negation of hlock# must be atomic (i.e., no dmi or pci express graphics accesses to dra m are allowed when hlock# is asserted by the processor). hpcreq# i gtl+ 2x precharge request: the processor provides a ?hint? to the (g)mch that it is ok to close the dram page of the memory read request with which the hint is associated. the (g)mch uses this information to schedule the read request to memory using the special ?aut oprecharge? attribute. this causes the dram to immediately close (pre charge) the page after the read data has been returned. this allows subs equent processor requests to more quickly access information on other dram pages, since it will no longer be necessary to close an open page prior to opening the proper page. asserted by the requesting agent during both halves of request phase. the same information is provided in both halves of the request phase. signal description r datasheet 37 signal name type description hreq[4:0]# i/o gtl+ 2x host request command: these signals define the attributes of the request. hreq[4:0]# are transferred at 2x rate. they are asserted by the requesting agent during both halves of r equest phase. in the first half the signals define the transaction type to a le vel of detail that is sufficient to begin a snoop request. in the second half the signals carry additional information to define the complete transaction type. the transactions supported by the (g )mch host bridge are defined in the host interface section of this document. htrdy# o gtl+ host target ready: this signal indicates that the target of the processor transaction is able to ent er the data transfer phase. hrs[2:0]# o gtl+ response signals: these signals indicate the type of response as shown below: 000 = response type 001 = idle state 010 = retry response 011 = deferred response 100 = reserved (not driven by (g)mch) 101 = hard failure (not driven by (g)mch) 110 = no data response 111 = implicit writeback 111 = normal data response bsel[2:0] i cmos bus speed select: at the de-assertion of rstin#, the value sampled on these pins determines the ex pected frequency of the bus. hrcomp i/o cmos host rcomp: used to calibrate the host gtl+ i/o buffers. this signal is powered by the host interface termination rail (vtt). hscomp i/o cmos slew rate compensation: compensation for the host interface. hswing i a host voltage swing: this signal provides t he reference voltage used by fsb rcomp circuits. hswing is used for the signals handled by hrcomp. hvref i a host reference voltage reference: voltage input for the data, address, and common clock signals of the host gtl interface. signal description r 38 datasheet 2.2 ddr/ddr2 dram channel a interface note that the 82910gl, 82915GL, and 82915pl (g)mch only supports ddr dram. signal name type description sclk_a[5:0] o sstl- 2/1.8 sdram differential clock: (3 per dimm). sclk_ax and its complement sclk_ax# signal make a differential clock pair output. the crossing of the positive edge of sclk_ax and the negative edge of its complement sclk_ax# are used to sample the command and control signals on the sdram. sclk_a[5:0]# o sstl- 2/1.8 sdram complementary differential clock: (3 per dimm) these are the complementary differential ddr/ddr2 clock signals. scs_a[3:0]# o sstl- 2/1.8 chip select: (1 per rank) these signals select particular sdram components during the active state. there is one chip select for each sdram rank. sma_a[13:0] o sstl- 2/1.8 memory address: these signals are used to provide the multiplexed row and column address to the sdram sbs_a[2:0] o sstl- 2/1.8 bank select: these signals define which banks are selected within each sdram rank ddr2: 1-gb technology is 8 banks. ddr: 1-gb technology is 4 banks. sbs_a[2] is not used. sras_a# o sstl- 2/1.8 row address strobe: this signal is used with scas_a# and swe_a# (along with scs_a#) to define the sdram commands. scas_a# o sstl- 2/1.8 column address strobe: this signal is used with sras_a# and swe_a# (along with scs_a#) to define the sdram commands. swe_a# o sstl- 2/1.8 write enable: this signal is used with scas_a# and sras_a# (along with scs_a#) to define the sdram commands. sdq_a[63:0] i/o sstl- 2/1.8 2x data lines: sdq_a signals interface to the sdram data bus. sdm_a[7:0] o sstl- 2/1.8 2x data mask: when activated during wr ites, the corresponding data groups in the sdram are masked. there is one sdm_ax signal for every data byte lane. sdqs_a[7:0] i/o sstl- 2/1.8 2x data strobes: for ddr, the rising and falling edges of sdqs_ax are used for capturing data during r ead and write transactions. for ddr2, sdqs_ax and its complement sdqs_ax# signal make up a differential strobe pair. the data is captured at the crossing point of sdqs_ax and its complement sdqs_ax# during read and write transactions. sdqs_a[7:0]# i/o sstl-1.8 2x data strobe complements (ddr2 only): these signals are the complementary ddr2 strobe signals. signal description r datasheet 39 signal name type description scke_a[3:0] o sstl- 2/1.8 clock enable: (1 per rank) sacke is used to initialize the sdrams during power-up, to power-down sdram ranks, and to place all sdram ranks into and out of self-refresh during suspend-to-ram. sodt_a[3:0] o sstl-1.8 on die termination (ddr2 only): active on-die termination control signals for ddr2 devices. 2.3 ddr/ddr2 dram channel b interface note that the 82910gl, 82915GL, and 82915pl (g)mch only supports ddr dram. signal name type description sclk_b[5:0] o sstl- 2/1.8 sdram differential clock: (3 per dimm) sclk_bx and its complement sclk_bx# signal make a differential clock pair output. the crossing of the positive edge of sclk_bx and the negative edge of its complement sclk_bx# are used to sample the command and control signals on the sdram. sclk_b[5:0]# o sstl- 2/1.8 sdram complementary differential clock: (3 per dimm) these are the complementary differential ddr/ddr2 clock signals. scs_b[3:0]# o sstl- 2/1.8 chip select: (1 per rank) these signals select particular sdram components during the active state. there is one chip select for each sdram rank sma_b[13:0] o sstl- 2/1.8 memory address: these signals are used to provide the multiplexed row and column address to the sdram sbs_b[2:0] o sstl- 2/1.8 bank select: these signals define which banks are selected within each sdram rank ddr2: 1-gb technology is 8 banks. ddr: 1-gb technology is 4 banks. sbs_b[2] is not used sras_b# o sstl- 2/1.8 row address strobe: this signal is used with scas_b# and swe_b# (along with scs_b#) to define the sdram commands scas_b# o sstl- 2/1.8 column address strobe: this signal is used with sras_b# and swe_b# (along with scs_b#) to define the sdram commands. swe_b# o sstl- 2/1.8 write enable: this signal is used with scas_b# and sras_b# (along with scs_b#) to define the sdram commands. sdq_b[63:0] i/o sstl- 2/1.8 2x data lines: sdq_bx signals interface to the sdram data bus sdm_b[7:0] o sstl- 2/1.8 2x data mask: when activated during wr ites, the corresponding data groups in the sdram are masked. there is one sdm_bx signal for every data byte lane. signal description r 40 datasheet signal name type description sdqs_b[7:0] i/o sstl- 2/1.8 2x data strobes: for ddr the rising and falling edges of sdqs_bx are used for capturing data during r ead and write transactions. for ddr2, sdqs_bx and its complement sdqs_bx# make up a differential strobe pair. the data is captured at the crossing point of sdqs_bx and its complement sdqs_bx# during read and write transactions. sdqs_b[7:0]# i/o sstl-1.8 2x data strobe complements (ddr2 only): these signals are the complementary ddr2 strobe signals. scke_b[3:0] o sstl- 2/1.8 clock enable: (1 per rank) scke_b is used to initialize the sdrams during power-up, to power-down sdram ranks, and to place all sdram ranks into and out of self-refresh during suspend-to-ram. sodt_b[3:0] o sstl-1.8 on die termination (ddr2 only): active on-die termination control signals for ddr2 devices. 2.4 ddr/ddr2 dram reference and compensation note that the 82910gl, 82915GL, and 82915pl (g)mch only supports ddr dram. signal name type description srcomp[1:0] i/o system memory rcomp socomp[1:0] i/o a ddr2 on-die dram over current detection (ocd) driver compensation (ddr2 only) sm_slewin[1:0] i a buffer slew rate input: slew rate characterization buffer input for x and y orientation. sm_slewout[1:0] o a buffer slew rate output: slew rate characterization buffer output for x and y orientation smvref[1:0] i a sdram reference voltage: reference voltage inputs for each dq, dm, dqs, and dqs# input signals. signal description r datasheet 41 2.5 pci express* x16 graphics port signals (intel ? 82915g, 82915p, 82915pl only) unless otherwise specified, pci express graphics signals are ac coupled, so the only voltage specified is a maximum 1.2 v differential swing. signal name type description exp_rxn[15:0] exp_rxp[15:0] i/o pcie pci express graphics receive differential pair exp_txn[15:0] exp_txp[15:0] o pcie pci express graphics transmit differential pair exp_compo i a pci express graphics output current compensation note: exp_comp0 is used for dmi current compensation. exp_compi i a pci express graphics input current compensation note: exp_compi is used for dmi current compensation. exp_slr i cmos pci express* static lane reversal: the (g)mch?s pci express lane numbers are reversed. for example, the (g)mch pci express interface signals can be configured as follows: normal lane ball operation reversed c10 exp_txp0 exp_txp15 a9 exp_txp1 exp_txp14 ? ? ? n3 exp_txp14? exp_txp1? p1 exp_txp15 exp_txp0 0 = (g)mch?s pci express lane numbers are reversed 1 = normal operation signal description r 42 datasheet 2.6 analog display signals (intel ? 82915g/82915gv/82915GL/82910gl gmch only) signal name type description red o a red analog video output: this signal is a crt analog video output from the internal color palette dac. the dac is designed for a 37.5 ? routing impedance; however, the terminating resistor to ground will be 75 ? (e.g., 75 ? resistor on the board, in parallel with a 75 ? crt load). red# o a redb analog output: this signal is an analog video output from the internal color palette dac. it should be shorted to the ground plane. green o a green analog video output: this signal is a crt analog video output from the internal color palette dac. the dac is designed for a 37.5 ? routing impedance; however, the terminating resistor to ground will be 75 ? (e.g., 75 ? resistor on the board, in parallel with a 75 ? crt load). green# o a greenb analog output: this signal is an analog video output from the internal color palette dac. it should be shorted to the ground plane. blue o a blue analog video output: this signal is a crt analog video output from the internal color palette dac. the dac is designed for a 37.5 ? routing impedance; however, the terminating resistor to ground will be 75 ? (e.g., 75 ? resistor on the board, in parallel with a 75 ? crt load). blue# o a blueb analog output: this signal is an analog video output from the internal color palette dac. it should be shorted to the ground plane. refset o a resistor set: set point resistor for the internal color palette dac. a 255 ? 1% resistor is required between refset and motherboard ground. hsync o 2.5 v cmos crt horizontal synchronization: this signal is used as the horizontal sync (polarity is programmable) or ?sync interval?. 2.5 v output vsync o 2.5 v cmos crt vertical synchronization: this signal is used as the vertical sync (polarity is programmable). 2.5 v output. ddc_clk i/o 2.5 v cmos monitor control clock. this signal may be used as the ddc_clk for a secondary multiplexed digital display connector. ddc_data i/o 2.5 v cmos monitor control data. this signal may be used as the ddc_data for a secondary multiplexed digital display connector. signal description r datasheet 43 2.7 clocks, reset, and miscellaneous signal name type description hclkp hclkn i cmos differential host clock in: these pins receive a differential host clock from the external clock synthesizer. this clock is used by all of the (g)mch logic that is in the host clock domain. gclkp gclkn i cmos differential pci express graphics clock in: these pins receive a differential 100 mhz serial referenc e clock from the external clock synthesizer. this clock is used to generate the clocks necessary for the support of pci express. drefclkn drefclkp i cmos display pll differential clock in rstin# i hvin reset in: when asserted, this signal will asynchronously reset the (g)mch logic. this signal is connec ted to the pltrst# output of the intel ? ich6. all pci express graphics attach output signals will also tri- state compatible with pci express* specification rev 1.0a. this input should have a schmitt tr igger to avoid spurious resets. this signal is required to be 3.3 v tolerant. pwrok i hvin power ok: when asserted, pwrok is an indication to the (g)mch that core power has been stable for at least 10 us. extts# i hvcmos external thermal sensor input: this signal may c onnect to a precision thermal sensor located on or near the dimms. if the system temperature reaches a dangerously high value, then this signal can be used to trigger the start of system thermal management. this signal is activated when an increase in temperature causes a voltage to cross some threshold in the sensor. mtype i cmos memory type select strap. this signal is a strapping option that indicates the type of system memory. for the 82910gl gmch, this signal must be tied to ground. 0 = ddr2 1 = ddr ich_sync# o hvcmos ich sync: this signal is connected to the mch_synch# signal on the ich6. 2.8 direct media interface (dmi) signal name type description dmi_rxp[3:0] dmi_rxn[3:0] i/o dmi direct media interface: these signals are the receive differential pair (rx). dmi_txp[3:0] dmi_txn[3:0] o dmi direct media interface: these signals are the transmit differential pair (tx). signal description r 44 datasheet 2.9 intel ? serial dvo (sdvo) interface (82915g/82915gv/82915GL/82910gl gmch only) for the 82915g/82915gv/82915GL/82910gl gmch, all but two of the pins in this section are multiplexed with the lower 8 lane s of the pci express interface. note: the sdvo interface does not support static lane reversal (e.g., sdvob_clk# will originate from the same ball whether the pci express interface is lane-reversed mode or not. signal name type description sdvob_green- o pcie serial digital video channel b green complement . this signal is multiplexed with exp_txn1. sdvob_green+ o pcie serial digital video channel b green . this signal is multiplexed with exp_txp1. sdvob_blue- o pcie serial digital video channel b blue complement . this signal is multiplexed with exp_txn2. sdvob_blue+ o pcie serial digital video channel b blue . this signal is multiplexed with exp_txp2. sdvoc_red- / sdvob_alpha- o pcie serial digital video channel c red complement channel b alpha complement . this signal is multiplexed with exp_txn4. sdvoc_red+ / sdvob_alpha+ o pcie serial digital video channel c red channel b alpha . this signal is multiplexed with exp_txp4. sdvoc_green- o pcie serial digital video channel c green complement . this signal is multiplexed with exp_txn5. sdvoc_green+ o pcie serial digital video channel c green . this signal is multiplexed with exp_txp5. sdvoc_blue- o pcie serial digital video channel c blue complement . this signal is multiplexed with exp_txn6. sdvoc_blue+ o pcie serial digital video channel c blue . this signal is multiplexed with exp_txp6. sdvoc_clk- o pcie serial digital video channel c clock complement . this signal is multiplexed with exp_txn7. sdvoc_clk+ o pcie serial digital video channel c clock . this signal is multiplexed with exp_txp7. sdvo_tvclkin- i pcie serial digital video tvout synchronization clock complement . this signal is multiplexed with exp_rxn0. sdvo_tvclkin+ i pcie serial digital video tvout synchronization clock . this signal is multiplexed with exp_rxp0. sdvob_int- i pcie serial digital video input interrupt complement. this signal is multiplexed with exp_rxn1. sdvob_int+ i pcie serial digital video input interrupt. this signal is multiplexed with exp_rxp1. sdvoc_int+ i pcie serial digital video input interrupt. this signal is multiplexed with exp_rxp5. sdvoc_int- i pcie serial digital video input interrupt complement. this signal is multiplexed with exp_rxn5. signal description r datasheet 45 signal name type description sdvo_stall- i pcie serial digital video field stall complement. this signal is multiplexed with exp_rxn2. sdvo_stall+ i pcie serial digital video field stall.. this signal is multiplexed with exp_rxp2. sdvo_ctrlclk i/o cod serial digital video device control clock. sdvo_ctrldata i/o cod serial digital video device control data. this signal also provides a str apping option. device 1 (host-pci express bridge) is disabled on reset when the sdvo presence strap (sdvo_ctlrdata) is sa mpled high, and is enabled when this signal is sampled low. 2.10 power and ground name voltage description vcc 1.5 v core power. vtt 1.2 v processor system bus power. vcc_exp 1.5 v pci express* and dmi power. vccsm 1.8 v / 2.6 v system memory power. ddr2: vccsm = 1.8 v ddr: vccsm = 2.6 v vcc2 2.5 v 2.5 v cmos power. vcca_exppll 1.5 v pci express pll analog power. vcca_dplla 1.5 v display pll a analog power. vcca_dpllb 1.5 v display pll b analog power. vcca_hpll 1.5 v host pll analog power. vcca_smpll 1.5 v system memory pll analog power. vcca_dac 2.5 v display dac analog power. this signal is on the 82915g/82915gv/82915GL/82910gl gmch only. vss 0 v ground. vssa_dac 0 v ground. this signal is on the 82915g/82915gv/82915GL/82910gl gmch only. signal description r 46 datasheet 2.11 reset states and pull-up/pull-downs this section describes the expected states of the (g)mch i/o buffers during and immediately after the assertion of rstin#. this table only re fers to the contributions on the interface from the (g)mch and does not reflect any external influence (such as external pull-up/pull-down resistors or external drivers). legend: cmct: common mode center tapped. differential signals are weakly driven to the common mode central voltage. drive: strong drive (to normal value supplied by core logic if not otherwise stated) term: normal termination devices are turned on lv: low voltage hv: high voltage in: input buffer enabled iso: isolate input buffer so that it doesn?t oscillate if input left floating tri: tri-state pu: weak internal pull-up pd: weak internal pull-down strap: strap input sampled during asserti on or on the de-asserting edge of rstin# table 2-1. host interface reset and s3 states interface signal name i/o state during rstin# assertion state after rstin# de- assertion s3 pull-up/ pull-down host i/f hcpurst# o drive lv term hv after approximately 1ms tri (no vtt) hadstb[1:0]# i/o term hv term hv tri (no vtt) ha[31:3]# i/o term hv term hv tri (no vtt) hd[63:0] i/o term hv term hv tri (no vtt) hdstbp[3:0]# i/o term hv term hv tri (no vtt) hdstbn[3:0]# i/o term hv term hv tri (no vtt) hdinv[3:0]# i/o term hv term hv tri (no vtt) hads# i/o term hv term hv tri (no vtt) hbnr# i/o term hv term hv tri (no vtt) hbpri# o term hv term hv tri (no vtt) hdbsy# i/o term hv term hv tri (no vtt) hdefer# o term hv term hv tri (no vtt) hdrdy# i/o term hv term hv tri (no vtt) hedrdy# o term hv term hv tri (no vtt) signal description r datasheet 47 interface signal name i/o state during rstin# assertion state after rstin# de- assertion s3 pull-up/ pull-down host i/f hhit# i/o term hv term hv tri (no vtt) hhitm# i/o term hv term hv tri (no vtt) hlock# i/o term hv term hv tri (no vtt) hreq[4:0]# i/o term hv term hv tri (no vtt) htrdy# o term hv term hv tri (no vtt) hrs[2:0]# o term hv term hv tri (no vtt) hbreq0# i/o term hv term hv tri (no vtt) hpcreq# i term hv term hv tri (no vtt) hvref i in in tri hrcomp i/o tri tri after rcomp tri 20 ? resistor for board with target impedance of 60 ? hswing i in in hscomp i/o tri tri tri table 2-2. system memory (ddr2) reset and s3 states interface signal name i/o state during rstin# assertion state after rstin# de- assertion s3 pull-up/ pull-down channel a sclk_a[5:0] o tri tri tri sclk_a[5:0]# o tri tri tri scs_a[3:0]# o tri tri tri sma_a[13:0] o tri tri tri sbs_a[2:0] o tri tri tri sras_a# o tri tri tri scas_a# o tri tri tri swe_a# o tri tri tri sdq_a[63:0] i/o tri tri tri sdm_a[7:0] o tri tri tri sdqs_a[7:0] i/o tri tri tri sdqs_a[7:0]# i/o tri tri tri scke_a[3:0] o lv lv lv system memory (ddr2) sodt_a[3:0] o lv lv lv signal description r 48 datasheet interface signal name i/o state during rstin# assertion state after rstin# de- assertion s3 pull-up/ pull-down channel b sclk_b[5:0] o tri tri tri sclk_b[5:0]# o tri tri tri scs_b[3:0]# o tri tri tri sma_b[13] o tri tri tri sma_b[12:11] o lv lv lv sma_b[10:8] o tri tri tri sma_b[7] o lv lv lv sma_b[6:0] o tri tri tri sbs_b[2] o lv lv lv sbs_b[1:0] o tri tri tri sras_b# o tri tri tri scas_b# o tri tri tri swe_b# o tri tri tri sdq_b[63:0] i/o tri tri tri sdm_b[7:0] o tri tri tri sdqs_b[7:0] i/o tri tri tri sdqs_b[7:0]# i/o tri tri tri scke_b[3:0] o lv lv lv sodt_b[3:0] o lv lv lv srcomp0 i/o tri tri (after rcomp) tri srcomp1 i/o tri tri (after rcomp) tri sm_slewin[1:0] i in in in sm_slewou{1:0] o tri tri (after rcomp) tri smvref[1:0] i in in in system memory (ddr2) socomp[1:0] i/o tri tri tri ddr2: 40 ? resistor to ground signal description r datasheet 49 table 2-3. system memory (ddr) reset and s3 states interface signal name i/o state during rstin# assertion state after rstin# de-assertion s3 pull-up/ pull-down channel a sclk_a[5:0] o tri tri tri sclk_a[5:0]# o tri tri tri sma_a[13:9] o tri tri tri sma_a[8] o lv lv lv sma_a[7:6] o tri tri tri sma_a[5] o lv lv lv sma_a[4:0] o tri tri tri sbs_a[2:0] o tri tri tri scs_a[3]# o tri tri tri scs_a[2:1]# o lv lv lv scs_a[0]# o tri tri tri sras_a# o tri tri tri scas_a# o lv lv lv swe_a# o tri tri tri sdq_a[63:0] i/o tri tri tri sdm_a[7:0] o tri tri tri sdqs_a[7:0] i/o tri tri tri sdqs_a[7:0]# i/o tri tri tri system memory (ddr) scke_a[3:0] o lv lv lv channel b sclk_b[5:0] o tri tri tri sclk_b[5:0]# o tri tri tri system memory (ddr) sma_b[13:0] o tri tri tri sma_b[0] o lv lv lv sbs_b[2] o tri tri tri sbs_b[1] o lv lv lv sbs_b[0] o tri tri tri scs_b[3]# o lv lv lv scs_b[2:0]# o tri tri tri sras_b# o tri tri tri scas_b# o tri tri tri signal description r 50 datasheet interface signal name i/o state during rstin# assertion state after rstin# de-assertion s3 pull-up/ pull-down swe_b# o tri tri tri sdq_b[63:0] i/o tri tri tri system memory (ddr) sdm_b[7:0] o tri tri tri sdqs_b[7:0] i/o tri tri tri sdqs_b[7:0]# i/o tri tri tri scke_b[3:0] o lv lv lv srcomp0 i/o tri tri (after rcomp) tri srcomp1 i/o tri tri (after rcomp) tri sm_slewin[1:0] i in in in sm_slewou[1:0] o tri tri (after rcomp) tri smvref[1:0] i in in in socomp[1:0] i/o tri tri tri ddr2: 40 ? resistor to ground table 2-4. pci express* graphics x16 port reset and s3 states interface signal name i/o state during rstin# assertion state after rstin# de-assertion s3 pull-up/ pull-down exp_rxn[15:0] i/o cmct cmct cmct exp_rxp[15:0] i/o cmct cmct cmct exp_txn[15:0] o cmct 1.0 v cmct 1.0 v cmct 1.0 v exp_txp[15:0] o cmct 1.0 v cmct 1.0 v cmct 1.0 v exp_compo i tri tri (after rcomp) tri pci express*- graphics exp_compi i tri tri (after rcomp) tri table 2-5. dmi reset and s3 states interface signal name i/o state during rstin# assertion state after rstin# de-assertion s3 pull-up/ pull- down dmi_rxn[3:0] i/o cmct cmct cmct dmi_rxp[3:0] i/o cmct cmct cmct dmi_txn[3:0] o cmct 1.0 v cmct 1.0 v cmct 1.0 v dmi dmi_txp[3:0] o cmct 1.0 v cmct 1.0 v cmct 1.0 v signal description r datasheet 51 table 2-6. clocking reset and s3 states interface signal name i/o state during rstin# assertion state after rstin# de- assertion s3 pull-up/ pull-down hclkn i in in in hclkp i in in in gclkn i in in in gclkp i in in in drefclkn i in in in clocks drefclkp i in in in table 2-7. misc reset and s3 states interface signal name i/o state during rstin# assertion state after rstin# de-assertion s3 pull-up/ pull-down rstin# i in in in pwrok i hv hv hv extts# i pu pu pu bsel[2:0] i tri tri tri mtype i term hv term hv term hv exp_slr i term hv term hv term hv ich_sync# o pu pu pu sdvo_ctrlclk o tri tri tri misc. sdvo_ctrldata i/o term pd tri term pd table 2-8. dac reset and s3 states (intel ? 82915g/82915gv/82915GL/82910gl gmch only) interface signal name i/o state during rstin# assertion state after rstin# deassertion s3 pull-up/ pull-down hsync o lv lv vsync o lv lv red o tri tri tri red# o tri tri tri green o tri tri tri green# o tri tri tri blue o tri tri tri blue# o tri tri tri refset o tri 0.5* vcca_dac tri 255 ? 1% resistor to ground ddc_clk i/o in in in dac ddc_data i/o in in in signal description r 52 datasheet register description r datasheet 53 3 register description the (g)mch contains two sets of software acce ssible registers, accessed via the processor i/o address space: control registers and internal configur ation registers. ? control registers are i/o mapped into the pro cessor i/o space that control access to pci and pci express configurati on space (see section 3.4). ? internal configuration registers residing within the (g)mch are partitioned into three logical device register sets (?logical? since they reside within a si ngle physical device). the first register set is dedicated to host bridge func tionality (i.e. dram configuration, other chipset operating parameters and optional features). th e second register block is dedicated to the 82915g/82915p/82915pl (g)mch host-pci express bridge functions (controls pci express interface configurations and operating parameters). the th ird register block is for the 82915g/82915gv/82915GL/82910gl gmch internal graphics functions. the (g)mch internal registers (i/o mapped, configuration and pci express extended configuration registers) are accessible by the processor. the regi sters that reside within the lower 256 bytes of each device can be accessed as byte, word (16-bit), or dword (32-bit) quantities, with the exception of config_address that can only be accessed as a dword. all multi-byte numeric fields use "little-endian" ordering (i.e., lower addresses contain the least significant parts of the field). registers that reside in bytes 256 through 4095 of each device may only be accessed using memory mapped transactions in dword (32-bit) quantities. 3.1 register terminology the following table shows the registe r-related terminology that is used. item description ro read only bit(s). writes to these bits have no effect. rs/wc read set / write clear bit(s). these bits are set to ?1? when read and then will continue to remain set until written. a write of ?1? cl ears (sets to ?0?) the corresponding bit(s) and a write of ?0? has no effect. r/w read / write bit(s). these bits can be read and written. r/wc read / write clear bit(s). these bits c an be read. internal events may set this bit. a write of ?1? clears (sets to ?0?) the corres ponding bit(s) and a write of ?0? has no effect. r/wc/s read / write clear / sticky bit(s). these bits can be read. internal events may set this bit. a write of ?1? clears (sets to ?0?) t he corresponding bit(s) and a write of ?0? has no effect. bits are not cleared by "warm" reset, but will be reset with a cold/complete reset (for pci express* related bits a cold rese t is ?power good reset? as defined in the pci express* specification ). r/w/l read / write / lockable bit(s). these bits can be read and written. additionally there is a bit (which may or may not be a bit marked r/w/ l) that, when set, prohibits this bit field from being writeable (bit field becomes read only). r/w/s read / write / sticky bit(s). these bits can be read and written. bits are not cleared by "warm" reset, but will be reset with a cold/complete reset (for pci express related bits a cold reset is ?power good reset? as defined in the pci express* specification ). register description r 54 datasheet item description r/wsc read / write self clear bit(s). these bits can be read and written. when the bit is ?1?, hardware may clear the bit to ?0? based upon internal events, possibly sooner than any subsequent read could retrieve a ?1?. r/wsc/l read / write self clear / lockable bit( s). these bits can be read and written. when the bit is ?1?, hardware may clear the bit to ?0? based upon internal events, possibly sooner than any subsequent read could retrieve a ?1?. additionally there is a bit (which may or may not be a bit marked r/w/l) that, when set, prohibits this bit field from being writeable (bit field becomes read only). r/wc read write clear bit(s). these bits can be read and written. however, a write of ?1? clears (sets to ?0?) the corresponding bit(s) and a write of ?0? has no effect. r/wo write once bit(s). once written, bits wi th this attribute become read only. these bits can only be cleared by a reset. w write only. whose bits may be written, but will always-return zeros when read. they are used for write side effects. any data writt en to these registers cannot be retrieved. reserved bits some of the (g)mch registers descri bed in this section cont ain reserved bits. these bits are labeled "reserved?. so ftware must deal correctly with fields that are reserved. on reads, software must use appropriate masks to extract the defined bits and not rely on reserved bits being any particular value. on writes, software must ensure that the values of reserved bit positi ons are preserved. that is, the values of reserved bit positions must first be read, merged with t he new values for other bit positions and then written back. note the software does not need to perform read, merge, and write operation for the configuration address register. reserved registers in addition to reserved bits within a regist er, the (g)mch contains address locations in the configuration space of the host bridge ent ity that are marked either "reserved" or ?intel reserved?. the (g)mch responds to accesses to ?reserved? address locations by completing the host cycle. when a ?reserved? register location is read, a zero value is returned. (?reserved? registers can be 8- , 16-, or 32-bits in size). writes to ?reserved? registers have no effect on the (g )mch. registers that are marked as ?intel reserved? must not be modified by system software. writes to ?intel reserved? registers may cause system failure. reads from ?intel reserved? registers may return a non-zero value. default value upon a full reset, the (g)mch sets its ent ire set of internal configuration registers to predetermined default states. some register va lues at reset are determined by external strapping options. the default state represent s the minimum functionality feature set required to successfully bringing up the sy stem. hence, it does not represent the optimal system configuration. it is the res ponsibility of the system initialization software (usually bios) to properly determine the dram configurations, operating parameters and optional system features that are applic able, and to program the (g)mch registers accordingly. register description r datasheet 55 3.2 platform configuration in platforms that support dmi (e.g. this (g)mch) the configuration structure is significantly different from previous hub architectures. th e dmi physically connect s the (g)mch and the intel ich6; so, from a configuration standpoint, the dmi is logically pci bus 0. as a result, all devices internal to the (g)mch and the intel ich6 appear to be on pci bus 0. the ich6 internal lan controller does not appear on bus 0; it appears on the external pci bus (whose number is configurable). the system?s primary pci expansion bus is physi cally attached to the intel ich6 and, from a configuration perspective, appears to be a hier archical pci bus behind a pci-to-pci bridge and therefore has a programmable pci bus number. the pci express graphics attach appears to system software to be a real pci bus behind a pci-to-pci bridge that is a device resident on pci bus 0. note: a physical pci bus 0 does not exist and that dmi and the internal devices in the (g)mch and intel ich6 logically constitute pci bus 0 to configuration software. this is shown in figure 3-1. figure 3-1. conceptual chipset pci configuration diagram device 1 (82915g/82915p/ 82915pl gmch only internal graphics bus 0, (82915g/82915gv/82915g l82910gl device intel ? 82915g/ 82915gv/ 82915GL/ 82915p/82915pl/82919gl (g)mch processor pci configuration in i/o dram interface bus 0, device 0 dmi pci_config_dia register description r 56 datasheet the (g)mch contains the following pci devices within a single physical component. the configuration registers for the devices ar e mapped as devices residing on pci bus 0. ? device 0 ? host bridge/dram controller : logically this appears as a pci device residing on pci bus 0. device 0 contains the standard pc i header registers, pci express base address register, dram control (including thermal/thro ttling control), and configuration for the dmi and other (g)mch sp ecific registers. ? device 1? host-pci express bridge (82915g/82915p/82915pl (g)mch only) . logically this appears as a ?virtual? pci-to-pci bridge residing on pci bus 0 and is compliant with pci express* specification revision 1.0a. device 1 contains the standard pci-to-pci bridge registers and the standard pci express/pci configuration registers (including the pci express memory address mapping). it also contains isochronous and virtual channel controls in the pci express extended configuration space. ? device 2 ? internal graphics control (82915g/82915gv/82915GL/82910gl gmch only) . logically, this appears as a pci device residing on pci bus 0. physically, device 2 contains the configuration registers for 3d, 2d, and display functions. register description r datasheet 57 figure 3-2. register organization (representative of the intel ? 82915g gmch) 000h vc1 (isochronous) port arbitration controls reg_org_82915g (g)mch-ich6 serial interface (dmi) controls: analog controls error reporting controls vc control (incl. vcp) pci express* egress port (rcrb) dmi root complex register block (rcrb) accessed only by pci express enhanced access mechanism. 4kb block allocated for each potential device in root hierarchy. pci express address range device 2 range device 1 range device 0 range thermal sensor psb analog controls (rcomp+) ch 0/1 analog controls ch 0/1 timing controls ch 0/1 throttling ch 0/1 oranization arviter controls device 0 mmio registers: (g)mch control unused device 0 configuration registers device level controls, pam epbar dmi bar pciexbar mchbar 000h 0ffh fffh pci express x16 controls: analog controls error reporting controls vc controls hot plug/slot controls device 1 configuration registers: pci express x16 device level controls 000h 0ffh fffh unused device 2 configuration registers: internal graphics mirror of bits needed by graphics driver graphics thermal controls 000h 0ffh fffh note: diagram not to scale 0000h 3fffh 0000 0000h 0fff ffffh 000h fffh fffh notes: 1. very high level representation. many details omitted. 2. inter graphics memory mapped registers are not shown. 3. only device 1 use pci expr ess extended configuration space. 4. device 0 and device 2 use onl y standard pci configuration space. 5. hex numbers represent address range size and not actual locations. table 3-1. device number assignment for internal (g)mch devices (g)mch function device# host bridge / dram controller device 0 host-to-pci express* bri dge (virtual p2p) (intel ? 82915g/82915p/82915pl (g)mch only) device 1 internal graphics control (82915g/82915gv/82915GL/82910gl gmch only) device 2 register description r 58 datasheet 3.3 general routing configuration accesses the (g)mch supports two pci related interfaces : dmi and pci express. pci and pci express configuration cycles are selectiv ely routed to one of these inte rfaces. the (g)mch is responsible for routing configuration cycles to the proper interface. confi guration cycles to the intel ich6 internal devices and primary pci (including downstream devices) are routed to the intel ich6 via dmi. configuration cycles to both the pci e xpress graphics pci compatibility configuration space and the pci express graphics extended conf iguration space are routed to the pci express graphics port. a detailed description of the mechanism for translating processor i/o bus cycles to configuration cycles is described below. 3.3.1 standard pci bus configuration mechanism the pci bus defines a slot based "configuration space" that allows each device to contain up to 8 functions with each function c ontaining up to 256 8-bit confi guration registers. the pci specification defines two bus cycles to access th e pci configuration space: configuration read and configuration write. memory and i/o spaces are supported di rectly by the processor. configuration space is supporte d by a mapping mechanism implemented within the (g)mch. the configuration access mechanism makes use of the config_address register (at i/o address 0cf8h though 0cfbh) and config_data register (at i/o address 0cfch though 0cffh). to reference a configura tion register a dw i/o write cycl e is used to place a value into config_address that specifies the pci bus, th e device on that bus, the function within the device, and a specific confi guration register of the de vice function being accessed. config_address [31] must be 1 to enable a configuration cycle. config_data then becomes a window into the four bytes of conf iguration space specified by the contents of config_address. any read or write to config_data will result in the (g)mch translating the config_address into th e appropriate configuration cycle. the (g)mch is responsible for translating a nd routing the processor?s i/o accesses to the config_address and config_data registers to internal (g)mch configuration registers, dmi or pci express. 3.3.2 logical pci bus 0 configuration mechanism the (g)mch decodes the bus number (bits 23: 16) and the device number fields of the config_address register. if the bus numb er field of config_address is 0 the configuration cycle is targeting a pci bus 0 device. the host-dmi bridge entity within the (g)mch is hardwired as device 0 on pci bus 0. the host-pci express bridge entity within the (g)mch is hardwired as device 1 on pci bus 0. the 82915g/82915gv/82915GL/82910gl gmch?s device 2 contains the control registers for the integrated graphics controller. the intel ich6 decodes the type 0 access and generates a configuration access to the selected internal device. register description r datasheet 59 3.3.3 primary pci and downstream configuration mechanism if the bus number in the config_address is non-zero, and falls outside the range claimed by the host-pci express bridge (not between upper bound in device?s subordinate bus number register and lower bound in device?s secondary bus number register), the (g)mch would generate a type 1 dmi configuration cycle. this dmi configuration cycle will be sent over the dmi. if the cycle is forwarded to the intel ich6 via the dmi, the intel ich6 compares the non-zero bus number with the secondary bus number and subordinate bus number registers of its pci- to-pci bridges to determine if the configuration cycle is meant for ich6 pci express ports one of the intel ich6?s devices, the dmi, or a downstream pci bus. figure 3-3. dmi type 0 configuration address translation 1 31 30 24 23 16 15 11 10 8 7 2 1 dmi_typ0_config 0 reserved bus number device number function double word xx 1 31 30 24 23 16 15 11 10 87 21 0 reserved bus number device number function double word 00 ocfbh dmi type 0 configuration address extension configuration address ocfah ocf9h ocf8h figure 3-4. dmi type 1 configuration address translation 1 31 30 24 23 16 15 11 10 87 21 dmi_typ1_config 0 reserved bus number device number function double word xx 1 31 30 24 23 16 15 11 10 87 21 0 reserved bus number device number function double word 00 ocfbh dmi type 1 configuration address extension configuration address ocfah ocf9h ocf8h register description r 60 datasheet 3.3.4 pci express* enhanced configuration mechanism pci express extends the configuration space to 4096 bytes per device/func tion as compared to 256 bytes allowed by pci specifica tion, revision 2.3. pci express configuration space is divided into a pci 2.3 compatible region that consists of the first 256b of a logical device?s configuration space and a pci express extended re gion that consists of the re maining configuration space. the pci compatible region can be accessed using e ither the mechanism defi ned in the previous section or using the enhanced pci express c onfiguration access mechanism described in this section. the extended configur ation registers may only be acce ssed using the enhanced pci express configuration access mechanism. to ma intain compatibility w ith pci configuration addressing mechanisms, system software must access the extended configuration space using 32-bit operations (32-bit aligned) only. these 32-bit operations include byte enables allowing only appropriate bytes within the dword to be acce ssed. locked transactions to the pci express memory mapped configuration a ddress space are not supported. all changes made using either access mechanism are equivalent. the enhanced pci express configuration access mechanism uses a flat memory-mapped address space to access device configuration regi sters. this address space is reported by the system firmware to the operating system. th e pciexbar register defines the base address for the 256-mb block of addresses below top of addressable memory (currently 4 gb) for the configur ation space associated with all devices and functions that are potentially a part of the pci express root complex hierarchy. the pci express configuration transaction header includes an additional 4 bits (extended register address[3:0]) between the function number and register address fields to provide indexing into the 4 kb of configuration space allocated to each potential device. for pci compatible configuration requests, the extended register address field must be all zeros. figure 3-5. memory map to pci express* device configuration space memmap_pciexpress bus 255 0xfffffffh bus 1 bus 0 0x1fffffh 0xfffffh 0h device 31 0xfffffh device 1 device 0 0xffffh 0x7fffh function 7 0xfffffh function 1 function 0 0xffffh 0x7fffh 0xfffh pci compatible config space pci compatible config header 0xffh 0x3fh pci express extended configuration space located by pci express base address just the same as with pci devices, each device is selected based on dec oded address information that is provided as a part of the address portion of configuration request packets. a pci express device will decode all address information fields (bus, device, function, and extended address numbers) to provide access to the correct register. register description r datasheet 61 to access this space (steps 1, 2, 3 are performed only once by bios) 1. use the pci compatible configuration mechan ism to enable the pci express enhanced configuration mechanism by writing 1 to bit 31 of the deven register. 2. use the pci compatible configuration mechanism to write an appropriate pci express base address into the pciexbar register. 3. calculate the host address of the register you wish to set using (pci express base + (bus number * 1 mb) + (device number * 32 kb) + (function number * 4 kb) + (1 b * offset within the function) = host address). 4. use a memory write or memory read cycle to th e calculated host address to write to or read from that register. base 31 28 20 19 15 14 11 8 2 70 1 config_write x bus device function extended register number 27 12 x pci express configuration writes internally the host interface unit translates writes to pci expre ss extended configuration space to configurations on the backbone. writes to ex tended space are posted on the fsb, but non-posted on the pci express* x16 graphics interface or dmi pi ns (i.e., translated to configuration writes). see the pci express specification for more information on both the pci 2.3 compatible and pci express enhanced configuration mechanism and transaction rules. register description r 62 datasheet 3.3.5 intel ? 915x gmch configuration cycle flowchart figure 3-6. intel ? 915x gmch configuration cycle flowchart dw i/o write to config_addres s with bit 31 = 1 i/o read/write to config_data gmch generates type 1 access to pci express mch allows cycle to go to dmi resulting in master abort bus# > sec bus bus# sub bus in gmch dev 1 bus# = 0 device# = 1 & dev # 1 enabled device# = 0 device# = 2 & dev# 2 enabled gmch generates misi type 1configuration cycle bus# = secondary bus in gmch dev 1 gmch generates dmi type 0 configuration cycle device# = 7& dev# 7 enabled gmch claims if function# = 0 gmch claims if function# = 0 gmch claims if function# = 0 gmch claims if function# = 0 yes no yes yes no no yes yes yes yes no no no no no device# = 0 gmch generates type 0 accessto pci express yes config_cyc_flow_915 register description r datasheet 63 3.4 i/o mapped registers the (g)mch contains two re gisters that reside in th e processor i/o address space ? the configuration address (conf ig_address) register and the configuration data (config_data) register. the configuration address register enables/disables the configuration space and determin es what portion of configura tion space is visible through the configuration data window. 3.4.1 config_address?configuration address register i/o address: 0cf8h accessed as a dword default value: 00000000h access: r/w size: 32 bits config_address is a 32-bit register that can be accessed only as a dw. a byte or word reference will "pass through" the configuration a ddress register and dmi onto the primary pci bus as an i/o cycle. the config_address register contains the bus number, device number, function number, and register number for which a subsequent configuration access is intended. bit access & default description 31 r/w 0b configuration enable (cfge): 1 = enable 0 = disable 30:24 reserved 23:16 r/w 00h bus number: if the bus number is programmed to 00h the target of the configuration cycle is a pci bus #0 agent. if this is the case and the (g)mch is not the target (i.e., the device number is 3 and not equal to 7), then a dmi type 0 configuration cycle is generated. if the bus number is non-zero, and does not fall within the ranges enumerated by device 1?s secondary bus number or s ubordinate bus number register, then a dmi type 1 configuration cycle is generated. if the bus number is non-zero and matches the value programmed into the secondary bus number register of device 1, a type 0 pci configuration cycle will be generated on pci express graphics. if the bus number is non-zero, greater than the value in the secondary bus number register of device 1 and less than or equal to the value programmed into the subordinate bus number register of device 1 a type 1 pci configuration cycle will be generated on pci express graphics. this field is mapped to byte 8 [7:0] of the request header format during pci express configuration cycles and a[23:16] during the dmi type 1 configuration cycles. register description r 64 datasheet bit access & default description 15:11 r/w 00h device number: this field selects one agent on the pci bus selected by the bus number. when the bus number field is ?00?, the (g)mch decodes the device number field. the (g)mch is always devi ce number 0 for the host bridge entity, device number 1 for the host-pci express entity. therefore, when the bus number =0 and the device number equals 0, 1, or 2 the internal (g)mch devices are selected. this field is mapped to byte 6 [7:3] of the request header format during pci express configuration cycles and a [15:11] during the dmi configuration cycles. 10:8 r/w 000b function number: this field allows the configur ation registers of a particular function in a multi-function device to be accessed. the (g)mch ignores configuration cycles to its internal devic es if the function number is not equal to 0 or 1. this field is mapped to byte 6 [2:0] of the request header format during pci express configuration cycles and a[10:8] during the dmi configuration cycles. 7:2 r/w 00h register number: this field selects one register wi thin a particular bus, device, and function as specified by the other fields in the configuration address register. this field is mapped to byte 7 [7:2] of the request header format during pci express configuration cycles and a[7:2] during the dmi configuration cycles. 1:0 reserved 3.4.2 config_data?configuration data register i/o address: 0cfch default value: 00000000h access: r/w size: 32 bits config_data is a 32-bit read/write window into configuration space. the portion of configuration space that is refe renced by config_data is dete rmined by the contents of config_address. bit access & default description 31:0 r/w 0000 0000h configuration data window (cdw): if bit 31 of config_address is 1, any i/o access to the config_data regi ster will produce a configuration transaction using the contents of config_address to determine the bus, device, function, and offset of the register to be accessed. host bridge/dram cont roller registers (d0:f0) r datasheet 65 4 host bridge/dram controller registers (d0:f0) the dram controller registers are in device 0 (d0), function 0 (f0). warning: address locations that are not listed are consid ered reserved registers locations. reads to reserved registers may return non-zero values. writes to reserved locations may cause system failures. all registers that are defined in the pci 2.3 specification, but are not necessary or implemented in this component are not included in this documen t. the reserved/unimplemented space in the pci configuration header space is not doc umented as such in this summary. table 4-1. device 0 function 0 register address map summary address offset register symbol register name default value access 00?01h vid vendor identification 8086h ro 02?03h did device identification 2580h ro 04?05h pcicmd pci command 0006h ro, r/w 06?07h pcists pci status 0090h ro, r/w/c 08h rid revision identification see register description ro 09?0bh cc class code 060000h ro 0ch ? reserved ? ? 0dh mlt master latency timer 00h ro 0eh hdr header type 00h ro 0f?2bh ? reserved ? ? 2c?2dh svid subsystem vendor identification 0000h r/w/o 2e?2fh sid subsystem identification 0000h r/w/o 30?33h ? reserved ? ? 34h capptr capabilities pointer eoh ro 35?3fh ? reserved ? ? 40?43h epbar egress port base address 00000000h ro 44?47h mchbar gmch memory mapped register range base address 00000000h r/w 48?4bh pciexbar pci express* regist er range base address e0000000h r/w 4c?4fh dmibar root complex register range base address 00000000h r/w host bridge/dram contro ller registers (d0:f0) r 66 datasheet address offset register symbol register name default value access 52?53h ggc gmch graphics control register (82915g gmch only) 0030h r/w/l 54?57h deven device enable 00000019h r/w 58?8fh ? reserved ? ? 90h pam0 programmable attribute map 0 00h r/w 91h pam1 programmable attribute map 1 00h r/w 92h pam2 programmable attribute map 2 00h r/w 93h pam3 programmable attribute map 3 00h r/w 94h pam4 programmable attribute map 4 00h r/w 95h pam5 programmable attribute map 5 00h r/w 96h pam6 programmable attribute map 6 00h r/w 97h lac legacy access control 00h r/w 98?9bh ? reserved ? ? 9ch tolud top of low usable dram 08h r/w 9dh smram system management ram control 00h ro, r/w/l 9eh esmramc extended system management ram control 00h ro, r/w/l 9f?c7h ? reserved ? ? c8?c9h errsts error status 0000h ro, r/w/l ca?cbh errcmd error command 0000h r/w cc?dbh ? reserved ? ? dc?dfh skpd scratchpad data 00000000h r/w e0?e8h capid0 capability identifier 0000000000 01090009h ro e9?ffh ? reserved ? ? 100h c0drb0 channel a dram rank boundary address 0 00h r/w 101h c0drb1 channel a dram rank boundary address 1 00h r/w 102h c0drb2 channel a dram rank boundary address 2 00h r/w 103h c0drb3 channel a dram rank boundary address 3 00h r/w 104?107h ? reserved ? ? 108h c0dra0 channel a dram rank 0,1 attribute 00h r/w 109h c0dra2 channel a dram rank 2,3 attribute 00h r/w 10a?10bh ? reserved ? ? 10ch c0dclkdis channel a dram clock disable 00h r/w 10dh ? reserved ? ? host bridge/dram cont roller registers (d0:f0) r datasheet 67 address offset register symbol register name default value access 10e?10f c0bnkarc channel a dram bank architecture 0000h r/w 110?113h ? reserved ? ? 114?117h c0drt1 channel a dram timing register 900122h r/w 118?11fh ? reserved ? ? 120?123h c0drc0 channel a dram controller mode 0 00000000h r/w, ro 124?17fh ? reserved ? ? 180h c1drb0 channel b dram rank boundary address 0 00h r/w 181h c1drb1 channel b dram rank boundary address 1 00h r/w 182h c1drb2 channel b dram rank boundary address 2 00h r/w 183h c1drb3 channel b dram rank boundary address 3 00h r/w 184?187h ? reserved ? ? 188h c1dra0 channel b dram rank 0,1 attribute 00h r/w 189h c1dra2 channel b dram rank 2,3 attribute 00h r/w 18a?18bh ? reserved ? ? 18ch c1dclkdis channel b dram clock disable 00h r/w 18dh ? reserved ? ? 18e?18fh c1bnkarc channel b bank architecture 0000h r/w 190?193h ? reserved ? ? 194h c1drt1 channel b dram timing register 1 900122h r/w, ro 195?19fh ? reserved ? ? 1a0?1a3h c1drc0 channel b dram controller mode 0 00000000h r/w, ro 1a4?f0fh ? reserved ? ? f10?f13h pmcfg power management configuration 00000000h r/w f14h pmsts power management status 00000000h r/w/c/s host bridge/dram contro ller registers (d0:f0) r 68 datasheet 4.1 host bridge/dram controller pci register details (d0:f0) 4.1.1 vid?vendor identification (d0:f0) pci device: 0 address offset: 00h default value: 8086h access: ro size: 16 bits this register combined with the device identification register uniquely identifies any pci device. bit access & default description 15:0 ro 8086h vendor identification number (vid): pci standard identification for intel. 4.1.2 did?device identification (d0:f0) pci device: 0 address offset: 02h default value: 2580h access: ro size: 16 bits this register combined with the vendor identification register uniquely identifies any pci device. bit access & default description 15:0 ro 2580h device identification number (did): this field is an identifier assigned to the (g)mch core/primary pci device. host bridge/dram cont roller registers (d0:f0) r datasheet 69 4.1.3 pcicmd?pci command (d0:f0) pci device: 0 address offset: 04h default value: 0006h access: ro, r/w size: 16 bits since (g)mch device 0 does not physically reside on primary pci bus, many of the bits are not implemented. bit access & default description 15:10 reserved 9 ro 0b fast back-to-back enable (fb2b). this bit controls whether or not the master can do fast back-to-back write. since device 0 is strictly a target this bit is not implemented and is hardwired to 0. 8 r/w 0b serr enable (serre). this bit is a global enabl e bit for device 0 serr messaging. the (g)mch does not have a serr signal. the (g)mch communicates the serr condition by sending an serr message over dmi to the ich6. 1 = enable. the (g)mch is enabled to generate serr messages over dmi for specific device 0 erro r conditions that are i ndividually enabled in the errcmd register. the error status is reported in the errsts, and pcists registers. if serre is clear, then the serr message is not generated by the (g)mch for device 0. 0 = disable note: that this bit only controls serr me ssaging for the device 0. device 1 has its own serre bits to control error repor ting for error conditions occurring in that device. the control bits are used in a logical or manner to enable the serr dmi message mechanism. 7 ro 0b address/data stepping enable (adstep). hardwired to 0. 6 ro 0b parity error enable (perre). perr# is not implemented by the (g)mch and this bit is hardwired to 0. 5 ro 0b vga palette snoop enable (vgasnoop). hardwired to a 0. 4 ro 0b memory write and invalidate enable (mwie). the (g)mch will never issue memory write and invalidate commands. this bit is therefore hardwired to 0. 3 ro 0b reserved 2 ro 1b bus master enable (bme). the (g)mch is always enabled as a master. this bit is hardwired to a "1". 1 ro 1b memory access enable (mae). the (g)mch always allows access to main memory. this bit is not implemented and is hardwired to 1. 0 ro 0b i/o access enable (ioae). hardwired to a 0. host bridge/dram contro ller registers (d0:f0) r 70 datasheet 4.1.4 pcists?pci status (d0:f0) pci device: 0 address offset: 06h default value: 0090h access: ro, r/w/c size: 16 bits this status register reports the occurrence of error events on device 0?s pci interface. since the (g)mch device 0 does not physically reside on primary pci, many of the bits are not implemented. bit access & default description 15 ro 0b detected parity error (dpe): hardwired to a 0. 14 r/w/c 0b signaled system error (sse): software clears this bit by writing a 1 to it. 1 = the (g)mch device 0 generated an serr message over dmi for any enabled device 0 error condition. device 0 error conditions are enabled in the pcicmd, and errcmd registers. device 0 error flags are read/reset from the pcists, or errsts registers. 13 r/wc 0b received master abort status (rmas): software clears this bit by writing a 1 to it. 1 = (g)mch generated a dmi request that receives an unsupported request completion packet. 12 r/wc 0b received target abort status (rtas): software clears this bit by writing a 1 to it. 1 = (g)mch generated a dmi request that receives a completer abort completion packet. 11 ro 0b signaled target abort status (stas): the (g)mch will not generate a target abort dmi completion packet or special cycl e. this bit is not implemented in the (g)mch and is hardwired to a 0. 10:9 ro 00b devsel timing (devt): these bits are hardwired to "00". device 0 does not physically connect to primary pci. these bi ts are set to "00" (fast decode) so that optimum devsel timing for primary pci is not limited by the (g)mch. 8 ro 0b master data parity error detected (dpd): perr signaling and messaging are not implemented by the (g)mch; therefore, this bit is hardwired to 0. 7 ro 1b fast back-to-back (fb2b): hardwired to 1. device 0 does not physically connect to primary pci. this bit is se t to 1 (indicating fast back-to-back capability) so that the optimum setting for primary pci is not limited by the (g)mch. 6 reserved 5 ro 0b 66 mhz capable: does not apply to pci express*. hardwired to 0. 4 ro 1b capability list (clist): this bit is hardwired to 1 to indicate to the configuration software that this device/function implem ents a list of new capabilities. a list of new capabilities is accessed via register capptr at configuration address offset 34h. register capptr contains an offset pointing to the start address within configuration space of th is device where the capability standard register resides. 3:0 reserved host bridge/dram cont roller registers (d0:f0) r datasheet 71 4.1.5 rid?revision identification (d0:f0) pci device: 0 address offset: 08h default value: see bit description access: ro size: 8 bits this register contains the revision number of the (g)mch device 0. bit access & default description 7:0 ro 00h revision identification number (rid): this field indicates the number of times that this device in this component has been ?stepped? through the manufacturing process. refer to the intel ? 82915g/82915p/82915gv/82910gl express chipset specification update for the value of the revision id register. 4.1.6 cc?class code (d0:f0) pci device: 0 address offset: 09h default value: 060000h access: ro size: 24 bits this register identifies the basic function of the device, a more specific s ub-class, and a register- specific programming interface. bit access & default description 23:16 ro 06h base class code (bcc): this is an 8-bit value that indicates the base class code for the (g)mch. 06h = bridge device. 15:8 ro 00h sub-class code (subcc): this is an 8-bit value that indicates the category of bridge into which the (g)mch falls. 00h = host bridge. 7:0 ro 00h programming interface (pi): this is an 8-bit value that indicates the programming interface of this device. th is value does not specify a particular register set layout and provides no practical use for this device. host bridge/dram contro ller registers (d0:f0) r 72 datasheet 4.1.7 mlt?master latency timer (d0:f0) pci device: 0 address offset: 0dh default value: 00h access: ro size: 8 bits device 0 in the (g)mch is not a pci master. th erefore, this register is not implemented. bit access & default description 7:0 reserved 4.1.8 hdr?header type (d0:f0) pci device: 0 address offset: 0eh default value: 00h access: ro size: 8 bits this register identifies th e header layout of the configuration space. no physical register exists at this location. bit access & default description 7:0 ro 00h pci header (hdr): this field always returns 0 to indicate that the (g)mch is a single function device with standard header layout. 4.1.9 svid?subsystem vendor identification (d0:f0) pci device: 0 address offset: 2ch default value: 0000h access: r/wo size: 16 bits this value is used to identify the vendor of the subsystem. bit access & default description 15:0 r/wo 0000h subsystem vendor id (subvid): this field should be programmed during boot- up to indicate the vendor of the system board. after it has been written once, it becomes read only. host bridge/dram cont roller registers (d0:f0) r datasheet 73 4.1.10 sid?subsystem identification (d0:f0) pci device: 0 address offset: 2eh default value: 0000h access: r/w/o size: 16 bits this value is used to identify a particular subsystem. bit access & default description 15:0 r/wo 0000h subsystem id (subid) : this field should be programmed during bios initialization. after it has been wr itten once, it becomes read only. 4.1.11 capptr?capabilities pointer (d0:f0) pci device: 0 address offset: 34h default value: e0h access: ro size: 8 bits the capptr provides the offset that is the pointer to the location of the first device capability in the capability list. bit access & default description 7:0 ro e0h pointer to the offset of the fi rst capability id register block: in this case the first capability is the product-specif ic capability identifier (capid0). host bridge/dram contro ller registers (d0:f0) r 74 datasheet 4.1.12 epbar?egress port base address (d0:f0) pci device: 0 address offset: 40h default value: 00000000h access: ro size: 32 bits this is the base address for the egress port mmio configuration space. there is no physical memory within this 4-kb window that can be addressed. the 4 kb reserved by this register does not alias to any pci 2.3 compliant memory-mapped space. on reset, this register is disabled and must be enabled by writing a 1 to epbaren[dev 0, offset 54h, bit 27] bit access & default description 31:12 r/w 00000h egress port mmio base address: this field corresponds to bits 31 to 12 of the base address egress port mmio configuration space. bios will program this register result ing in a base address for a 4-kb block of contiguous memory address space. this r egister ensures that a naturally aligned 4-kb space is allocated within total addressable memory space of 4 gb. system software uses this base address to program the (g)mch mmio register set. 11:0 reserved host bridge/dram cont roller registers (d0:f0) r datasheet 75 4.1.13 mchbar?(g)mch memory mapped register range base address (d0:f0) pci device: 0 address offset: 44h default value: 00000000h access: r/w size: 32 bits this is the base address for the (g)mch me mory-mapped configuration space. there is no physical memory within this 16-kb window that can be addressed. the 16 kb reserved by this register does not alias to any pci 2.3 compliant memory mapped space. on reset, this register is disabled and must be enabled by writing a 1 to mchbaren [dev 0, offset 54h, bit 28] bit access & default description 31:14 r/w 00000h (g)mch memory mapped base address: this field corresponds to bits 31:14 of the base address (g)mch memory -mapped configuration space. bios will program this register result ing in a base address for a 16-kb block of contiguous memory address space. this r egister ensures that a naturally aligned 16-kb space is allocated within total addressable memory space of 4 gb. system software uses this base address to program the (g)mch memory- mapped register set. 13:0 reserved host bridge/dram contro ller registers (d0:f0) r 76 datasheet 4.1.14 pciexbar?pci express* register range base address (d0:f0) (intel ? 82915g/82915p/82915pl only) pci device: 0 address offset: 48h default value: e0000000h access: r/w size: 32 bits this is the base address for the pci express configuration space. this window of addresses contains the 4 kb of configura tion space for each pci express devi ce that can potentially be part of the pci express hierarchy a ssociated with the (g)mch. ther e is not actual physical memory within this 256-mb window that can be addressed. each pci express hierarchies require a pci express base register. the (g)mch supports one pci express hierarchy. the 256 mb reserved by this register does not alias to any pci 2.3 compliant memory-mapped space. for example, mchbar reserves a 16-kb space and reserves a 4-kb space both outside of pciexbar space. they cannot be overlaid on the space reserved by pciexbar for devices 0. on reset, this register is disabled and must be enabled by writing a 1 to pciexbaren [dev 0, offset 54h, bit 31] if the pci express base address [bits 31:28] were set to fh, an overlap with the high bios area, apic ranges would result. soft ware must guarantee that these ranges do not overlap. the pci express base address cannot be less than the maximum address written to the top of physical memory register (tolud). if a system is populated with more than 3.5 gb, either the pci express enhanced access mechanism must be disabled or the value in tolud must be reduced to report that only 3.5 gb are present in the syst em to allow a value of eh for the pci express base address (assuming that all pci 2.3 compa tible configuration space fits above 3.75 gb). bit access & default description 31:28 r/w eh pci express* base address: this field corresponds to bits 31 to 28 of the base address for pci express enhanced configuration space. bios will program this register result ing in a base address for a 256-mb block of contiguous memory address space. havi ng control of those particular 4 bits insures that this base address will be on a 256-mb boundary, above the lowest 256 mb and still within total addressable memory space, currently 4 gb. the address used to access the pci expre ss configuration space for a specific device can be determined as follows: pci express base address + bus number * 1 mb + device number * 32 kb + function number * 4 kb the address used to access the pci express configuration space for device 1 in this component would be pci express base address + 0 * 1 mb + 1 * 32 kb + 0 * 4 kb = pci express base address + 32 kb . remember that this address is the beginning of the 4-kb s pace that contains both the pci compatible configuration space and t he pci express extended configuration space. 27:0 reserved host bridge/dram cont roller registers (d0:f0) r datasheet 77 4.1.15 dmibar?root complex register range base address (d0:f0) pci device: 0 address offset: 4ch default value: 00000000h access: r/w size: 32 bits this is the base address for the root comple x configuration space. th is window of addresses contains the root complex register set for th e pci express hierarchy associated with the (g)mch. there is no physical memory within this 4-kb window that can be addressed. the 4 kb that is reserved by this register does not alias to any pci 2.3 compliant memory mapped space. on reset, this register is disabled and must be enabled by writing a 1 to the dmibaren [dev 0, offset 54h, bit 29]. | bit access & default description 31:12 r/w 0000 0h dmi base address: this field corresponds to bits 31 to 12 of the base address dmi configuration space. bios will program this register result ing in a base address for a 4-kb block of contiguous memory address space. this register ensures that a naturally aligned 4-kb space is allocated within total addressable memory space of 4 gb. system software uses this base addre ss to program the dmi register set. 11:0 reserved host bridge/dram contro ller registers (d0:f0) r 78 datasheet 4.1.16 ggc?gmch graphics control register (d0:f0) (82915g/82915gv/82915GL/82910gl gmch only) pci device: 0 address offset: 52h default value: 0030h access: r/w/l size: 16 bits bit access & default descriptions 15:7 reserved 6:4 r/w/l 011b graphics mode select (gms): this field is used to select the amount of main memory that is pre-allocated to s upport the internal graphics device in vga (non-linear) and native (linear) modes. the bios ensures that memory is pre- allocated only when internal graphics is enabled. device 2 (igd) does not claim vga cycles (memory and i/o), and the sub- class code field within device 2, function 0 class code register is 80h. 000 = no memory pre-allocated 001 = dvmt (uma) mode, 1 mb of memory pre-allocated for frame buffer. 010 = reserved. 011 = dvmt (uma) mode, 8 mb of memory pre-allocated for frame buffer. 100?111 = reserved. notes: 1. this register is locked and becomes read only when the d_lck bit in the smram register is set. 2. if igd is disabled, this field should be set to 000. 3:2 reserved 1 r/w 0b igd vga disable (ivd): 0 = enable. device 2 (igd) claims vg a memory and i/o cycles, the sub-class code within device 2 class code register is 00h. 1 = disable. device 2 (igd) does not claim vga cycles (memory and i/o), and the sub-class code field within device 2, function 0 class code register is 80h. 0 reserved host bridge/dram cont roller registers (d0:f0) r datasheet 79 4.1.17 deven?device enable (d0:f0) pci device: 0 address offset: 54h default value: 00000019h access: r/w size: 32 bits this register allows for enabling/disabling of pci devices and functions that are within the (g)mch. bit access & default description 31 r/w 0b 82915g/82915p/82915pl (g)mch: pciexbar enable (pciexbaren): 0 = the pciexbar register is disabl ed. memory read and write transactions proceed as if there were no pciexbar register. pciexbar bits 31:28 are r/w with no functionality behind them. 1 = the pciexbar register is enabled. memory read and write transactions whose address bits 31:28 match pciexbar 31:28 will be translated to configuration reads and writes within the (g)mch. these translated cycles are routed as shown in the table above. 82915gv/82915GL/82910gl gmch: reserved. 30 reserved 29 r/w 0b dmibar enable (dmibaren): 0 = dmibar is disabled and does not claim any memory. 1 = dmibar memory mapped accesses are claimed and decoded appropriately. 28 r/w 0b mchbar enable (mchbaren): 0 = mchbar is disabled and does not claim any memory. 1 = mchbar memory mapped accesses are claimed and decoded appropriately. 27 r/w 0b epbar enable (epbaren): 0 = epbar is disabled and does not claim any memory. 1 = epbar memory mapped accesses are claimed and decoded appropriately. 26:5 reserved host bridge/dram contro ller registers (d0:f0) r 80 datasheet bit access & default description 4 r/w 1b 82915g/82915gv/82915GL/82910gl gmch: internal graphics engine function 1 (d2f1en): 0 = bus 0 device 2 function 1 is disabled and hidden 1 = bus 0 device 2 function 1 is enabled and visible note: setting this bit to enabled w hen bit 3 is 0 has no meaning. 82915p/82915pl mch: reserved. 3 r/w 1b 82915g/82915gv/82915GL/82910gl gmch: internal graphics engine function 0 (d2f0en): 0 = bus 0 device 2 function 0 is disabled and hidden 1 = bus 0 device 2 function 0 is enabled and visible 82915p/82915pl mch: reserved. 2 reserved 1 r/w 1b strap dependent 82915g/82915p/82915pl (g)mch: pci express* port (d1en): 0 = bus 0 device 1 function 0 is di sabled and hidden. this also gates pci express internal clock (lgclk) and assert s pci express inter nal reset (lgrstb). 1 = bus 0 device 1 function 0 is enabled and visible. the sdvo presence hardware strap deter mines default value. device 1 is disabled on reset when the sdvo presenc e strap (sdvo_ctlrdata signal) is sampled high, and is enabled otherwise. 82915gv/82915GL/82910gl gmch: reserved. 0 ro 1b host bridge: bus 0 device 0 function 0 can not be disabled and is therefore hardwired to 1. host bridge/dram cont roller registers (d0:f0) r datasheet 81 4.1.18 pam0?programmable attribute map 0 (d0:f0) pci device: 0 address offset: 90h default value: 00h access: r/w size: 8 bits this register controls the read, write, and shadowing attributes of the bios area from 0f0000h? 0fffffh the (g)mch allows programmable memory attributes on 13 legacy memory segments of various sizes in the 768-kb to 1-mb address range. seven programmable attribute map (pam) registers are used to support these features. c ache ability of these areas is controlled via the mtrr registers in the processor. two bits are used to specify memory attributes for each memory segment. these bits apply to both host accesses and pci initiator accesses to the pam areas. these attributes are: ? re (read enable). when re = 1, the pro cessor read accesses to the corresponding memory segment are claimed by the (g)mch and directed to main memory. conversely, when re = 0, the host read accesses ar e directed to primary pci. ? we (write enable). when we = 1, the host write accesses to the corresponding memory segment are claimed by the (g)mch and directed to main memory. conversely, when we = 0, the host write accesses ar e directed to primary pci. the re and we attributes permit a memory segment to be read only, write only, read/write, or disabled. for example, if a memory segment has re = 1 and we = 0, the segment is read only. each pam register controls two regions, typically 16 kb in size. bit access & default description 7:6 reserved 5:4 r/w 00b 0f0000-0fffff attribute (hienable): this field controls the steering of read and write cycles that addresses the bios area from 0f0000h to 0fffffh. 00 = dram disabled: all accesses are directed to the dmi. 01 = read only: all reads are sent to dram. all writes are forwarded to the dmi. 10 = write only: all writes are sent to dram. reads are serviced by dmi. 11 = normal dram operation: all reads and writes are serviced by dram. 3:0 reserved warning: the (g)mch may hang if a pci express graphics attach or dmi originated access to read disabled or write disabled pam segments occurs (due to a possible iwb to non-dram). for these reasons the following critical restriction is placed on the programming of the pam regions: at the time that a dmi or pci express graphics attach accesses to the pa m region may occur, the targeted pam segment must be programmed to be both readable and writeable. host bridge/dram contro ller registers (d0:f0) r 82 datasheet 4.1.19 pam1?programmable attribute map 1 (d0:f0) pci device: 0 address offset: 91h default value: 00h access: r/w size: 8 bits this register controls the read, write, and shadowing attributes of the bios areas from 0c0000h? 0c7fffh. bit access & default description 7:6 reserved 5:4 r/w 00b 0c4000-0c7fff attribute (hienable): this field controls the steering of read and write cycles that address the bios area from 0c4000h to 0c7fffh. 00 = dram disabled: accesses are directed to the dmi. 01 = read only: all reads are serviced by dram. all writes are forwarded to the dmi. 10 = write only: all writes are sent to dram. reads are serviced by dmi. 11 = normal dram operation: all reads and writes are serviced by dram. 3:2 reserved 1:0 r/w 00b 0c0000-0c3fff attribute (loenable): this field controls the steering of read and write cycles that address the bios area from 0c0000h to 0c3fffh. 00 = dram disabled: accesses are directed to the dmi. 01 = read only: all reads are serviced by dram. all writes are forwarded to the dmi. 10 = write only: all writes are sent to dram. reads are serviced by dmi. 11 = normal dram operation: all reads and writes are serviced by dram. host bridge/dram cont roller registers (d0:f0) r datasheet 83 4.1.20 pam2?programmable attribute map 2 (d0:f0) pci device: 0 address offset: 92h default value: 00h access: r/w size: 8 bits this register controls the read, write, and shadowing attributes of the bios areas from 0c8000h? 0cffffh. bit access & default description 7:6 reserved 5:4 r/w 00b 0cc000h?0cffffh attribute (hienable): 00 = dram disabled: accesses are directed to the dmi. 01 = read only: all reads are serviced by dram. all writes are forwarded to the dmi. 10 = write only: all writes are sent to dram. reads are serviced by dmi. 11 = normal dram operation: all reads and writes are serviced by dram. 3:2 reserved 1:0 r/w 00b 0c8000h?0cbfffh attribute (loenable): this field controls the steering of read and write cycles that address the bios area from 0c8000h to 0cbfffh. 00 = dram disabled: accesses are directed to the dmi. 01 = read only: all reads are serviced by dram. all writes are forwarded to the dmi. 10 = write only: all writes are sent to dram. reads are serviced by dmi. 11 = normal dram operation: all reads and writes are serviced by dram. host bridge/dram contro ller registers (d0:f0) r 84 datasheet 4.1.21 pam3?programmable attribute map 3 (d0:f0) pci device: 0 address offset: 93h default value: 00h access: r/w size: 8 bits this register controls the read, write, and shadowing attributes of the bios areas from 0d0000h? 0d7fffh. bit access & default description 7:6 reserved 5:4 r/w 00b 0d4000h?0d7fffh attribute (hienable): this field controls the steering of read and write cycles that address the bios area from 0d4000h to 0d7fffh. 00 = dram disabled: accesses are directed to the dmi. 01 = read only: all reads are serviced by dram. all writes are forwarded to the dmi. 10 = write only: all writes are sent to dram. reads are serviced by dmi. 11 = normal dram operation: all reads and writes are serviced by dram. 3:2 reserved 1:0 r/w 00b 0d0000h?0d3fffh attribute (loenable): this field controls the steering of read and write cycles that address the bios area from 0d0000h to 0d3fffh. 00 = dram disabled: accesses are directed to the dmi. 01 = read only: all reads are serviced by dram. all writes are forwarded to the dmi. 10 = write only: all writes are sent to dram. reads are serviced by dmi. 11 = normal dram operation: all reads and writes are serviced by dram. host bridge/dram cont roller registers (d0:f0) r datasheet 85 4.1.22 pam4?programmable attribute map 4 (d0:f0) pci device: 0 address offset: 94h default value: 00h access: r/w size: 8 bits this register controls the read, write, and shadowing attributes of the bios areas from 0d8000h- 0dffffh. bit access & default description 7:6 reserved 5:4 r/w 00b 0dc000h?0dffffh attribute (hienable): this field controls the steering of read and write cycles that address the bios area from 0dc000h to 0dffffh. 00 = dram disabled: accesses are directed to the dmi. 01 = read only: all reads are serviced by dram. all writes are forwarded to the dmi. 10 = write only: all writes are sent to dram. reads are serviced by dmi. 11 = normal dram operation: all reads and writes are serviced by dram. 3:2 reserved 1:0 r/w 00b 0d8000h?0dbfffh attribute (loenable): this field controls the steering of read and write cycles that address the bios area from 0d8000h to 0dbfffh. 00 = dram disabled: accesses are directed to the dmi. 01 = read only: all reads are serviced by dram. all writes are forwarded to the dmi. 10 = write only: all writes are sent to dram. reads are serviced by dmi. 11 = normal dram operation: all reads and writes are serviced by dram. host bridge/dram contro ller registers (d0:f0) r 86 datasheet 4.1.23 pam5?programmable attribute map 5 (d0:f0) pci device: 0 address offset: 95h default value: 00h access: r/w size: 8 bits this register controls the read, write, and shadowing attributes of the bios areas from 0e0000h- 0e7fffh. bit access & default description 7:6 reserved 5:4 r/w 00b 0e4000h?0e7fffh attribute (hienable): this field controls the steering of read and write cycles that address the bios area from 0e4000h to 0e7fffh. 00 = dram disabled: accesses are directed to the dmi. 01 = read only: all reads are serviced by dram. all writes are forwarded to the dmi. 10 = write only: all writes are sent to dram. reads are serviced by dmi. 11 = normal dram operation: all reads and writes are serviced by dram. 3:2 reserved 1:0 r/w 00b 0e0000h?0e3fffh attribute (loenable): this field controls the steering of read and write cycles that address the bios area from 0e0000h to 0e3fffh. 00 = dram disabled: accesses are directed to the dmi. 01 = read only: all reads are serviced by dram. all writes are forwarded to the dmi. 10 = write only: all writes are sent to dram. reads are serviced by dmi. 11 = normal dram operation: all reads and writes are serviced by dram. host bridge/dram cont roller registers (d0:f0) r datasheet 87 4.1.24 pam6?programmable attribute map 6 (d0:f0) pci device: 0 address offset: 96h default value: 00h access: r/w size: 8 bits this register controls the read, write, and shadowing attributes of the bios areas from 0e8000h? 0effffh. bit access & default description 7:6 reserved 5:4 r/w 00b 0ec000h?0effffh attribute (hienable): this field controls the steering of read and write cycles that address the bios area from 0e4000h to 0e7fffh. 00 = dram disabled: accesses are directed to the dmi. 01 = read only: all reads are serviced by dram. all writes are forwarded to the dmi. 10 = write only: all writes are sent to dram. reads are serviced by dmi. 11 = normal dram operation: all reads and writes are serviced by dram. 3:2 reserved 1:0 r/w 00b 0e8000h?0ebfffh attribute (loenable): this field controls the steering of read and write cycles that address the bios area from 0e0000h to 0e3fffh. 00 = dram disabled: accesses are directed to the dmi. 01 = read only: all reads are serviced by dram. all writes are forwarded to the dmi. 10 = write only: all writes are sent to dram. reads are serviced by dmi. 11 = normal dram operation: all reads and writes are serviced by dram. host bridge/dram contro ller registers (d0:f0) r 88 datasheet 4.1.25 lac?legacy access control (d0:f0) pci device: 0 address offset: 97h default value: 00h access: r/w size: 8 bits this 8-bit register controls a fixed dram hole from 15?16 mb. bit access & default description 7 r/w 0b hole enable (hen): this field enables a memory hole in dram space. the dram that lies "behind" this space is not remapped. 0 = no memory hole. 1 = memory hole from 15 mb to 16 mb. 6:1 reserved 0 r/w 0b mda present (mdap): this bit works with the vga enable bits in the bctrl register of device 1 to control the routing of processor initiated transactions targeting mda compatible i/o and memory address ranges. this bit should not be set if device 1's vga enable bit is not set. if device 1's vga enable bit is not set, then accesses to i/o address range x3bch? x3bfh are forwarded to the dmi. if the vga enable bit is set and mda is not present, then accesses to i/o address range x3bch?x3bfh are forwarded to pci ex press* if the address is within the corresponding iobase and iolimit, otherwise they are forwarded to the dmi. mda resources are defined as the following: memory: 0b0000h ? 0b7fffh i/o: 3b4h, 3b5h, 3b8h, 3b9h, 3bah, 3bfh, (including isa address aliases, a [15:10] are not used in decode) any i/o reference that includes the i/o locati ons listed above, or their aliases, will be forwarded to the dmi even if the referenc e includes i/o locations not listed above. the following table shows the behavior for all combinations of mda and vga: vgaen mdap description 0 0 all references to mda and vga space are routed to the dmi 0 1 illegal combination 1 0 all vga and mda references are routed to pci express graphics attach. 1 1 all vga references ar e routed to pci express graphics attach. mda references are routed to the dmi host bridge/dram cont roller registers (d0:f0) r datasheet 89 4.1.26 tolud?top of low usable dram (d0:f0) pci device: 0 address offset: 9ch default value: 08h access: r/w size: 8 bits this 8-bit register defines the top of low usable dram. tseg and graphics stolen memory (82915g only) are within the dram space defined. from the top, the (g)mch optionally claims 1 to 32 mb of dram for internal graphics if enabled (82915g/82915gv/82915GL/82910gl gmch only), and 1, 2, or 8 mb of dram for tseg if enabled. these bits are lt lockable. bit access & default description 7:3 r/w 01h top of low usable dram (tolud): this register contains bits 31:27 of an address one byte above the maximum dram memory that is usable by the operating system. address bits 31:27 programmed to 01h implies a minimum memory size of 128 mbs. configuration software must set this value to the smaller of the following 2 choices: ? maximum amount memory in the system plus one byte or the minimum address allocated for pci memory. address bits 26:0 are assumed to be 000_0000h for the purposes of address comparison. the host interface positivel y decodes an address towards dram if the incoming address is less than the val ue programmed in this register. if this register is set to 0000 0b, it implies 128 mbs of system memory. note: the top of low usable dram is the lowest address above both graphics stolen memory (82915g/82915gv/82915GL/ 82910gl only) and tseg. the host interface determines the base of graphi cs stolen memory by subtracting the graphics stolen memory size from tolud and further decrements by 1 mb to determine base of tseg. 2:0 reserved programming example (82915g/82915gv/82915GL/82910gl gmch only): ? c1drb7 is set to 4 gb ? tseg is enabled and tseg size is set to 1 mb ? internal graphics is enabled and graphics mode select is set to 32 mb ? bios knows the os requires 1g of pci space. bios also knows the range from fec0_0000h to ffff_ ffffh is not usable by the system. this 20-mb range at the very top of addressable memory space is lost to apic. according to the above equation, tolud is originally calculated to: 4 gb = 1_0000_0000h the system memory requirements are: 4 gb (max addressable space) ? 1 gb (pci space) ? 20 mb (lost memory) = 3 gb ? 128 mb (minimum granularity) = b800_0000h since b800_0000h (pci and other system requirements) is less than 1_0000_0000h, tolud should be programmed to b8h. host bridge/dram contro ller registers (d0:f0) r 90 datasheet 4.1.27 smram?system management ram control (d0:f0) pci device: 0 address offset: 9dh default value: 00h access: r/w/l, ro size: 8 bits the smramc register controls how accesses to compatible and extended smram spaces are treated. the open, close, and lock bits function only when g_smrame bit is set to a 1. also, the open bit must be reset before the lock bit is set. bit access & default description 7 reserved 6 r/w/l 0b smm space open (d_open): when d_open=1 and d_lck=0, the smm space dram is made visible even when smm decode is not active. this is intended to help bios initialize smm space. software should ensure that d_open=1 and d_cls=1 are not set at the same time. 5 r/w/l 0b smm space closed (d_cls): when d_cls = 1 smm space dram is not accessible to data references, even if smm decode is active. code references may still access smm space dram. this will allow smm software to reference through smm space to update the displa y even when smm is mapped over the vga range. software should ensure that d_open=1 and d_cls=1 are not set at the same time. note that the d_cls bit only applies to compatible smm space. 4 r/w/l 0b smm space locked (d_lck): when d_lck is set to 1, d_open is reset to 0 and d_lck, d_open, c_base_seg, h_smram_en, tseg_sz and tseg_en become read only. d_lck can be set to 1 via a normal configuration space write but can only be cleared by a full reset. the combination of d_lck and d_open provide convenience with security. the bios can use the d_open function to initialize smm space and then use d_lck to "lock down" smm space in the future so that no application software (or bios itself) can violate the integrity of smm space, ev en if the program has knowledge of the d_open function. 3 r/w/l 0b global smram enable (g_smrame): if set to a 1, compatible smram functions are enabled, providing 128 kb of dram accessible at the a0000h address while in smm (adsb with smm decode). to enable extended smram function this bit has be set to 1. refer to the section on smm for more details. once d_lck is set, this bit becomes read only. 2:0 ro 010b compatible smm space base segment (c_base_seg): this field indicates the location of smm space. smm dram is not remapped. it is simply made visible if the conditions are right to a ccess smm space, otherwise the access is forwarded to dmi. since the (g)mch supports only the smm space between a0000h and bffffh, this field is hardwired to 010. host bridge/dram cont roller registers (d0:f0) r datasheet 91 4.1.28 esmramc?extended system management ram control (d0:f0) pci device: 0 address offset: 9eh default value: 00h access: r/w/l, ro size: 8 bits the extended smram register controls the configuration of extended smram space. the extended smram (e_smram) me mory provides a write-back cacheable smram memory space that is above 1 mb. bit access & default description 7 r/w/l 0b enable high smram (h_smrame): this bit controls the smm memory space location (i.e., above 1 mb or below 1 mb ). when g_smrame is 1 and h_smrame is 1, the high smram memory space is enabled. smram accesses within the range 0feda0000h to 0fedbffffh are remapped to dram addresses within the range 000a0000h to 000bffffh. once d_lck has been set, this bit becomes read only. 6 r/w/c 0b invalid smram access (e_smerr): this bit is set when the processor has accessed the defined memory ranges in extended smram (high memory and t- segment) while not in smm space and with the d-open bit = 0. it is software?s responsibility to clear this bit. the software must write a 1 to this bit to clear it. 5 ro 1b smram cacheable (sm_cache): this bit is forced to 1 by the (g)mch . 4 ro 1b l1 cache enable for smram (sm_l1): this bit is forced to 1 by the (g)mch. 3 ro 1b l2 cache enable for smram (sm_l2): this bit is forced to 1 by the (g)mch. 2:1 r/w/l 00b tseg size (tseg_sz): this field selects the size of the tseg memory block if enabled. memory from the top of dram spac e is partitioned away so that it may only be accessed by the processor interf ace and only then when the smm bit is set in the request packet. non-smm accesses to this memory region are sent to the dmi when the tseg memory block is enabled. 00 = 1-mb tseg. (tolud ? graphics stolen memory size ? 1m) to (tolud ? graphics stolen memory size). 01 = 2-mb tseg (tolud ? graphics stolen memory size ? 2m) to (tolud ? graphics stolen memory size). 10 = 8-mb tseg (tolud ? graphics stolen memory size ? 8m) to (tolud ? graphics stolen memory size). 11 = reserved. once d_lck has been set, these bits become read only. note: references to graphics stolen memory only apply to the 82915g/82915gv/82915GL/82910gl gmch only. 0 r/w/l 0b tseg enable (t_en): this bit enables smram memory for extended smram space only. when g_smrame =1 and t seg_en = 1, the tseg is enabled to appear in the appropriate physical address spac e. note that once d_lck is set, this bit becomes read only. host bridge/dram contro ller registers (d0:f0) r 92 datasheet 4.1.29 errsts?error status (d0:f0) pci device: 0 address offset: c8h default value: 0000h access: r/wc/s, ro size: 16 bits this register is used to report various error conditions via the serr dmi messaging mechanism. a serr dmi message is generated on a zero to one transition of any of these flags (if enabled by the errcmd and pcicmd registers). these bits are set regardless of whether or not the serr is enabled and generated. after the error processing is complete, the error logging mechanism can be unlocked by clearing the appropriate status bit by software writing a 1 to it. 0bit access & default description 15:13 reserved 12 r/wc/s 0b (g)mch software generated event for smi: 1 = this bit indicates the source of the smi was a device 2 software event. 11 r/wc/s 0b (g)mch thermal sensor event for smi/sci/serr: this bit indicates that a (g)mch thermal sensor trip has o ccurred and an smi, sci, or serr has been generated. the status bit is set only if a message is sent based on thermal event enables in error command, smi command, and sci command registers. a trip point can generate one of smi, sci, or serr interrupts (two or more per event is illegal). multiple trip points c an generate the same interrupt, if software chooses this mode, subsequent trips may be lost. if this bit is already set, an interrupt message will not be sent on a new thermal sensor event. 10 reserved 9 r/wc/s 0b lock to non-dram memory flag (lckf): 1 = (g)mch detected a lock operation to memory space that did not map into dram. 8 r/wc/s 0b received refresh timeout flag(rrtof): 1 = 1024 memory core refreshes are enqueued. 7:0 reserved host bridge/dram cont roller registers (d0:f0) r datasheet 93 4.1.30 errcmd?error command (d0:f0) pci device: 0 address offset: cah default value: 0000h access: r/w size: 16 bits this register controls the (g)mch responses to various system errors. since the (g)mch does not have an serr# signal, serr messages are passed from the (g)mch to the intel ich6 over dmi. when a bit in this register is set, a serr message will be generated on dmi when the corresponding flag is set in the errsts register. the actual generation of the serr message is globally enabled for device 0 via the pci command register. bit access & default description 15:12 reserved 11 r/w 0b serr on (g)mch thermal sensor event (tseserr) 1 = the (g)mch generates a dmi serr special cycle when bit 11 of the errsts is set. the serr must not be enabled at the same time as the smi for the same thermal sensor event. 0 = reporting of this condition vi a serr messaging is disabled. 10 reserved 9 r/w 0b serr on lock to non-dram memory (lckerr) 1 = the (g)mch will generate a dmi serr special cycle whenever a processor lock cycle is detected that does not hit dram. 0 = reporting of this condition via serr messaging is disabled. 8 r/w 0b serr on dram refresh timeout (drtoerr) 1 = the (g)mch generates a dmi serr special cycle when a dram refresh timeout occurs. 0 = reporting of this condition via serr messaging is disabled. 7:0 reserved host bridge/dram contro ller registers (d0:f0) r 94 datasheet 4.1.31 skpd?scratchpad data (d0:f0) pci device: 0 address offset: dch default value: 00000000h access: r/w size: 32 bits this register holds 32 writable bits with no func tionality behind them. it is for the convenience of bios and graphics drivers. bit access & default description 31:0 r/w 00000000 h scratchpad data: 1 dword of data storage. 4.1.32 capid0?capability identifier (d0:f0) pci device: 0 address offset: e0h default value: 000000000001090009h access: ro size: 72 bits bit access & default description 71:28 reserved 27:24 ro 1h capid version: this field has the value 0001b to i dentify the first revision of the capid register definition. 23:16 ro 09h capid length: this field has the value 09h to indicate the structure length (9 bytes). 15:8 ro 00h next capability pointer: this field is hardwired to 00h indicating the end of the capabilities linked list. 7:0 ro 09h cap_id: this field has the value 1001b to identify the cap_id assigned by the pci sig for vendor dependent capability pointers. mchbar registers r datasheet 95 5 mchbar registers these registers are offset fro m the mchbar base address. address offset register symbol register name default value access 100h c0drb0 channel a dram rank boundary address 0 00h r/w 101h c0drb1 channel a dram rank boundary address 1 00h r/w 102h c0drb2 channel a dram rank boundary address 2 00h r/w 103h c0drb3 channel a dram rank boundary address 3 00h r/w 104?107h ? reserved ? ? 108h c0dra0 channel a dram rank 0,1 attribute 00h r/w 109h c0dra2 channel a dram rank 2,3 attribute 00h r/w 10a?10bh ? reserved ? ? 10ch c0dclkdis channel a dram clock disable 00h r/w 10dh ? reserved ? ? 10e?10f c0bnkarc channel a dram bank architecture 0000h r/w 110?113h ? reserved ? ? 114?117h c0drt1 channel a dram timing register 900122h r/w 118?11fh ? reserved ? ? 120?123h c0drc0 channel a dram controller mode 0 00000000h r/w, ro 124?17fh ? reserved ? ? 180h c1drb0 channel b dram rank boundary address 0 00h r/w 181h c1drb1 channel b dram rank boundary address 1 00h r/w 182h c1drb2 channel b dram rank boundary address 2 00h r/w 183h c1drb3 channel b dram rank boundary address 3 00h r/w 184?187h ? reserved ? ? 188h c1dra0 channel b dram rank 0,1 attribute 00h r/w 189h c1dra2 channel b dram rank 2,3 attribute 00h r/w 18a?18bh ? reserved ? ? 18ch c1dclkdis channel b dram clock disable 00h r/w 18dh ? reserved ? ? 18e?18fh c1bnkarc channel b bank architecture 0000h r/w 190?193h ? reserved ? ? 194h c1drt1 channel b dram timing register 1 900122h r/w, ro mchbar registers r 96 datasheet address offset register symbol register name default value access 195?19fh ? reserved ? ? 1a0?1a3h c1drc0 channel b dram controller mode 0 00000000h r/w, ro 1a4?f0fh ? reserved ? ? f10?f13h pmcfg power management configuration 00000000h r/w f14h pmsts power management status 00000000h r/w/c/s 5.1 mchbar register details 5.1.1 c0drb0?channel a dram rank boundary address 0 mmio range: mchbar address offset: 100h default value: 00h access: r/w size: 8 bits the dram rank boundary register defines the upper boundary a ddress of each dram rank with a granularity of 32 mb. each rank has its own single-byte drb register. these registers are used to determine which chip select will be active for a given address. channel and rank map: channel a rank 0: 100h channel a rank 1: 101h channel a rank 2: 102h channel a rank 3: 103h channel b rank 0: 180h channel b rank 1: 181h channel b rank 2: 182h channel b rank 3: 183h single channel or asymmetric channels example if the channels are independent, addresses in ch annel b should begin where addresses in channel a left off, and the address of the first rank of channel a can be calculated from the technology (256 mbit, 512 mbit, or 1 gbit) and the x8 or x16 configuration. with independent channels, a value of 01h in c0drb0 indicates that 32 mb of dram has been populated in the first rank, and the top address in that rank is 32 mb. mchbar registers r datasheet 97 programming guide if channel a is empty, all of the c0drbs are programmed with 00h. c0drb0 = total memory in cha rank0 (in 32-mb increments) c0drb1 = total memory in cha rank0 + cha rank1 (in 32-mb increments) ______ c1drb0 = total memory in cha rank0 + cha rank1 + cha rank2 + cha rank3 + chb rank0 (in 32-mb increments) if channel b is empty, all of the c1drbs ar e programmed with the same value as c0drb3. interleaved channels example if channels are interleaved, corresponding ranks in opposing channels will contain the same value, and the value programmed takes into account the fact that twice as many addresses are spanned by this rank compared to the single channel case. with interleaved channels, a value of 01h in c0drb0 and a value of 01h in c1drb0 indicate that 32 mb of dram has been populated in the first rank of each channel and the top addre ss in that rank of either channel is 64 mb. programming guide: c0drb0 = c1drb0 = total memory in cha rank0 (in 32-mb increments) c0drb1 = c1drb1 = total memory in cha rank0 + cha rank1 (in 32-mb increments) ______ c0drb3 = c1drb3 = total memory in cha rank0 + cha rank1+ cha rank2 + cha rank3 (in 32-mb increments) note: channel a drb3 and channel b drb3 must be e qual for this mode, but the other drbs may be different. in all modes, if a dimm is single sided, it appears as a populated rank and an empty rank. a drb must be programmed appropriately for each. each rank is represented by a byte. each byte has the following format. bit access & default description 7:0 r/w 00h channel a dram rank boundary address: this 8 bit value defines the upper and lower addresses for each dram rank . bits 6:2 are compared against address 31:27 to determine the upper address limit of a particular rank. bits 1:0 must be 0s. bit 7 may be programmed to a 1 in the highest drb (drb3) if 4 gbs of memory is present. mchbar registers r 98 datasheet 5.1.2 c0drb1?channel a dram rank boundary address 1 mmio range: mchbar address offset: 101h default value: 00h access: r/w size: 8 bits the operation of this register is detailed in the description for register c0drb0. 5.1.3 c0drb2?channel a dram rank boundary address 2 mmio range: mchbar address offset: 102h default value: 00h access: r/w size: 8 bits the operation of this register is detailed in the description for register c0drb0. 5.1.4 c0drb3?channel a dram rank boundary address 3 mmio range: mchbar address offset: 103h default value: 00h access: r/w size: 8 bits the operation of this register is detailed in the description for register c0drb0. mchbar registers r datasheet 99 5.1.5 c0dra0?channel a dram rank 0,1 attribute mmio range: mchbar address offset: 108h default value: 00h access: r/w size: 8 bits the dram rank attribute registers define the page sizes to be used when accessing different ranks. these registers should be left with thei r default value (all zeros) for any rank that is unpopulated, as determined by the corresponding cxdrb registers. each byte of information in the cxdra registers describes the page size of a pair of ranks. channel and rank map: channel a rank 0, 1: 108h channel a rank 2, 3: 109h channel b rank 0, 1: 188h channel b rank 2, 3: 189h bit access & default description 7 reserved 6:4 r/w 000b channel a dram odd rank attribute: this 3 bit field defines the page size of the corresponding rank. 000 = unpopulated 001 = reserved 010 = 4 kb 011 = 8 kb 100 = 16 kb others = reserved 3 reserved 2:0 r/w 000b channel a dram even rank attribute: this 3 bit field defines the page size of the corresponding rank. 000 = unpopulated 001 = reserved 010 = 4 kb 011 = 8 kb 100 = 16 kb others = reserved 5.1.6 c0dra2?channel a dram rank 2,3 attribute mmio range: mchbar address offset: 109h default value: 00h access: r/w size: 8 bits the operation of this register is detailed in the description for register c0dra0. mchbar registers r 100 datasheet 5.1.7 c0dclkdis?channel a dram clock disable mmio range: mchbar address offset: 10ch default value: 00h access: r/w size: 8 bits this register can be used to di sable the system memory clock si gnals to each dimm slot. this can significantly reduce emi and power concerns for clocks that go to unpopulated dimms. clocks should be enabled based on whether a slot is populated, and what kind of dimm is present. bit access & default description 7:6 reserved 5 r/w 0b dimm clock gate enable pair 5 0 = tri-state the corresponding clock pair. 1 = enable the corresponding clock pair. 4 r/w 0b dimm clock gate enable pair 4 0 = tri-state the corresponding clock pair. 1 = enable the corresponding clock pair. 3 r/w 0b dimm clock gate enable pair 3 0 = tri-state the corresponding clock pair. 1 = enable the corresponding clock pair. 2 r/w 0b dimm clock gate enable pair 2 0 = tri-state the corresponding clock pair. 1 = enable the corresponding clock pair. 1 r/w 0b dimm clock gate enable pair 1 0 = tri-state the corresponding clock pair. 1 = enable the corresponding clock pair. 0 r/w 0b dimm clock gate enable pair 0 0 = tri-state the corresponding clock pair. 1 = enable the corresponding clock pair. note: since there are multiple clock signals assigned to each rank of a dimm, it is important to clarify exactly which rank width field affects which clock signal: channel rank clocks affected 0 0 or 1 sclk_a[2:0]/ sclk_a[2:0]# 0 2 or 3 sclk_a[5:3]/ sclk_a[5:3]# 1 0 or 1 sclk_b[2:0]/ sclk_b[2:0]# 1 2 or 3 sclk_b[5:3]/ sclk_b[5:3]# mchbar registers r datasheet 101 5.1.8 c0bnkarc?channel a dram bank architecture mmio range: mchbar address offset: 10eh default value: 0000h access: r/w size: 16 bits this register is used to program the bank architecture for each rank. bit access & default description 15:8 reserved 7:6 r/w 00b rank 3 bank architecture 00 = 4 bank. 01 = 8 bank. 1x = reserved 5:4 r/w 00b rank 2 bank architecture 00 = 4 bank. 01 = 8 bank. 1x = reserved 3:2 r/w 00b rank 1 bank architecture 00 = 4 bank. 01 = 8 bank. 1x = reserved 1:0 r/w 00b rank 0 bank architecture 00 = 4 bank. 01 = 8 bank. 1x = reserved mchbar registers r 102 datasheet 5.1.9 c0drt1?channel a dram timing register mmio range: mchbar address offset: 114h default value: 900122hh access: r/w, ro size: 32 bits bit access & default description 31:24 reserved 23:20 r/w 9h activate to precharge delay (t ras ). this bit controls the number of dram clocks for t ras . minimum recommendations are bes ide their corre sponding encodings. 0h ? 3h = reserved 4h ? fh = four to fifteen clocks respectively. 19 ro 0b reserved for activate to precharge delay (t ras ) max: it is required that the panic refresh timer be set to a value less than the t ras maximum. based on this setting, a panic refresh occurs before t ras maximum expiration and closes all the banks. this bit controls the maximum number of clocks that a dram bank can remain open. after this time period, the dram controller will guarantee to pre-charge the bank. this time period may or may not be set to overlap with time period that requires a refresh to happen. the dram controller includes a separate t ras-max counter for every supported bank. with a maximum of four ranks, and four banks per rank, there are 16 counters per channel. 0 = 120 microseconds 1 = reserved note: this register will become read only with a value of 0 if the design does not implement these counters. t ras-max is not required because a panic refr esh will close all banks in a rank before t ras-max expires. 18:10 reserved 9:8 r/w 01b casb latency (tcl). this value is programmable on ddr2 dimms. the value programmed here must match the cas latency of every ddr2 dimm in the system. encoding ddr cl ddr2 cl 00 3 5 01 2.5 4 10 2 3 11 reserved reserved 7 reserved mchbar registers r datasheet 103 bit access & default description 6:4 r/w 010b dram ras to cas delay (t rcd ). this bit controls the number of clocks inserted between a row activate command and a read or write command to that row. 000 = 2 dram clocks 001 = 3 dram clocks 010 = 4 dram clocks 011 = 5 dram clocks 100 ? 111 = reserved 3 reserved 2:0 r/w 010b dram ras precharge (t rp ). this bit controls the number of clocks that are inserted between a row precharge command and an activate command to the same rank. 000 = 2 dram clocks 001 = 3 dram clocks 010 = 4 dram clocks 011 = 5 dram clocks 100 ? 111 = reserved mchbar registers r 104 datasheet 5.1.10 c0drc0?channel a dram controller mode 0 mmio range: mchbar address offset: 120h default value: 00000000h access: r/w size: 32 bits bit access & default description 31:30 reserved 29 r/w 0b initialization complete (ic): this bit is used for communication of software state between the memory controller and the bios. bios sets this bit to 1 after initialization of the dram memory array is complete. 28:11 reserved 10:8 r/w 000b refresh mode select (rms): this field determines whether refresh is enabled and, if so, at what rate refreshes will be executed. 000 = refresh disabled 001 = refresh enabled. refres h interval 15.6 sec 010 = refresh enabled. refres h interval 7.8 sec 011 = refresh enabled. refres h interval 3.9 sec 100 = refresh enabled. refres h interval 1.95 sec 111 = refresh enabled. refresh interv al 64 clocks (fast refresh mode) other = reserved 7 ro 0b reserved mchbar registers r datasheet 105 bit access & default description 6:4 r/w 000 b mode select (sms). these bits select the specia l operational mode of the dram interface. the special modes are intended for initialization at power up. 000 = post reset state ? when the (g)mch exits reset (power-up or otherwise), the mode select field is cleared to ?000?. during any reset sequence, while power is applied and reset is active, the (g)mch de-asserts all cke signals. afte r internal reset is de-asserted, cke signals remain de-asserted until this field is written to a value different than ?000?. on this event, all cke signals are asserted. during suspend, (g)mch internal signal triggers dram controller to flush pending commands and enter all ranks into self-refresh mode. as part of resume sequence, (g)mch will be reset ? which will clear this bit field to ?000? and maintain cke signals de-asse rted. after internal reset is de- asserted, cke signals remain de-asserted until this field is written to a value different than ?000?. on this event, all cke signals are asserted. during entry to other low power states (c3, s1), (g)mch internal signal triggers dram controller to flush pending commands and enter all ranks into self-refresh mode. during exit to normal mode, (g)mch signal triggers dram controller to exit self-refresh and resume normal operation without s/w involvement. 001 = nop command enable ? all processor cycles to dram result in a nop command on the dram interface. 010 = all banks pre-charge enable ? all pr ocessor cycles to dram result in an ?all banks precharge? command on the dram interface. 011 = mode register set enable ? all processor cycles to dram result in a ?mode register? set command on the dram interface. host address lines are mapped to dram address lines in order to specify the command sent. host address lines [12:3] are mapped to ma[9:0], and ha[13] is mapped to ma[11]. 101 = reserved 110 = cbr refresh enable ? in this mode a ll processor cycles to dram result in a cbr cycle on the dram interface 111 = normal operation 3:2 reserved 1:0 ro dram type (dt). this field is used to select between supported sdram types. this bit is controlled by the mtype strap signal. 00 = reserved 01 = dual data rate (ddr) sdram 10 = second revision dual data rate (ddr2) sdram 11 = reserved mchbar registers r 106 datasheet 5.1.11 c1drb0?channel b dram rank boundary address 0 mmio range: mchbar address offset: 180h default value: 00h access: r/w size: 8 bits the operation of this register is detailed in the description for register c0drb0. 5.1.12 c1drb1?channel b dram rank boundary address 1 mmio range: mchbar address offset: 181h default value: 00h access: r/w size: 8 bits the operation of this register is detailed in the description for register c0drb0. 5.1.13 c1drb2?channel b dram rank boundary address 2 mmio range: mchbar address offset: 182h default value: 00h access: r/w size: 8 bits the operation of this register is detailed in the description for register c0drb0. 5.1.14 c1drb3?channel b dram rank boundary address 3 mmio range: mchbar address offset: 183h default value: 00h access: r/w size: 8 bits the operation of this register is detailed in the description for register c0drb0. 5.1.15 c1dra0?channel b dram rank 0,1 attribute mmio range: mchbar address offset: 188h default value: 00h access: r/w size: 8 bits the operation of this register is detailed in the description for register c0dra0. mchbar registers r datasheet 107 5.1.16 c1dra2?channel b dram rank 2,3 attribute mmio range: mchbar address offset: 189h default value: 00h access: r/w size: 8 bits the operation of this register is detailed in the description for register c0dra0. 5.1.17 c1dclkdis?channel b dram clock disable mmio range: mchbar address offset: 18ch default value: 00h access: r/w size: 8 bits the operation of this register is detailed in the description for register c0dclkdis. 5.1.18 c1bnkarc?channel b bank architecture mmio range: mchbar address offset: 18eh default value: 0000h access: r/w size: 16 bits the operation of this register is detailed in the description for register c0bnkarc. 5.1.19 c1drt1?channel b dram timing register 1 mmio range: mchbar address offset: 194h default value: 900122h access: r/w size: 32 bits the operation of this register is detailed in the description for register c0drt1. 5.1.20 c1drc0?channel b dram controller mode 0 mmio range: mchbar address offset: 1a0h default value: 00000000h access: r/w size: 32 bits the operation of this register is detailed in the description for register c0drc0. mchbar registers r 108 datasheet 5.1.21 pmcfg?power management configuration mmio range: mchbar address offset: f10h default value: 00000000h access: r/w size: 32 bits bit access & default description 31:5 reserved 4 r/w 0b enhanced power management features enable 0 = legacy power management mode 1 = reserved. 3:0 reserved 5.1.22 pmsts?power management status mmio range: mchbar address offset: f14h default value: 00000000h access: r/w size: 32 bits this register is reset by pwrok only. bit access & default description 31:2 reserved 1 r/wc/s 0b channel b in self-refresh. this bit is set by power management hardware after channel b is placed in self refresh as a result of a power state or a reset warn sequence. it is cleared by power managem ent hardware before starting channel b self refresh exit sequence initiated by a power management exit. it is cleared by bios in a warm reset (reset# asserted while pwrok is asserted) exit sequence. 0 = channel b not guaranteed to be in self-refresh. 1 = channel b in self-refresh. 0 r/wc/s 0b channel a in self-refresh. set by power management hardware after channel a is placed in self refresh as a result of a power state or a reset warn sequence. it is cleared by power managem ent hardware before starting channel a self refresh exit sequence initiated by a power management exit. it is cleared by the bios in a warm reset (reset# asserted while pwok is asserted) exit sequence. 0 = channel a not guaranteed to be in self-refresh. 1 = channel a in self-refresh. epbar registers?egress port register summary r datasheet 109 6 epbar registers?egress port register summary these registers are offset from the epbar base address. table 6-1. egress port register address map address offset register symbol register name default value access 044h?047h epesd ep element self description 0000h r/wo, ro 050h?053h eple1d ep link entry 1 description 0100h r/wo, ro 058h? 05fh eple1a ep link entry 1 address 000000000 0000000h r/wo, ro 060h?063h eple2d ep link entry 2 description 02000002h r/wo, ro 068h? 06fh eple2a ep link entry 2 address 000000000 0008000h ro 6.1 ep rcrb configuration register details figure 6-1. link declaration topology peg (port #2) egress_linkdeclar_topo egress port (port #0) dmi (port #1) link #2 (type 1) link #1 (type 0) link #2 (type 0) link #1 (type 0) egress port (port #0) x4 x16 (g)mch main memory subsystem intel ? ich6 link #1 (type 0) epbar registers?egress port register summary r 110 datasheet 6.1.1 epesd?ep element self description mmio range: epbar address offset: 044h default value: 00000201h access: r/wo, ro size: 32 bits this register provides information about the root complex element containing this link declaration capability. bit access & default description 31:24 ro 00h port number: this field specifies the port number associated with this element with respect to the component that contains th is element. a value of 00h indicates to configuration software that this is the default egress port. 23:16 r/wo 00h component id: this field identifies the physical co mponent that contains this root complex element. component ids start at 1. this value is a mirror of the value in the component id field of all elements in this component. the value only needs to be writt en in one of the mirrored fields and it will be reflected everywhere that it is mirrored. 15:8 ro 02h number of link entries: this field indicates the number of link entries following the element self description. this field reports 2 (one each for pci express* x16 interface and dmi). 7:4 reserved 3:0 ro 1h element type: this field indicates the type of the root complex element. 1h = port to system memory epbar registers?egress port register summary r datasheet 111 6.1.2 eple1d?ep link entry 1 description mmio range: epbar address offset: 050h default value: 0100h access: r/wo, ro size: 32 bits this register provides the first part of a link entry that declares an internal link to another root complex element. bit access & default description 31:24 ro 01h target port number: this field specifies the port number associated with the element targeted by this link entry (dmi). the target port number is with respect to the component that contains this element as specified by the target component id. 23:16 r/wo 00h target component id: this field identifies the physical or logical component that is targeted by this link entry. a value of 0 is reserved; component ids start at 1. this value is a mirror of the value in the component id field of all elements in this component. the value only needs to be writt en in one of the mirrored fields and it will be reflected everywhere that it is mirrored. 15:2 reserved 1 ro 0b link type: this bit indicates that the link points to memory-mapped space (for rcrb). the link address specifies the 64- bit base address of the target rcrb. 0 r/wo 0b link valid 0 = link entry is not valid and will be ignored. 1 = link entry specifies a valid link. 6.1.3 eple1a?ep link entry 1 address mmio range: epbar address offset: 058h default value: 0000000000000000h access: r/wo size: 64 bits this register provides the second part of a link entry, which declares an internal link to another root complex element. bit access & default description 63:32 reserved 31:12 r/wo 0 0000h link address: this field provides the me mory-mapped base address of the rcrb that is the target element (dmi) for this link entry. 11:0 reserved epbar registers?egress port register summary r 112 datasheet 6.1.4 eple2d?ep link entry 2 description mmio range: epbar address offset: 060h default value: 02000002h access: r/wo, ro size: 32 bits this register provides the first part of a link entry that declares an internal link to another root complex element. bit access & default description 31:24 ro 02h target port number: this field specifies the port number associated with the element targeted by this link entry (pci express* x16 interface). the target port number is with respect to the component t hat contains this el ement as specified by the target component id. 23:16 r/wo 00h target component id: this field identifies the physical or logical component that is targeted by this link entry. a value of 0 is reserved; component ids start at 1. this value is a mirror of the value in the component id field of all elements in this component. the value only needs to be writt en in one of the mirrored fields and it will be reflected everywhere that it is mirrored. 15:2 reserved 1 ro 1b link type: 1 = link points to configuration space of the integrated device that controls the x16 root port. the link address specifie s the configuration address (segment, bus, device, function) of the target root port. 0 r/wo 0b link valid 0 = link entry is not valid and will be ignored. 1 = link entry specifies a valid link. epbar registers?egress port register summary r datasheet 113 6.1.5 eple2a?ep link entry 2 address mmio range: epbar address offset: 068h default value: 0000000000008000h access: ro size: 64 bits this register provides the second part of a link entry that declares an internal link to another root complex element. bit access & default description 63:28 reserved 27:20 ro 00h bus number 19:15 ro 0 0001b device number: target for this link is pci express* x16 port (device 1). 14:12 ro 000b function number 11:0 reserved epbar registers?egress port register summary r 114 datasheet dmibar registers?direct media interface (dmi) rcrb r datasheet 115 7 dmibar registers?direct media interface (dmi) rcrb this root complex register bl ock (rcrb) controls the (g)mch-in tel ich6 serial interconnect. the base address of this space is programmed in dmibar in device 0 c onfiguration space. these registers are offset from the dmibar base address table 7-1. dmi register address map summary address offset register symbol register name pci dev # 000?003h dmivcech dmi virtual channel enhanced capability header dmibar 004?007h dmipvccap1 dmi port vc capability register 1 dmibar 008?00bh dmipvccap2 dmi port vc capability register 2 dmibar 00c?00dh dmipvcctl dmi port vc control dmibar 00e?00fh ? reserved dmibar 010?013h dmivc0rcap dmi vc0 resource capability dmibar 014?017h dmivc0rctl dmi vc0 resource control dmibar 018?019h ? reserved dmibar 01a?01bh dmivc0rsts dmi vc0 resource status dmibar 01c?01fh dmivc1rcap dmi vc1 resource capability dmibar 020?023h dmivc1rctl dmi vc1 resource control dmibar 024?025h ? reserved dmibar 026?027h dmivc1rsts dmi vc1 resource status dmibar 028?083h ? reserved dmibar 084?087h dmilcap dmi link capabilities dmibar 088?089h dmilctl dmi link control dmibar 08a?08bh dmilsts dmi link status dmibar 08c?fffh ? reserved dmibar dmibar registers?direct media interface (dmi) rcrb r 116 datasheet 7.1 direct media interface (dmi) rcrb register details 7.1.1 dmivcech?dmi virtual channel enhanced capability header mmio range: dmibar address offset: 000h default value: 04010002h access: ro size: 32 bits this register indicates dmi virtual channel capabilities. bit access & default description 31:20 ro 040h pointer to next capability: this field indicates the next item in the list. 19:16 ro 1h capability version: this field indicates suppor t as a version 1 capability structure. 15:0 ro 0002h capability id: this field indicates this is the virtual channel capability item. 7.1.2 dmipvccap1?dmi port vc capability register 1 mmio range: dmibar address offset: 004h default value: 00000001h access: r/wo, ro size: 32 bits this register describes the configuration of virtual channels associated with this port. bit access & default description 31:12 reserved 11:10 ro 00b port arbitration table entry size (pats): this field indicates the size of the port arbitration table is 4 bi ts (to allow up to 8 ports). 9:8 ro 00b reference clock (rc) fixed at 10 ns. 7 reserved 6:4 ro 000b low priority extended vc count (lpevc): this field indicates that there are no additional vcs of low priority with extended capabilities. 3 reserved 2:0 r/wo 001b extended vc count: this field indicates that t here is one additional vc (vc1) that exists with extended capabilities. dmibar registers?direct media interface (dmi) rcrb r datasheet 117 7.1.3 dmipvccap2?dmi port vc capability register 2 mmio range: dmibar address offset: 008h default value: 00000001h access: ro size: 32 bits this register describes the configuration of virtual channels associated with this port. bit access & default description 31:24 ro 00h vc arbitration table offset (ato): this field indicates that no table is present for vc arbitration since it is fixed. 23:8 reserved 7:0 ro 01h vc arbitration capability: this field indicates that the vc arbitration is fixed in the root complex. vc1 is highest priority and vc0 is lowest priority. 7.1.4 dmipvcctl?dmi port vc control mmio range: dmibar address offset: 00ch default value: 00000000h access: r/w, ro size: 16 bits bit access & default description 15:4 reserved 3:1 r/w 000b vc arbitration select: this field indicates which vc should be programmed in the vc arbitration table. the root complex takes no action on the setting of this field since there is no arbitration table. 0 ro 0b load vc arbitration table (lat): this field indicates that the table programmed should be loaded into the vc arbitration table. this bit is defined as read/write with always returning 0 on reads. dmibar registers?direct media interface (dmi) rcrb r 118 datasheet 7.1.5 dmivc0rcap?dmi vc0 resource capability mmio range: dmibar address offset: 010h default value: 00000001h access: ro size: 32 bits bit access & default description 31:24 ro 00h port arbitration table offset (at): this vc implements no port arbitration table since the arbitration is fixed. 23 reserved 22:16 ro 00h maximum time slots (mts): this vc implements fixed arbitration, and therefore this field is not used. 15 ro 0b reject snoop transactions (rts): this vc must be able to take snoopable transactions. 14 ro 0b advanced packet switching (aps): this vc is capable of all transactions, not just advanced packet switching transactions. 13:8 reserved 7:0 ro 01h port arbitration capability (pac): this field indicates that this vc uses fixed port arbitration. dmibar registers?direct media interface (dmi) rcrb r datasheet 119 7.1.6 dmivc0rctl0?dmi vc0 resource control mmio range: dmibar address offset: 014h default value: 8000007fh access: r/w, ro size: 32 bits this register controls the resources associated with pci express virtual channel 0. bit access & default description 31 ro 1b virtual channel enable (en): enables the vc when set. disables the vc when cleared. 30:27 reserved 26:24 ro 000b virtual channel identifier (id): indicates the id to use for this virtual channel. 23:20 reserved 19:17 r/w 0h port arbitration select (pas): indicates which port table is being programmed. the root complex takes no action on this setting since the arbitration is fixed and there is no arbitration table. 16 ro 0b load port arbitration table (lat): the root complex does not implement an arbitration table for this virtual channel. 15:8 reserved 7:1 r/w 7fh transaction class / virtual channel map (tvm): this field indicates which transaction classes are mapped to this vi rtual channel. when a bit is set, this transaction class is mapped to the virtual channel. 0 reserved dmibar registers?direct media interface (dmi) rcrb r 120 datasheet 7.1.7 dmivc0rsts?dmi vc0 resource status mmio range: dmibar address offset: 01ah default value: 00000002h access: ro size: 16 bits this register reports the vi rtual channel specific status. bit access & default description 15:2 reserved 1 ro 1b vc negotiation pending (np): 0 = virtual channel is not being negotiated with ingress ports. 1 = virtual channel is still being negotiated with ingress ports. 0 ro 0b port arbitration tables status (ats): there is no port arbitration table for this vc, so this bit is reserved at 0. 7.1.8 dmivc1rcap?dmi vc1 resource capability mmio range: dmibar address offset: 01ch default value: 00008001h access: ro size: 32 bits bit access & default description 31:24 ro 00h port arbitration table offset (at): this field indicates the location of the port arbitration table in the root complex. a va lue of 3h indicates the table is at offset 30h. 23 reserved 22:16 ro 00h maximum time slots (mts): this value is updated by platform bios based upon the determination of the number of time slots available in the platform. 15 ro 1b reject snoop transactions (rts): all snoopable transactions on vc1 are rejected. this vc is fo r isochronous transfers only. 14 ro 0b advanced packet switching (aps): this vc is capable of all transactions, not just advanced packet switching transactions. 13:8 reserved 7:0 ro 01h port arbitration capability (pac): this field indicates the port arbitration capability is time-based wrr of 128 phases. dmibar registers?direct media interface (dmi) rcrb r datasheet 121 7.1.9 dmivc1rctl1?dmi vc1 resource control mmio range: dmibar address offset: 020h default value: 00100000h access: r/w, ro size: 32 bits this register controls the resources associated with virtual channel 1. bit access & default description 31 r/w 0b virtual channel enable (en): 0 = disable. 1 = enable. 30:27 ro 0h reserved 26:24 r/w 001b virtual channel identifier (id): this field indicates the id to use for this virtual channel. 23:20 reserved 19:17 r/w 0h port arbitration select (pas): this field indicates wh ich port table is being programmed. the only permissible value of this field is 4h for the time-based wrr entries. 16:8 reserved 7:1 r/w 00h transaction class / virtual channel map (tvm): this field indicates which transaction classes are mapped to this vi rtual channel. when a bit is set, this transaction class is mapped to the virtual channel. 0 reserved 7.1.10 dmivc1rsts?dmi vc1 resource status mmio range: dmibar address offset: 026h default value: 0000h access: ro size: 16 bits this register reports the vi rtual channel specific status. bit access & default description 15:2 reserved 1 ro 0b vc negotiation pending (np): 0 = virtual channel is not being negotiated with ingress ports. 1 = virtual channel is still being negotiated with ingress ports. 0 reserved dmibar registers?direct media interface (dmi) rcrb r 122 datasheet 7.1.11 dmilcap?dmi link capabilities mmio range: dmibar address offset: 084h default value: 00012c41h access: r/wo, ro size: 32 bits this register indicates dmi specific capabilities. bit access & default description 31:18 reserved 17:15 r/wo 010b l1 exit latency (el1). l1 not supported on dmi. 14:12 r/wo 010b l0s exit latency (el0): this field indicates that exit latency is 128 ns to less than 256 ns. 11:10 ro 11b active state link pm support (apms): this field indicates that l0s is supported on dmi. 9:4 ro 4h maximum link width (mlw): this field indicates the maximum link width is 4 ports. 3:0 ro 1h maximum link speed (mls): this field indicates the link speed is 2.5 gb/s. 7.1.12 dmilctl?dmi link control mmio range: dmibar address offset: 088h default value: 0000h access: r/w size: 16 bits this register allows control of dmi. bit access & default description 15:8 reserved 7 r/w 0h extended synch (es): 1 = forces extended transmission of fts or dered sets when exiting l0s prior to entering l0 and extra ts1 sequences at exit from l1 prior to entering l0. 6:2 reserved 1:0 r/w 00b active state link pm control (apmc): indicates whether dmi should enter l0s. 00 = disabled 01 = l0s entry enabled 10 = reserved 11 = reserved dmibar registers?direct media interface (dmi) rcrb r datasheet 123 7.1.13 dmilsts?dmi link status mmio range: dmibar address offset: 08ah default value: 0001h access: ro size: 16 bits this register indi cates dmi status. bit access & default description 15:10 reserved 9:4 ro 00h negotiated link width (nlw): this field is valid only when the link is in the l0, l0s, or l1 states (after link width negotiation is successfully completed). negotiated link width is x4 (000100b). all other encodings are reserved. 3:0 ro 1h link speed (ls) link is 2.5 gb/s. dmibar registers?direct media interface (dmi) rcrb r 124 datasheet host-pci express* bridge registers (d1:f0) (intel? 82915g/82915p/82915pl only) r datasheet 125 8 host-pci express* bridge registers (d1:f0) (intel ? 82915g/82915p/82915pl only) device 1contains the controls associated with the pci express x16 root port that is the intended to attach as the point for external graphics. it is typically referred to as pci express* x16 graphics interface port. in addition, it also functi ons as the virtual pci-to-pci bridge. warning: when reading the pci express "conceptual" register s such as this, you may not get a valid value unless the register value is stable. the pci express* specification defines two types of reserved bits: reserved and preserved: ? reserved for future r/w implementations; softwa re must preserve value read for writes to bits. ? reserved and zero: reserved for future r/wc /s implementations; software must use 0 for writes to bits. unless explicitly documented as reserved and zero, all bits marked as reserved are part of the reserved and preserved type that have historically been the typical definition for reserved. it is important to note that most (if not all) control bits in this device cannot be modified unless the link is down. software is required to first disable the link, then program the registers, and then re-enable the link (which will cause a full-retrain with the new settings). table 8-1. host-pci express* graphics bridge register address map (d1:f0) address offset register symbol register name default value access 00?01h vid1 vendor identification 8086h ro 02?03h did1 device identification 2581h ro 04?05h pcicmd1 pci command 0000h ro, r/w 06?07h pcists1 pci status 0000h ro, r/w 08h rid1 revision identification see register description ro 09?0bh cc1 class code 060400h ro 0ch cl1 cache line size 00h r/w 0dh ? reserved ? ? 0eh hdr1 header type 01h ro host-pci express* bridge registers (d1:f0) (intel? 82915g/82915p/82915pl only) r 126 datasheet address offset register symbol register name default value access 0f?17h ? reserved ? ? 18h pbusn1 primary bus number 00h ro 19h sbusn1 secondary bus number 00h ro 1ah subusn1 subordinate bus number 00h r/w 1bh ? reserved ? ? 1ch iobase1 i/o base address f0h ro 1dh iolimit1 i/o limit address 00h r/w 1eh?1fh ssts1 secondary status 00h ro, r/w/c 20?21h mbase1 memory base address fff0h r/w 22?23h mlimit1 memory limit address 0000h r/w 24?25h pmbase1 prefetchable memory base address fff0h ro, r/w 26?27h pmlimit1 prefetchable memory limit address 0000h ro, r/w 28?33h ? reserved ? ? 34h capptr1 capabilities pointer 88h ro 35?3bh ? reserved ? ? 3ch intrline1 interrupt line 00h r/w 3dh intrpin1 interrupt pin 00h ro 3e?3fh bctrl1 bridge control 0000h ro, r/w 40?7fh ? reserved ? ? 80?83h pm_capid1 power management capabilities 19029001h or 1902a001h ro 84?87h pm_cs1 power management control/status 00000000h ro, r/w/s 88?8bh ss_capid subsystem id and vendor id capabilities 0000800d h ro 8c?8fh ss subsystem id and subsystem vendor id 00008086h ro 90?91h msi_capid message signaled interrupts capability id a005h ro 92?93h mc message control 0000h ro, r/w 94?97h ma message address 00000000h ro, r/w 98?99h md message data 0000h r/w 9a?9fh ? reserved ? ? a0?a1h peg_capl pci express* capability list 0010h ro a2?a3h peg_cap pci express capabilities 0141h ro a4?a7h dcap device capabilities 00000000h ro a8?a9h dctl device control 0000h r/w aa?abh dsts device status 0000h ro ac?afh lcap link capabilities 02012e01h r/wo b0?b1h lctl link control 0000h ro, r/w host-pci express* bridge registers (d1:f0) (intel? 82915g/82915p/82915pl only) r datasheet 127 address offset register symbol register name default value access b2?b3h lsts link status 1001h ro b4?b7h slotcap slot capabilities 00000000h r/wo b8?b9h slotctl slot control 01c0h r/w ba?bbh slotsts slot status 0x00h ro, r/w/c bc?bdh rctl root control 0000h r/w be?bfh ? reserved ? ? c0?c3h rsts root status 00000000h ro, r/w/c c4?ebh ? reserved ? ? ec?efh peglc pci express*-gr aphics legacy control 00000000h r/w, ro f0?ffh ? reserved ? ? 100?103h vcech virtual channel enhanced capability header 14010002h ro 104?107h pvccap1 port vc capability register 1 00000001h ro, r/wo 108?10bh pvccap2 port vc capability register 2 00000001h ro 10c?10dh pvcctl port vc control 0000h r/w 10e?10fh ? reserved ? ? 110?113h vc0rcap vc0 resource capability 00000000h ro 114?117h vc0rctl vc0 resource control 8000007fh ro, r/w 118?119h ? reserved ? ? 11a?11bh vc0rsts vc0 resource status 0000h ro 11c?11fh vc1rcap vc1 resource capability 00008000h ro 120?123h vc1rctl vc1 resource control 01000000h ro, r/w 124?125h ? reserved ? ? 126?127h vc1rsts vc1 resource status 0000h ro 128?13fh ? reserved ? ? 140?143h rcldech root complex link declaration enhanced capability header 00010005h ro 144?147h esd element self description 02000100h ro, r/wo 148?14fh ? reserved ? ? 150?153h le1d link entry 1 description 00000000h ro, r/wo 154?157h ? reserved ? ? 158?15fh le1a link entry 1 address 000000000 0000000h r/wo 160?217h ? reserved ? ? 218?21fh pegssts pci express*-g raphics sequence status 000000000 0000fffh ro 220?fffh ? reserved ? ? host-pci express* bridge registers (d1:f0) (intel? 82915g/82915p/82915pl only) r 128 datasheet 8.1 host-pci express* bridge pci register details (d1:f0) 8.1.1 vid1?vendor identification (d1:f0) pci device: 1 address offset: 00h default value: 8086h access: ro size: 16 bits this register combined with the device identification register uniquely identifies any pci device. bit access & default description 15:0 ro 8086h vendor identification (vid1): pci standard identification for intel. 8.1.2 did1?device identification (d1:f0) pci device: 1 address offset: 02h default value: 2581h access: ro size: 16 bits this register combined with the vendor identification register uniquely identifies any pci device. bit access & default description 15:0 ro 2581h device identification number (did1): this field is an identifier assigned to the (g)mch device 1 (virtual pci-to-pci bridge, pci express* graphics port). host-pci express* bridge registers (d1:f0) (intel? 82915g/82915p/82915pl only) r datasheet 129 8.1.3 pcicmd1?pci command (d1:f0) pci device: 1 address offset: 04h default value: 0000h access: ro, r/w size: 16 bits bit access & default description 15:11 reserved 10 r/w 0b inta assertion disable: 0 = this device is permitted to generate inta interrupt messages. 1 = this device is prevented fr om generating interrupt messages. any inta emulation interrupts already asserted must be de-asserted when this bit is set. only affects interrupts generated by the device (pci inta from a pme or hot plug event) controlled by this command register. it does not affect upstream msis, upstream pci inta-intd asserts and de-assert messages. 9 ro 0b fast back-to-back enable (fb2b): not applicable or implemented. hardwired to 0. 8 r/w 0b serr message enable (serre1): this bit is an enable bit for device 1 serr messaging. the (g)mch communicates the serr# condition by sending a serr message to the intel ? ich6. this bit, when set, enables reporting of non- fatal and fatal errors to the root complex. note that errors are reported if enabled either through this bit or through t he pci express* specific bits in the device control register 0 = the serr message is generated by the (g)mch for device 1 only under conditions enabled individually through the device control register. 1 = the (g)mch is enabled to generate serr messages which will be sent to the ich6 for specific device 1 error conditions that are individually enabled in the bctrl1 register and for all non-fatal and fatal errors generated on the primary side of the virtual pci to pci express bridge (not those received by the secondary side). the error status is reported in the pcists1 register. 7 reserved 6 r/wo 0b parity error enable (perre): this bit controls whether or not the master data parity error bit in the pci status register can bet set. 0 = master data parity error bit in pci status register cannot be set. 1 = master data parity error bit in pci status register can be set. 5 ro 0b vga palette snoop: hardwired to 0. 4 ro 0b memory write and invalidate enable (mwie): hardwired to 0. 3 ro 0b special cycle enable (sce): hardwired to 0. host-pci express* bridge registers (d1:f0) (intel? 82915g/82915p/82915pl only) r 130 datasheet bit access & default description 2 r/w 0b bus master enable (bme): this bit does not affect forwarding of completions from the primary interface to the secondary interface. 0 = this device is prevented from making memory or i/o requests to its primary bus. note that according to the pci s pecification, as msi interrupt messages are in-band memory writes, disabling t he bus master enable bit prevents this device from generating msi interrupt messages or passing them from its secondary bus to its primary bus. up stream memory writes/reads, i/o writes/reads, peer writes/reads, and msis will all be treated as illegal cycles. writes are forwarded to memory address 0h with byte enables de-asserted. reads will be forwarded to memory address 0h and will return unsupported request status (or master abort) in its completion packet. 1 = this device is allowed to issue reques ts to its primary bus. completions for previously issued memory read reques ts on the primary bus will be issued when the data is available. 1 r/w 0b memory access enable (mae) 0 = all of device 1?s memo ry space is disabled. 1 = enable the memory and pre-fetchable memory address ranges defined in the mbase1, mlimit1, pmbase1, and pmlimit1 registers. 0 r/w 0b io access enable (ioae) 0 = all of device 1?s i/o space is disabled. 1 = enable the i/o address range defined in the iobase1 and iolimit1 registers. 8.1.4 pcists1?pci status (d1:f0) pci device: 1 address offset: 06h default value: 0000h access: ro, r/w/c size: 16 bits this register reports the occurrence of error c onditions associated with primary side of the ?virtual? host-pci express bridge in the (g)mch. bit access & default description 15 ro 0b detected parity error (dpe): hardwired to 0. parity (generating poisoned tlps) is not supported on the primary side of this device. 14 r/wc 0b signaled system error (sse): 1 = this bit is set when this de vice sends an serr due to detecting an err_fatal or err_nonfatal condi tion and the serr enable bit in the command register is ?1?. both received (if enabled by bctrl1[1]) and internally detected error messages do not affect this field. 13 ro 0b received master abort status (rmas): not applicable or implemented. hardwired to 0. the concept of a mast er abort does not exist on primary side of this device. host-pci express* bridge registers (d1:f0) (intel? 82915g/82915p/82915pl only) r datasheet 131 bit access & default description 12 ro 0b received target abort status (rtas): hardwired to 0. the concept of a target abort does not exist on primary side of this device. 11 ro 0b signaled target abort status (stas): hardwired to 0. the concept of a target abort does not exist on primary side of this device. 10:9 ro 00b devselb timing (devt): this device is not the subtractive decoded device on bus 0. this bit field is therefore hardwir ed to 00b to indicate that the device uses the fastest possible decode. 8 ro 0b master data parity error (pmdpe): because the primary side of the pci express* x16 graphics interface?s virtual pc i-to-pci bridge is integrated with the (g)mch functionality, there is no scenario where this bit will get set. because hardware will never set this bit, it is impossible for software to have an opportunity to clear this bit or otherwise test that it is implemented. the pci specification defines it as a r/wc; how ever, for this implementation, an ro definition behaves the same way and will meet all microsoft testing requirements. this bit can only be set when the parity error enable bit in the pci command register is set. 7 ro 0b fast back-to-back (fb2b): hardwired to 0. 6 reserved 5 ro 0b 66/60mhz capability (cap66): hardwired to 0. 4 ro 1b capabilities list: this bit indicates that a capabilities list is present. hardwired to 1. 3 ro 0b inta status: this field indicates that an interrupt message is pending internally to the device. only pme and hot plug sources feed into this status bit (not pci inta-intd assert and de-assert messages ). the inta assertion disable bit, pcicmd1[10], has no effect on this bit. 2:0 reserved host-pci express* bridge registers (d1:f0) (intel? 82915g/82915p/82915pl only) r 132 datasheet 8.1.5 rid1?revision identification (d1:f0) pci device: 1 address offset: 08h default value: see bit description access: ro size: 8 bits this register contains the revision number of the (g)mch device 1. bit access & default description 7:0 ro 00h revision identification number (rid1): this field indicates the number of times that this device in this component has been ?stepped? through the manufacturing process. refer to the intel ? 82915g/82915p/82915pl/82915gv/82915GL/82910gl express chipset specification update for the value of the revision id register. 8.1.6 cc1?class code (d1:f0) pci device: 1 address offset: 09h default value: 060400h access: ro size: 24 bits this register identifies the basic function of the device, a more specific s ub-class, and a register- specific programming interface. bit access & default description 23:16 ro 06h base class code (bcc): this field indicates the base class code for this device. 06h = bridge device. 15:8 ro 04h sub-class code (subcc): this field indicates the sub-class code for this device. 04h = pci-to-pci bridge. 7:0 ro 00h programming interface (pi): this field indicates the programming interface of this device. this value does not specif y a particular register set layout and provides no practical use for this device. host-pci express* bridge registers (d1:f0) (intel? 82915g/82915p/82915pl only) r datasheet 133 8.1.7 cl1?cache line size (d1:f0) pci device: 1 address offset: 0ch default value: 00h access: r/w size: 8 bits bit access & default description 7:0 r/w 00h cache line size (scratch pad): this field is implemented by pci express* devices as a read/write field for legac y compatibility purposes but has no impact on any pci express device functionality. 8.1.8 hdr1?header type (d1:f0) pci device: 1 address offset: 0eh default value: 01h access: ro size: 8 bits this register identifies th e header layout of the configuration space. no physical register exists at this location. bit access & default description 7:0 ro 01h header type register (hdr): this field returns 01h to indicate that this is a single function device with bridge header layout. 8.1.9 pbusn1?primary bus number (d1:f0) pci device: 1 address offset: 18h default value: 00h access: ro size: 8 bits this register identifies that this ?virtual? host-pci express bridge is connected to pci bus 0. bit access & default description 7:0 ro 00h primary bus number (busn): configuration software typically programs this field with the number of the bus on the pr imary side of the bridge. since device 1 is an internal device and its primary bus is always 0, these bits are read only and are hardwired to 0. host-pci express* bridge registers (d1:f0) (intel? 82915g/82915p/82915pl only) r 134 datasheet 8.1.10 sbusn1?secondary bus number (d1:f0) pci device: 1 address offset: 19h default value: 00h access: ro size: 8 bits this register identifies the bus number assigned to the second bus side of the ?virtual? bridge i.e. to pci express graphics. this number is programme d by the pci configuration software to allow mapping of configuration cycles to pci express graphics. bit access & default description 7:0 r/w 00h secondary bus number (busn): this field is progra mmed by configuration software with the bus number assigned to pci express*-g. 8.1.11 subusn1?subordinate bus number (d1:f0) pci device: 1 address offset: 1ah default value: 00h access: r/w size: 8 bits this register identifies the subordinate bus (if any) that resides at the level below pci express graphics. this number is programmed by the pc i configuration software to allow mapping of configuration cycles to pci express graphics. bit access & default description 7:0 r/w 00h subordinate bus number (busn): this register is programmed by configuration software with the number of the highest subordinate bus that lies behind the device 1 bridge. when only a single pci device resides on the pci express*-g segment, this register will contain the same value as the sbusn1 register. host-pci express* bridge registers (d1:f0) (intel? 82915g/82915p/82915pl only) r datasheet 135 8.1.12 iobase1?i/o base address (d1:f0) pci device: 1 address offset: 1ch default value: f0h access: ro size: 8 bits this register controls the pr ocessor-to-pci express graphics i/o access routing based on the following formula: io_base address io_limit only the upper 4 bits are programmable. for the purpose of address decode, address bits a[11:0] are treated as 0. thus, the bottom of the defined i/o address range will be aligned to a 4-kb boundary. bit access & default description 7:4 r/w fh i/o address base (iobase): this field corresponds to a[15:12] of the i/o addresses passed by bridge 1 to pci express* -g. bios must not set this register to 00h; otherwise, 0cf8h/0cfch accesse s will be forwarded to the pci express hierarchy associated with this device. 3:0 reserved 8.1.13 iolimit1?i/o limit address (d1:f0) pci device: 1 address offset: 1dh default value: 00h access: r/w size: 8 bits this register controls the pr ocessor-to-pci express graphics i/o access routing based on the following formula: io_base address io_limit only the upper 4 bits are programmable. for the pur poses of address decode, address bits a[11:0] are assumed to be fffh. thus, the top of the defi ned i/o address range will be at the top of a 4- kb aligned address block. bit access & default description 7:4 r/w 0h i/o address limit (iolimit): this field corresponds to a[15:12] of the i/o address limit of device 1. devices between this upper limit and iobase1 will be passed to the pci express* hierar chy associated with this device. 3:0 reserved host-pci express* bridge registers (d1:f0) (intel? 82915g/82915p/82915pl only) r 136 datasheet 8.1.14 ssts1?secondary status (d1:f0) pci device: 1 address offset: 1eh default value: 00h access: ro, r/w/c size: 16 bits ssts1 is a 16-bit status register that reports th e occurrence of error cond itions associated with secondary side (i.e., pci express graphics side) of the ?virtual? pci-pci bridge in the (g)mch. bit access & default description 15 r/wc 0b detected parity error (dpe): 1 = the mch received across the link (upstream) a posted write data poisoned tlp (ep=1). 14 r/wc 0b received system error (rse): 1 = secondary side sends an err_fata l or err_nonfatal message due to an error detected by the secondary side, and the serr enable bit in the bridge control register is 1. 13 r/wc 0b received master abort (rma): 1 = secondary side for type 1 configurati on space header device (for requests initiated by the type 1 header device itself) receives a completion with unsupported request completion status. 12 r/wc 0b received target abort (rta): 1 = secondary side for type 1 configurati on space header device (for requests initiated by the type 1 header device itself) receives a completion with completer abort completion status. 11 ro 0b signaled target abort (sta): hardwired to 0. the (g)mch does not generate target aborts (the (g)mch will never complete a request using the completer abort completion status). 10:9 ro 00b devselb timing (devt): hardwired to 0. 8 r/wc 0b master data parity error (smdpe). 1 = the mch received across the link (upstream) a read data completion poisoned tlp (ep=1). note: this bit can only be set when the parity error enable bit in the bridge control register is set. 7 ro 0b fast back-to-back (fb2b): hardwired to 0. 6 reserved 5 ro 0b 66/60 mhz capability (cap66): hardwired to 0. 4:0 reserved host-pci express* bridge registers (d1:f0) (intel? 82915g/82915p/82915pl only) r datasheet 137 8.1.15 mbase1?memory base address (d1:f0) pci device: 1 address offset: 20h default value: fff0h access: r/w size: 16 bits this register controls the processor to pci express graphics non-prefetchable memory access routing based on the following formula: memory_base address memory_limit the upper 12 bits of the register are read/write and correspond to the upper 12 address bits a[31:20] of the 32-bit address. the bottom 4 bits of this register are read-only and return zeroes when read. the configuration software must initialize this register. for the purpose of address decode, address bits a[19:0] are assumed to be 0. thus, the bottom of the defined memory address range will be a ligned to a 1-mb boundary. bit access & default description 15:4 r/w fffh memory address base (mbase): this field corresponds to a[31:20] of the lower limit of the memory range that will be passed to pci express*. 3:0 reserved host-pci express* bridge registers (d1:f0) (intel? 82915g/82915p/82915pl only) r 138 datasheet 8.1.16 mlimit1?memory limit address (d1:f0) pci device: 1 address offset: 22h default value: 0000h access: r/w size: 16 bits this register controls the pr ocessor-to-pci express graphics non-prefetchable memory access routing based on the following formula: memory_base address memory_limit the upper 12 bits of the register are read/write and correspond to the upper 12 address bits a[31:20] of the 32-bit address. the bottom 4 bits of this register are read-only and return zeroes when read. configuration software must initialize this register. for the purpose of address decode, address bits a[19:0] are assumed to be fffffh. thus, the top of the defined memory address range will be at the top of a 1-mb aligned memory block. note: memory range covered by mbase and mlimit registers are used to map non-prefetchable pci express graphics address ranges (typically, where control/status memory-mapped i/o data structures of the graphics controller will reside) and pmbase and pmlimit are used to map prefetchable address ranges (typ ically, graphics local memory). this segregation allows application of uswc space attribute to be perfo rmed in a true plug-and-play manner to the prefetchable address range for improved pro cessor-pci express memory access performance. note: configuration software is responsible for progra mming all address range registers (prefetchable, non-prefetchable) with the values that provide exclusive address ranges (i.e., prevent overlap with each other and/or with the ranges covered with the main memory). there is no provision in the (g)mch hardware to enforce prevention of overlap and operations of the system in the case of overlap are not guaranteed. bit access & default description 15:4 r/w 000h memory address limit (mlimit): this field corresponds to a[31:20] of the upper limit of the address r ange passed to pci express*. 3:0 reserved host-pci express* bridge registers (d1:f0) (intel? 82915g/82915p/82915pl only) r datasheet 139 8.1.17 pmbase1?prefetchable memory base address (d1:f0) pci device: 1 address offset: 24h default value: fff0h access: ro, r/w size: 16 bits this register, in conjunction with the correspondi ng upper base address register, controls the processor-to-pci express graphics prefetchab le memory access routing based on the following formula: prefetchable_memory_base address prefetchable_memory_limit the upper 12 bits of this register are read/write and correspond to address bits a[31:20] of the 40- bit address. the lower 8 bits of the upper base address register are read/write and correspond to address bits a[39:32] of the 40-bit address. the configuration software must initialize this register. for the purpose of address decode, addre ss bits a[19:0] are assumed to be 0. thus, the bottom of the defined memory address ra nge will be aligned to a 1-mb boundary. bit access & default description 15:4 r/w fffh prefetchable memory base address (mbase): this field corresponds to a[31:20] of the lower limit of the memory range that will be passed to pci express*. 3:0 ro 0h 64-bit address support: this field indicates that the bridge supports only 32 bit addresses. host-pci express* bridge registers (d1:f0) (intel? 82915g/82915p/82915pl only) r 140 datasheet 8.1.18 pmlimit1?prefetchable memory limit address (d1:f0) pci device: 1 address offset: 26h default value: 0000h access: ro, r/w size: 16 bits this register, in conjunction with the corresponding upper limit address register, controls the processor-to-pci express graphics prefetchab le memory access routing based on the following formula: prefetchable_memory_base address prefetchable_memory_limit the upper 12 bits of this register are read/write and correspond to address bits a[31:20] of the 40- bit address. the lower 8 bits of the upper limit address register are read/write and correspond to address bits a[39:32] of the 40-bit address. the configuration software must initialize this register. for the purpose of address decode, a ddress bits a[19:0] are assumed to be fffffh. thus, the top of the defined memory address range will be at the top of a 1-mb aligned memory block. note that prefetchable memory range is supported to allow segregation by the configuration software between the memory ranges that must be defined as uc and the ones that can be designated as a uswc (i.e., prefet chable) from the processor perspective. bit access & default description 15:4 r/w 000h prefetchable memory address limit (pmlimit): this field corresponds to a[31:20] of the upper limit of the address range passed to pci express*. 3:0 ro 0h 64-bit address support: this field indicates the bridge supports only 32 bit addresses. 8.1.19 capptr1?capabilities pointer (d1:f0) pci device: 1 address offset: 34h default value: 88h access: ro size: 8 bits the capabilities pointer provides the address offset to the location of the first entry in this device?s linked list of capabilities. bit access & default description 7:0 ro 88h first capability (capptr1): the first capability in the list is the subsystem id and subsystem vendor id capability. host-pci express* bridge registers (d1:f0) (intel? 82915g/82915p/82915pl only) r datasheet 141 8.1.20 intrline1?interrupt line (d1:f0) pci device: 1 address offset: 3ch default value: 00h access: r/w size: 8 bits this register contains interrupt line routing information. the device itself does not use this value; rather device drivers and operating systems use it to determine priority and vector information. bit access & default description 7:0 r/w 00h interrupt connection: this field is used to communi cate interrupt line routing information. post software writes the routi ng information into this register as it initializes and configures the system. the value in this register indicates which input of the system interrupt controller th is device?s interrupt pin is connected to. 8.1.21 intrpin1?interrupt pin (d1:f0) pci device: 1 address offset: 3dh default value: 00h access: ro size: 8 bits this register specifies which interrupt pin this device uses. bit access & default description 7:0 ro 01h interrupt pin: as a single function device, the pci express* device specifies inta as its interrupt pin. 01h = inta host-pci express* bridge registers (d1:f0) (intel? 82915g/82915p/82915pl only) r 142 datasheet 8.1.22 bctrl1?bridge control (d1:f0) pci device: 1 address offset: 3eh default value: 0000h access: ro, r/w size: 16 bits this register provides extensions to the pcicmd1 register that are specific to pci-pci bridges. the bctrl provides additional control for the sec ondary interface (i.e., pci express) as well as some bits that affect the overall behavior of the ?virtual? host-pci express bridge embedded within (g)mch (e.g., vga compatible address ranges mapping). bit access & default description 15:12 reserved 11 ro 0b discard timer serr enable: hardwired to 0. 10 ro 0b discard timer status: hardwired to 0. 9 ro 0b secondary discard timer: hardwired to 0. 8 ro 0b primary discard timer: hardwired to 0. 7 ro 0b fast back-to-back enable (fb2ben): hardwired to 0. 6 r/w 0b secondary bus reset (sreset): setting this bit triggers a hot reset on the corresponding pci express* port. 5 ro 0b master abort mode (mamode): when acting as a master, unclaimed reads that experience a master abort returns a ll 1s and any writes that experience a master abort completes normally and the data is thrown away. hardwired to 0. 4 r/w 0b vga 16-bit decode: this bit enables the pci-to-p ci bridge to provide 16-bit decoding of vga i/o address precluding t he decoding of alias addresses every 1 kb. this bit only has meaning if bit 3 (vga e nable) of this register is also set to 1, enabling vga i/o decoding and forwarding by the bridge. 0 = execute 10-bit address decodes on vga i/o accesses. 1 = execute 16-bit address decodes on vga i/o accesses. 3 r/w 0b vga enable (vgaen): this bit controls the rout ing of processor-initiated transactions targeting vga compatible i/o and memory address ranges. see the vgaen/mdap table in device 0, offset 97h[0]. host-pci express* bridge registers (d1:f0) (intel? 82915g/82915p/82915pl only) r datasheet 143 bit access & default description 2 r/w 0b isa enable (isaen): this bit is needed to exclude legacy resource decode to route isa resources to legacy decode path. this bit modifies the response by the (g)mch to an i/o access issued by the proc essor that target isa i/o addresses. this applies only to i/o addresses t hat are enabled by the iobase and iolimit registers. 0 = all addresses defined by the io base and iolimit for processor i/o transactions will be mapped to pci express graphics. 1 = (g)mch will not forward to pci express graphics any i/o transactions addressing the last 768 bytes in each 1- kb block, even if the addresses are within the range defined by the iobase and iolimit registers. instead of going to pci express graphics, these cy cles are forwarded to dmi where they can be subtractively or posit ively claimed by the isa bridge. 1 r/w 0b serr enable (serren) 0 = no forwarding of error messages fr om secondary side to primary side that could result in an serr. 1 = err_cor, err_nonfatal, and err_fatal messages result in serr message when individually enabled by the root control register. 0 ro 0b parity error response enable (peren): this bit controls whether or not the master data parity error bit in the secondary status register is set when the mch receives across the link (upstream) a read data completion poisoned tlp. 0 = master data parity error bit in secondary status register cannot be set. 1 = master data parity error bit in secondary status register can be set.. host-pci express* bridge registers (d1:f0) (intel? 82915g/82915p/82915pl only) r 144 datasheet 8.1.23 pm_capid1?power management capabilities (d1:f0) pci device: 1 address offset: 80h default value: 1902 9001h or 1902 a001h access: ro size: 32 bits bit access & default description 31:27 ro 19h pme support: this field indicates the power st ates in which this device may indicate pme wake via pci express messaging. d0, d3hot, and d3cold. this device is not required to do anything to support d3hot and d3cold; it simply must report that those states are supported. refer to the pci power management 1.1 specification for encoding explanati on and other power management details. 26 ro 0b d2: hardwired to 0 to indicate that the d2 power management state is not supported. 25 ro 0b d1: hardwired to 0 to indicate that the d1 power management state is not supported. 24:22 ro 000b auxiliary current: hardwired to 0 to indicate that there are no 3.3vaux auxiliary current requirements. 21 ro 0 b device specific initialization (dsi): hardwired to 0 to indicate that special initialization of this device is not requir ed before generic class device driver is to use it. 20 ro 0b auxiliary power source (aps): hardwired to 0. 19 ro 0b pme clock: hardwired to 0 to indicate th is device does not support pme# generation. 18:16 ro 010b pci pm cap version: hardwired to 02h to indicate there are 4 bytes of power management registers implemented and that this device complies with revision 1.1 of the pci power management interface specification . 15:8 ro 90h or a0h pointer to next capability: this field contains a pointer to the next item in the capabilities list. if msich (capl[0] @ 7fh) is 0, then the next item in the capabilities list is the message signaled interrupts (msi) capability at 90h. if msich (capl[0] @ 7fh) is 1, then the next item in the capabilities list is the pci express* capability at a0h. 7:0 ro 01h capability id: value of 01h identifies this linked list item (capability structure) as being for pci power management registers. host-pci express* bridge registers (d1:f0) (intel? 82915g/82915p/82915pl only) r datasheet 145 8.1.24 pm_cs1?power management control/status (d1:f0) pci device: 1 address offset: 84h default value: 00000000h access: ro, r/w/s size: 32 bits bit access & default description 31:16 reserved 15 ro 0b pme status: this bit indicates that this device does not support pme# generation from d3 cold . 14:13 ro 00b data scale: this field indicates that this device does not support the power management data register. 12:9 ro 0h data select: this field indicates that this device does not support the power management data register. 8 r/w/s 0b pme enable: this bit indicates that th is device does not generate pmeb assertion from any d-state. 0 = pmeb generation not possible from any d state 1 = pmeb generation enabled from any d state the setting of this bit has no effect on hardware. see pm_cap[15:11] 7:2 reserved 1:0 r/w 00b power state: this field indicates the current power state of this device and can be used to set the device into a new power state. if software attempts to write an unsupported state to this field, write operation must complete normally on the bus, but the data is discarded and no state change occurs. 00 = d0 01 = d1 (not supported in this device.) 10 = d2 (not supported in this device.) 11 = d3 support of d3cold does not require any special action. while in the d3hot state, this device can only act as the target of pci configuration transactions (for power management control). this device also cannot generate interrupts or respond to mmr cycles in the d3 state. the device must return to the d0 state to be fully functional. there is no hardware functionality requi red to support these power states. host-pci express* bridge registers (d1:f0) (intel? 82915g/82915p/82915pl only) r 146 datasheet 8.1.25 ss_capid?subsystem id and vendor id capabilities (d1:f0) pci device: 1 address offset: 88h default value: 0000800dh access: ro size: 32 bits this capability is used to unique ly identify the subsystem where the pci device resides. because this device is an integrated part of the system and not an add-in device, it is anticipated that this capability will never be used. however, it is n ecessary because microsoft will test for its presence. bit access & default description 31:16 reserved 15:8 ro 80h pointer to next capability: this field contains a pointer to the next item in the capabilities list which is the pci power management capability. 7:0 ro 0d h capability id: a value of 0dh identifies this lin ked list item (capability structure) as being for ssid/ssvid registers in a pci-to-pci bridge. 8.1.26 ss?subsystem id and subsystem vendor id (d1:f0) pci device: 1 address offset: 8ch default value: 00008086h access: ro size: 32 bits system bios can be used as the mechanism fo r loading the ssid/svid values. these values must be preserved through power manageme nt transitions and hardware reset. bit access & default description 31:16 r/wo 0000h subsystem id (ssid): this field identifies the particular subsystem and is assigned by the vendor. 15:0 r/wo 8086h subsystem vendor id (ssvid): this field identifies the manufacturer of the subsystem and is the same as the vendor id that is assigned by the pci special interest group. host-pci express* bridge registers (d1:f0) (intel? 82915g/82915p/82915pl only) r datasheet 147 8.1.27 msi_capid?message signaled interrupts capability id (d1:f0) pci device: 1 address offset: 90h default value: a005h access: ro size: 16 bits when a device supports msi, it can generate an interrupt request to the processor by writing a predefined data item (a message) to a predefined memory address. the reporting of the existence of this capability can be disabled by setting msich (capl [0] at 7fh). in that case walking this linked list will skip this capability and, instead, go directly from the pci pm capability to the pci express capability. bit access & default description 15:8 ro a0h pointer to next capability: this field contains a pointer to the next item in the capabilities list that is the pci express* capability. 7:0 ro 05h capability id: 05h = identifies this linked list item (capability structure) as being for msi registers. host-pci express* bridge registers (d1:f0) (intel? 82915g/82915p/82915pl only) r 148 datasheet 8.1.28 mc?message control (d1:f0) pci device: 1 address offset: 92h default value: 0000h access: ro, r/w size: 16 bits system software can modify bits in this register, but the device is prohibited from doing so. if the device writes the same message multiple times, only one of those messages is guaranteed to be serviced. if all of them must be serviced, th e device must not generate the same message again until the driver services the earlier one. bit access & default description 15:8 reserved 7 ro 0b 64-bit address capable: hardwired to 0 to indicate that the function does not implement the upper 32 bits of the mess age address register and is incapable of generating a 64-bit memory address. 6:4 r/w 000b multiple message enable (mme): system software programs this field to indicate the actual number of messages a llocated to this device. this number will be equal to or less than the number actually requested. 000 = 1 message allocated 001?111 = reserved 3:1 ro 000b multiple message capable (mmc): system software reads this field to determine the number of messages being requested by this device. 000 = 1 message requested 001?111 = reserved 0 r/w 0b msi enable (msien) controls the ability of this device to generate msis. 0 = msi will not be generated. 1 = msi will be generated when we receive pme or hotplug messages. inta will not be generated and inta status (pcists1[3]) will not be set. host-pci express* bridge registers (d1:f0) (intel? 82915g/82915p/82915pl only) r datasheet 149 8.1.29 ma?message address (d1:f0) pci device: 1 address offset: 94h default value: 00000000h access: ro, r/w size: 32 bits bit access & default description 31:2 r/w 00000000 h message address: this field is used by system software to assign an msi address to the device. the device handles an msi by writing the padded contents of the md register to this address. 1:0 ro 00b force dword align: hardwired to 0 so that addresses assigned by system software are always aligned on a dword address boundary. 8.1.30 md?message data (d1:f0) pci device: 1 address offset: 98h default value: 0000h access: r/w size: 16 bits bit access & default description 15:0 r/w 0000h message data: this field provides a base message data pattern assigned by system software and used to handle an msi from the device. when the device must generate an interrupt request, it writes a 32-bit value to the memory address specified in the ma register. the upper 16 bits are always set to 0. this register supplies the lower 16 bits. host-pci express* bridge registers (d1:f0) (intel? 82915g/82915p/82915pl only) r 150 datasheet 8.1.31 peg_capl?pci express* capability list (d1:f0) pci device: 1 address offset: a0h default value: 0010h access: ro size: 16 bits this register enumerates the pci express capability structure. bit access & default description 15:8 ro 00h pointer to next capability: this value terminates the capabilities list. the virtual channel capability and any other pci expre ss* specific capabilities that are reported via this mechanism are in a separate capabilities list located entirely within pci express extended configuration space. 7:0 ro 10h capability id: this field identifies this linked list item (capability structure) as being for pci express registers. 8.1.32 peg_cap?pci express*-g capabilities (d1:f0) pci device: 1 address offset: a2h default value: 0141h access: ro size: 16 bits indicates pci express device capabilities. bit access & default description 15:14 reserved 13:9 ro 00h interrupt message number: hardwired to 0. 8 r/wo 1b slot implemented 0 = the pci express* link associated wi th this port is connected to an integrated component or is disabled. 1 = the pci express link associated wi th this port is connected to a slot. bios must initialize this field appropriate ly if a slot connection is not implemented. 7:4 ro 4h device/port type: hardwired to 0100 to indicate root port of pci express root complex. 3:0 ro 1h pci express capability version: hardwired to 1 as it is the first version. host-pci express* bridge registers (d1:f0) (intel? 82915g/82915p/82915pl only) r datasheet 151 8.1.33 dcap?device capabilities (d1:f0) pci device: 1 address offset: a4h default value: 00000000h access: ro size: 32 bits this register indicates pci express link capabilities. bit access & default description 31:6 reserved 5 ro 0b extended tag field supported: hardwired to indicate support for 5-bit tags as a requestor. 4:3 ro 00b phantom functions supported: hardwired to 0. 2:0 ro 000b max payload size: hardwired to indicate 128b maximum supported payload for transaction layer packets (tlp). host-pci express* bridge registers (d1:f0) (intel? 82915g/82915p/82915pl only) r 152 datasheet 8.1.34 dctl?device control (d1:f0) pci device: 1 address offset: a8h default value: 0000h access: r/w size: 16 bits this register provides control for pci express device specific capabilities. the error reporting enable bits are in reference to errors detected by this device, not error messages received across the link. the reporting of error messages (err_corr, err_nonfatal, err_fatal) received by root port is controlled exclus ively by root port command register. bit access & default description 15:8 reserved 7:5 r/w 000b max payload size 000 = 128b maximum supported payload for transaction layer packets (tlp). as a receiver, the device must handle tl ps as large as the set value; as transmitter, the device must not gener ate tlps exceeding the set value. note: all other encodings are reserved. 4 reserved 3 r/w 0b unsupported request reporting enable: 0 = disable. 1 = enable. unsupported requests will be reported. note that reporting of error messages received by root port is controlled exclusively by root control register. 2 r/w 0b fatal error reporting enable: 0 = disable. 1 = enable. fatal errors will be reported. for a root port, the reporting of fatal errors is internal to the root. no external err_fatal message is generated. 1 r/w 0b non-fatal error reporting enable: 0 = disable. 1 = enable. non-fatal errors will be reported. for a root port, the reporting of non-fatal errors is internal to t he root. no external err_nonfatal message is generated. uncorrectable errors can result in degraded performance. 0 r/w 0b correctable error reporting enable: 0 = disable. 1 = enable. correctable errors will be reported. for a root port, the reporting of correctable errors is internal to t he root. no external err_corr message is generated. host-pci express* bridge registers (d1:f0) (intel? 82915g/82915p/82915pl only) r datasheet 153 8.1.35 dsts?device status (d1:f0) pci device: 1 address offset: aah default value: 0000h access: ro size: 16 bits this register reflects status corresponding to controls in the device control register. note: the error reporting bits are in reference to errors detected by this device, not errors messages received across the link. bit access & default description 15:6 reserved 5 ro 0b transactions pending 0 = all pending transacti ons (including completi ons for any outstanding non- posted requests on any used virtual channel) have been completed. 1 = device has transaction(s) pending (i ncluding completions for any outstanding non-posted requests for all used traffic classes). 4 reserved 3 r/wc 0b unsupported request detected: 1 = device received an unsupported reques t. errors are logged in this register regardless of whether error reporting is enabled or not in the device control register. 2 r/wc 0b fatal error detected: 1 = fatal error(s) were detected. errors are logged in this register regardless of whether error reporting is enabled or not in the device control register. 1 r/wc 0b non-fatal error detected: 1 = non-fatal error(s) were detected. erro rs are logged in this register regardless of whether error reporting is enabled or not in the device control register. 0 r/wc 0b correctable error detected: 1 = correctable error(s) were detected. errors are logged in this register regardless of whether error reporting is enabled or not in the device control register. note: the (g)mch may report a false 8b/10b receiver error when exiting l0s. this is reported thru the correctable e rror detected bit cests device 1, offset 1d0h, bit [0]. this will reduce the value of receiver error detection when l0s is enabled. disable l0s for accurate receiver error reporting. host-pci express* bridge registers (d1:f0) (intel? 82915g/82915p/82915pl only) r 154 datasheet 8.1.36 lcap?link capabilities (d1:f0) pci device: 1 address offset: ach default value: 02012e01h access: r/wo size: 16 bits this register indicates pci express device specific capabilities. bit access & default description 31:24 ro 02h port number: this field indicates the pci expr ess* port number for the given pci express link. this field matches the va lue in element self description [31:24]. 23:18 reserved 17:15 r/wo 010b l1 exit latency: this field indicates the length of time this port requires to complete the transition from l1 to l0. the value 010 b indicates the range of 2 s to less than 4 s. if this field is requi red to be any value other than the default, bios must initialize it accordingly. both bytes of this register that contai n a portion of this field must be written simultaneously in order to prevent an intermediate (and undesired) value from ever existing. 14:12 r/wo 010b l0s exit latency: this field indicates the length of time this port requires to complete the transition from l0s to l0. the value 010 b indicates the range of 128 ns to less than 256 ns. if this field is required to be any value other than the default, bios must initialize it accordingly. note: when pci express* is operating with separate reference clocks, l0s exit latency may be greater than the setting in the l0s exit latency register. expect longer exit latency then setting in l0s exit latency register. the link may enter recovery state before reaching l0. system bios can program the appropriate exit latency and advertised n_fts value if it detects that the downstream device is not using the common reference clock (indicated in the slot clock conf iguration bit 12 of the device?s link status register) 11:10 r/wo 11b active state link pm support: l0s & l1 entry supported. 9:4 ro 10h max link width: hardwired to indicate x16. when force x1 mode is enabled on this pci express* x16 graphics interface device, this field reflects x1 (01h). 3:0 ro 1h max link speed: hardwired to indicate 2.5 gb/s. host-pci express* bridge registers (d1:f0) (intel? 82915g/82915p/82915pl only) r datasheet 155 8.1.37 lctl?link control (d1:f0) pci device: 1 address offset: b0h default value: 0000h access: ro, r/w size: 16 bits this register allows control of pci express link. bit access & default description 15:8 reserved 7 r/w 0h reserved. must be 0 when writing this register. 6 r/w 0b common clock configuration 0 = this component and the component at the opposite end of this link are operating with asynchronous reference clock. 1 = this component and the component at the opposite end of this link are operating with a distributed common reference clock. components use this common clock configurat ion information to report the correct l0s and l1 exit latencies. 5 r/w 0b retrain link 0 = normal operation 1 = full link retraining is initiated by di recting the physical layer ltssm from l0, l0s, or l1 states to the recovery state. this bit always returns 0 when read. this bit is cleared automatically (no need to write a 0). 4 r/w 0b link disable 0 = normal operation 1 = link is disabled. forc es the ltssm to transition to the disabled state (via recovery) from l0, l0s, or l1 states. link retraining happens automatically on 0 to 0 transition, just like when coming out of reset. writes to this bit are immedi ately reflected in the value read from the bit, regardless of actual link state. 3 ro 0b read completion boundary (rcb): hardwired to 0 to indicate 64 byte. 2 reserved 1:0 r/w 00b active state pm: this field controls the level of active state power management supported on the given link. 00 = disabled 01 = l0s entry supported 10 = reserved 11 = l0s and l1 entry supported host-pci express* bridge registers (d1:f0) (intel? 82915g/82915p/82915pl only) r 156 datasheet 8.1.38 lsts?link status (d1:f0) pci device: 1 address offset: b2h default value: 1001h access: ro size: 16 bits this register indicates pci express link status. bit access & default description 15:13 reserved 12 ro 1b slot clock configuration 0 = the device uses an independent clock irrespective of the presence of a reference on the connector. 1 = the device uses the same physical refe rence clock that the platform provides on the connector. 11 ro 0b link training: 1 = link training is in progress. hardwa re clears this bit onc e link training is complete. 10 ro 0b training error: 1 = this bit is set by hardware upon detecti on of unsuccessful training of the link to the l0 link state. 9:4 ro 00h negotiated width: this field indicates negotiated link width. this field is valid only when the link is in the l0, l0s, or l1 states (after link width negotiation is successfully completed). 00h = reserved 01h = x1 04h = reserved 08h = reserved 10h = x16 all other encodings are reserved. 3:0 ro 1h negotiated speed: this field indicates negotiated link speed. 1h = 2.5 gb/s all other encodings are reserved. host-pci express* bridge registers (d1:f0) (intel? 82915g/82915p/82915pl only) r datasheet 157 8.1.39 slotcap?slot capabilities (d1:f0) pci device: 1 address offset: b4h default value: 00000000h access: r/wo size: 32 bits pci express slot-related registers allow for the support of hot-plug. bit access & default description 31:19 r/wo 0000h physical slot number: this field indicates the physical slot number attached to this port. this field must be initialized by bios to a value that assigns a slot number that is globally unique within the chassis. 18:17 reserved 16:15 r/wo 00b slot power limit scale: this field specifies the scale used for the slot power limit value. 00 = 1.0x 01 = 0.1x 10 = 0.01x 11 = 0.001x if this field is written, the link sends a set_slot_power_limit message. 14:7 r/wo 00h slot power limit value: in combination with the slot power limit scale value, this field specifies the upper limit on pow er supplied by slot. power limit (in watts) is calculated by multiplying the value in this field by the value in the slot power limit scale field. if this field is written, the link sends a set_slot_power_limit message. 6 r/wo 0b hot-plug capable: this field indicates that this slot is capable of supporting hot-plug operations. 5 r/wo 0b hot-plug surprise: this field indicates that a devic e present in this slot might be removed from the system without any prior notification. 4 r/wo 0b power indicator present: this field indicates that a power indicator is implemented on the chassis for this slot. 3 r/wo 0b attention indicator present: this field indicates that an attention indicator is implemented on the chassis for this slot. 2:1 reserved 0 r/wo 0b attention button present: this field indicates that an attention button is implemented on the chassis for this slot. t he attention button allows the user to request hot-plug operations. host-pci express* bridge registers (d1:f0) (intel? 82915g/82915p/82915pl only) r 158 datasheet 8.1.40 slotctl?slot control (d1:f0) pci device: 1 address offset: b8h default value: 01c0h access: r/w size: 16 bits pci express slot related registers allow for the support of hot-plug. bit access & default description 15:10 reserved 9:8 r/w 01b power indicator control: reads to this register return the current state of the power indicator. writes to this register set the power indicator and cause the port to send the appropriate power_indicator_* messages. 00 = reserved 01 = on 10 = blink 11 = off 7:6 r/w 11b attention indicator control: reads to this register return the current state of the attention indicator. writes to this register set the attenti on indicator and cause the port to send the appropriate attention_indicator_* messages. 00 = reserved 01 = on 10 = blink 11 = off 5 r/w 0b hot plug interrupt enable: 0 = disable. 1 = enables generation of hot plug interrupt on enabled hot plug events. 4 r/w 0b command completed interrupt enable: 0 = disable. 1 = enables the generation of hot plug interrupt when the hot plug controller completes a command. 3 r/w 0b presence detect changed enable: 0 = disable. 1 = enables the generation of hot plug interrupt or wake message on a presence detect changed event. 2:1 reserved 0 r/w 0b attention button pressed enable: 0 = disable. 1 = enables the generation of hot plug interrupt or wake message on an attention button pressed event. host-pci express* bridge registers (d1:f0) (intel? 82915g/82915p/82915pl only) r datasheet 159 8.1.41 slotsts?slot status (d1:f0) pci device: 1 address offset: bah default value: 0x00h access: ro, r/w/c size: 16 bits pci express slot-related registers allow for the support of hot-plug. bit access & default description 15:7 reserved 6 ro xb presence detect state: this bit indicates the presence of a card in the slot. 0 = slot empty 1 = card present in slot. 5 reserved 4 r/wc 0b command completed: 1 = hot plug controller completed an issued command. 3 r/wc 0b presence detect changed: 1 = presence detect change is detect ed. this corresponds to an edge on the signal that corresponds to bit 6 of this register (presence detect state). 2:1 reserved 0 r/wc 0b attention button pressed: 1 = attention button is pressed. host-pci express* bridge registers (d1:f0) (intel? 82915g/82915p/82915pl only) r 160 datasheet 8.1.42 rctl?root control (d1:f0) pci device: 1 address offset: bch default value: 0000h access: r/w size: 16 bits this register allows control of pci express root complex specific parameters. the system error control bits in this register determine if corresponding serrs are generated when our device detects an error (reported in this device?s device status register) or when an error message is received across the link. reporting of serr as c ontrolled by these bits takes precedence over the serr enable in the pci command register. bit access & default description 15:4 reserved 3 r/w 0b pme interrupt enable 0 = no interrupts are generated as a result of receiving pme messages. 1 = enables interrupt generation upon rece ipt of a pme message as reflected in the pme status bit of the root status register. a pme interrupt is also generated if the pme status bit of the root status register is set when this bit is set from a cleared state. 2 r/w 0b system error on fatal error enable: this bit controls the root complex?s response to fatal errors. 0 = no serr generated on receipt of fatal error. 1 = indicates that an serr should be generated if a fatal error is reported by any of the devices in the hierarchy associated with this root port, or by the root port itself. 1 r/w 0b system error on non-fatal un correctable error enable: this bit controls the root complex?s response to non-fatal errors. 0 = no serr generated on receipt of non-fatal error. 1 = indicates that an serr should be generated if a non-fatal error is reported by any of the devices in the hierarchy associated with this root port, or by the root port itself. 0 r/w 0b system error on correctable error enable: this bit controls the root complex?s response to correctable errors. 0 = no serr generated on receipt of correctable error. 1 = indicates that an serr should be generated if a correctable error is reported by any of the devices in the hierarchy associated with this root port, or by the root port itself. host-pci express* bridge registers (d1:f0) (intel? 82915g/82915p/82915pl only) r datasheet 161 8.1.43 rsts?root status (d1:f0) pci device: 1 address offset: c0h default value: 00000000h access: ro, r/w/c size: 32 bits this register provides information about pci express root complex specific parameters. bit access & default description 31:18 reserved 17 ro 0b pme pending: this bit indicates that another pme is pending when the pme status bit is set. when the pme status bit is cleared by software; the pme is delivered by hardware by setting the pme status bit again and updating the requestor id appropriately. the pme pending bit is cleared by hardware if no more pmes are pending. 16 r/w/c 0b pme status: this bit indicates that the requestor id indicated in the pme requestor id field asserted pme. s ubsequent pmes are kept pending until the status register is cleared by writing a 1 to this field. 15:0 ro 0000h pme requestor id: this field indicates the pci requestor id of the last pme requestor. host-pci express* bridge registers (d1:f0) (intel? 82915g/82915p/82915pl only) r 162 datasheet 8.1.44 peglc?pci express*-g legacy control pci device: 1 address offset: ech default value: 00000000h access: ro, r/w size: 32 bits this register controls functiona lity that is needed by legacy (non-pci express aware) os?s during run time. bit access & default description 31:3 ro 0000 0000h reserved 2 r/w 0b pme gpe enable (pmegpe): 0 = do not generate gpe pme message when pme is received. 1 = enable. generate a gpe pme message when pme is received (assert_pmegpe and deassert_pmeg pe messages on dmi). this enables the (g)mch to support pmes on the pc i express* x16 graphics interface port under legacy oss. 1 r/w 0b hot-plug gpe enable (hpgpe) 0 = do not generate gpe hot-plug message when hot-plug event is received. 1 = enable. generate a gpe hot-plug me ssage when hot-plug event is received (assert_hpgpe and deassert_hpgpe messages on dmi). this enables the (g)mch to support hot-plug on the pci express* x16 graphics interface port under legacy oss. 0 r/w 0b general message gpe enable (gengpe) 0 = do not forward received gpe assert/deassert messages. 1 = enable. forward received gpe a ssert/deassert messages. these general gpe message can be received via the pc i express* x16 graphics interface port from an external intel device and will be subsequently forwarded to the intel ? ich6 (via assert_gpe and deassert_gpe messages on dmi). host-pci express* bridge registers (d1:f0) (intel? 82915g/82915p/82915pl only) r datasheet 163 8.1.45 vcech?virtual channel enhanced capability header (d1:f0) pci device: 1 address offset: 100h default value: 14010002h access: ro size: 32 bits this register indicates pci express device virtual channel capabilities. note: extended capability structures for pci express devices are located in pci express extended configuration space and ha ve different field defi nitions than standard pci capability structures. bit access & default description 31:20 ro 140h pointer to next capability: the link declaration capability is the next in the pci express* extended capabilities list. 19:16 ro 1h pci express virtual channel capability version: hardwired to 1 to indicate compliances with the 1.0a version of the pci express specification. 15:0 ro 0002h extended capability id: value of 0002 h identifies this linked list item (capability structure) as being for pci ex press virtual channel registers. 8.1.46 pvccap1?port vc capability register 1 (d1:f0) pci device: 1 address offset: 104h default value: 00000001h access: ro, r/wo size: 32 bits this register describes the configuration of pci express virtual channels associated with this port. bit access & default description 31:7 reserved 6:4 ro 000b low priority extended vc count: this field indicates the number of (extended) virtual channels in addition to the default vc belonging to the low-priority vc (lpvc) group that has the lowest priority with respect to other vc resources in a strict-priority vc arbitration. the value of 0 in this field implies strict vc arbitration. 3 reserved 2:0 r/wo 001b extended vc count: this field indicates the number of (extended) virtual channels in addition to the default vc supported by the device. host-pci express* bridge registers (d1:f0) (intel? 82915g/82915p/82915pl only) r 164 datasheet 8.1.47 pvccap2?port vc capability register 2 (d1:f0) pci device: 1 address offset: 108h default value: 00000001h access: ro size: 32 bits this register describes the configuration of pci express virtual channels associated with this port. bit access & default description 31:24 ro 00h vc arbitration table offset: this field indicates the location of the vc arbitration table. this field contains the zero-bas ed offset of the table in dqwords (16 bytes) from the base address of the virt ual channel capability structure. a value of 0 indicates that the table is not present (due to fixed vc priority). 23:8 reserved 7:0 ro 01h vc arbitration capability: this field indicates that the only possible vc arbitration scheme is hardware fixed (in the root complex). vc1 is the highest priority, vc0 is the lowest priority. 8.1.48 pvcctl?port vc control (d1:f0) pci device: 1 address offset: 10ch default value: 0000h access: r/w size: 16 bits bit access & default description 15:4 reserved 3:1 r/w 000b vc arbitration select: this field will be programmed by software to the only possible value as indicated in the vc ar bitration capability field. the value 001b when written to this field will indicate t he vc arbitration scheme is hardware fixed (in the root complex). this field can not be modified when mo re than one vc in the lpvc group is enabled. 0 reserved host-pci express* bridge registers (d1:f0) (intel? 82915g/82915p/82915pl only) r datasheet 165 8.1.49 vc0rcap?vc0 resource capability (d1:f0) pci device: 1 address offset: 110h default value: 00000000h access: ro size: 32 bits bit access & default description 31:16 reserved 15 ro 0b reject snoop transactions 0 = transactions with or without the no snoop bit set within the tlp header are allowed on this vc. 1 = any transaction without the no snoop bit set within the tlp header will be rejected as an unsupported request. 14:0 reserved 8.1.50 vc0rctl?vc0 resource control (d1:f0) pci device: 1 address offset: 114h default value: 8000007fh access: ro, r/w size: 32 bits this register controls the resources associated with pci express virtual channel 0. bit access & default description 31 ro 1b vc0 enable: for vc0, this is hardwired to 1 and read only as vc0 can never be disabled. 30:27 reserved 26:24 ro 000b vc0 id: this field assigns a vc id to the vc resource. for vc0 this is hardwired to 0 and read only. 23:8 reserved 7:1 r/w 7fh tc/vc0 map: this field indicates the tcs (traffic classes) that are mapped to the vc resource. bit locations within this field correspond to tc values. for example, when bit 7 is set in this field, tc7 is mapped to this vc resource. when more than one bit in this field is set, it indicates that multiple tcs are mapped to the vc resource. in order to remove one or more tcs from the tc/vc map of an enabled vc, software must ensure that no new or outstanding transactions with the tc labels are targeted at the given link. 0 ro 1b tc0/vc0 map: traffic class 0 is always routed to vc0. host-pci express* bridge registers (d1:f0) (intel? 82915g/82915p/82915pl only) r 166 datasheet 8.1.51 vc0rsts?vc0 resource status (d1:f0) pci device: 1 address offset: 11ah default value: 0000h access: ro size: 16 bits this register reports the vi rtual channel specific status. bit access & default description 15:2 reserved 1 ro 1b vc0 negotiation pending 0 = the vc negotiation is complete. 1 = the vc resource is still in the pr ocess of negotiation (initialization or disabling). this bit indicates the status of the process of flow control initialization. it is set by default on reset, as well as whenever the corresponding virtual channel is disabled or the link is in the dl_d own state. it is cleared when the link successfully exits the fc_init2 state before using a virtual channel, software must check whether the vc negotiation pending fields for that vi rtual channel are cleared in both components on a link. 0 reserved 8.1.52 vc1rcap?vc1 resource capability (d1:f0) pci device: 1 address offset: 11ch default value: 00008000h access: ro size: 32 bits bit access & default description 31:16 reserved 15 ro 1b reject snoop transactions 0 = transactions with or without the no snoop bit set within the tlp header are allowed on this vc. 1 = any transaction without the no snoop bit set within the tlp header will be rejected as an unsupported request. 14:0 reserved host-pci express* bridge registers (d1:f0) (intel? 82915g/82915p/82915pl only) r datasheet 167 8.1.53 vc1rctl?vc1 resource control (d1:f0) pci device: 1 address offset: 120h default value: 01000000h access: ro, r/w size: 32 bits controls the resources associated with pci express virtual channel 1. bit access & default description 31 r/w 0b vc1 enable 0 = virtual channel is disabled. 1 = virtual channel is enabled. s ee exceptions in note below. software must use the vc negotiation pending bit to check whether the vc negotiation is complete. when vc negotia tion pending bit is cleared, a 1 read from this vc enable bit indicates that the vc is enabled (flow control initialization is completed for the pci express* port); a 0 read from this bit indicates that the virtual c hannel is currently disabled. notes: ? to enable a virtual channel, the vc enabl e bits for that virtual channel must be set in both components on a link. ? to disable a virtual channel, the vc e nable bits for that virtual channel must be cleared in both components on a link. ? software must ensure that no traffic is us ing a virtual channel at the time it is disabled. ? software must fully disable a virt ual channel in both components on a link before re-enabling the virtual channel. 30:27 reserved 26:24 r/w 001b vc1 id: assigns a vc id to the vc resource. assigned value must be non-zero. this field cannot be modified w hen the vc is already enabled. 23:8 reserved 7:1 r/w 00h tc/vc1 map: this field indicates the tcs (traffic classes) that are mapped to the vc resource. bit locations within this field correspond to tc values. for example, when bit 7 is set in this field, tc7 is mapped to this vc resource. when more than one bit in this field is set, it indicates that multiple tcs are mapped to the vc resource. in order to remove one or more tcs from the tc/vc map of an enabled vc, software must ensure that no new or outstanding transactions with the tc labels are targeted at the given link. 0 ro 0b tc0/vc1 map: traffic class 0 is always routed to vc0. host-pci express* bridge registers (d1:f0) (intel? 82915g/82915p/82915pl only) r 168 datasheet 8.1.54 vc1rsts?vc1 resource status (d1:f0) pci device: 1 address offset: 126h default value: 0000h access: ro size: 16 bits this register reports the vi rtual channel specific status. bit access & default description 15:2 reserved 1 ro 1b vc1 negotiation pending 0 = the vc negotiation is complete. 1 = the vc resource is still in the pr ocess of negotiation (initialization or disabling). this bit indicates the status of the process of flow control initialization. it is set by default on reset, as well as when the co rresponding virtual c hannel is disabled or the link is in the dl_down state. it is cleared when the link successfully exits the fc_init2 state before using a virtual channel, software must check whether the vc negotiation pending fields for that vi rtual channel are cleared in both components on a link. 0 reserved 8.1.55 rcldech?root complex link declaration enhanced capability header (d1:f0) pci device: 1 address offset: 140h default value: 00010005h access: ro size: 32 bits this capability declares links fro m this element (pci express* x16 graphics interface) to other elements of the root complex component to which it belongs. see the pci express specification for link/topology declaration requirements. bit access & default description 31:20 ro 000h pointer to next capability: this is the last capability in the pci express* extended capabilities list. 19:16 ro 1h link declaration capability version: hardwired to 1 to indicate compliances with the 1.0a version of the pci express specification. 15:0 ro 0005h extended capability id: value of 0005h identifies this linked list item (capability structure) as being for pci expr ess link declaration capability. note: see corresponding egress port li nk declaration capability regi sters for diagram of link declaration topology. host-pci express* bridge registers (d1:f0) (intel? 82915g/82915p/82915pl only) r datasheet 169 8.1.56 esd?element self description (d1:f0) pci device: 1 address offset: 144h default value: 02000100h access: ro, r/wo size: 32 bits this register provides information about the root complex element containing this link declaration capability. bit access & default description 31:24 ro 02h port number: this field specifies the port number associated with this element with respect to the component that contai ns this element. the egress port of the component to provide arbitration to this root complex element uses this port number value. 23:16 r/wo 00h component id: this field indicates the physica l component that contains this root complex element. component ids start at 1. this value is a mirror of the value in the component id field of all elements in this component. the value only needs to be written in one of the mirrored fields and it will be reflected everywhere that it is mirrored. 15:8 ro 01h number of link entries: this field indicates the number of link entries following the element self description. this fiel d reports 1 (to egress port only as peer-to- peer capabilities in this topology are not reported). 7:4 reserved 3:0 ro 0h element type: this field indicates the type of the root complex element. 0h = root port. host-pci express* bridge registers (d1:f0) (intel? 82915g/82915p/82915pl only) r 170 datasheet 8.1.57 le1d?link entry 1 description (d1:f0) pci device: 1 address offset: 150h default value: 00000000h access: ro, r/wo size: 32 bits this register provides the first part of a link entry that declares an internal link to another root complex element. bit access & default description 31:24 ro 00h target port number: this field specifies the port number associated with the element targeted by this link entry (egress port). the target port number is with respect to the component that contains th is element as specified by the target component id. 23:16 r/wo 00h target component id: this field indicates the physical or logical component that is targeted by this link entry. a value of 0 is reserved; component ids start at 1. this value is a mirror of the value in the component id field of all elements in this component. the value only needs to be written in one of the mirrored fields and it will be reflected everywhere that it is mirrored. 15:2 reserved 1 ro 0b link type: this field indicates that the lin k points to memory-mapped space (for rcrb). the link address specifies the 64- bit base address of the target rcrb. 0 r/wo 0b link valid: 0 = link entry is not valid and will be ignored. 1 = link entry specifies a valid link. host-pci express* bridge registers (d1:f0) (intel? 82915g/82915p/82915pl only) r datasheet 171 8.1.58 le1a?link entry 1 address (d1:f0) pci device: 1 address offset: 158h default value: 0000000000000000h access: r/wo size: 64 bits this register provides the second part of a link entry that declares an internal link to another root complex element. bit access & default description 63:32 reserved 31:12 r/wo 0 0000h link address: this field indicates memory-mapped base address of the rcrb that is the target element (egress port) for this link entry. 11:0 reserved 8.1.59 pegssts?pci express*-g sequence status (d1:f0) pci device: 1 address offset: 218h default value: 0000000000000fffh access: ro size: 64 bits this register provides pci express status reporting that is required by the pci express specification. bit access & default description 63:60 reserved 59:48 ro 000h next transmit sequence number: value of the nxt_trans_seq counter. this counter represents the transmit sequence number to be applied to the next tlp to be transmitted onto the link for the first time. 47:44 reserved 43:32 ro 000h next packet sequence number: packet sequence number to be applied to the next tlp to be transmitted or re-transmitted onto the link. 31:28 reserved 27:16 ro 000h next receive sequence number: this is the sequence number associated with the tlp that is expected to be received next. 15:12 reserved 11:0 ro fffh last acknowledged sequence number: this is the sequence number associated with the last acknowledged tlp. integrated graphics device registers (d2:f0) (intel? 82915g/82915gv/82915GL/ 82910gl gmch only) r datasheet 173 9 integrated graphics device registers (d2:f0) (intel ? 82915g/82915gv/82915GL/ 82910gl gmch only) device 2 contains registers for the internal graphics functions. table 9-1 lists the pci configuration registers in orde r of ascending offset address. function 0 can be vga compatible or not, this is selected through bit 1 of ggc register (device 0, offset 52h). the following sections describe device 2 pci configuration registers only. table 9-1. integrated graphics device register address map (d2:f0) address offset register symbol register name default value access 00?01h vid2 vendor identification 8086h ro 02?03h did2 device identification 2582h ro 04?05h pcicmd2 pci command 0000h ro, r/w 06?07h pcists2 pci status 0090h ro 08h rid2 revision identification see register description ro 09?0bh cc class code 030000h ro 0ch cls cache line size 00h ro 0dh mlt2 master latency timer 00h ro 0eh hdr2 header type 80h ro 0fh ? reserved ? ? 10?13h mmadr memory mapped range address 00000000h ro, r/w 14?17h iobar i/o base address 00000001h ro, r/w 18?1bh gmadr graphics memory range address 00000008h ro, r/w/l 1c?1fh gttadr graphics translation t able range address 00000000h ro, r/w 20?2bh ? reserved ? ? 2c?2dh svid2 subsystem vendor identification 0000h r/wo 2e?2fh sid2 subsystem identification 0000h r/wo 30?33h romadr video bios rom base address 00000000h ro 34h cappoint capabilities pointer d0h ro 35?3bh ? reserved ? ? integrated graphics device registers (d2:f0) (intel? 82915g/82915gv/82915GL/ 82910gl gmch only) r 174 datasheet address offset register symbol register name default value access 3ch intrline interrupt line 00h r/w 3dh intrpin interrupt pin 01h ro 3eh mingnt minimum grant 00h ro 3fh maxlat maximum latency 00h ro 40?43h ? reserved ? ? 44h mcapptr mirror of dev0 capability pointer d0h ro 45?47h ? reserved ? ? 48?50h mcapid mirror of dev0 capability identification 0000000000 01090009h ro 51h ? reserved ? ? 52?53h mggc mirror of dev0 gmch graphics control 0030h ro 54?57h mdevende v0f0 mirror of dev0 device enable 00000019h ro 58?5bh ? reserved ? ? 5c?5fh bsm base of stolen memory 07800000h ro 60?61h ? reserved ? ? 62h msac multi size aperture control 00h r/w 63?cfh ? reserved ? ? d0?d1h pmcapid power management capabilities id 0001h ro d2?d3h pmcap power management capabilities 0022h ro d4?d5h pmcs power management control/status 0000h ro, r/w d6?d7h ? reserved ? ? e0?e1h swsmi software smi 0000h r/w e2?e3h ? reserved ? ? e4?e7 asle system display event 00000000h r/w e8h?fbh ? reserved ? ? fc?ffh asls asl storage 00000000h r/w integrated graphics device registers (d2:f0) (intel? 82915g/82915gv/82915GL/ 82910gl gmch only) r datasheet 175 9.1 integrated graphics device pci register details (d2:f0) 9.1.1 vid2?vendor identification (d2:f0) pci device: 2 address offset: 00h default value: 8086h access: ro size: 16 bits this register, combined with the device identification register, uniquely identifies any pci device. bit access & default description 15:0 ro 8086h vendor identification number (vid): pci standard identification for intel. 9.1.2 did2?device identification (d2:f0) pci device: 2 address offset: 02h default value: 2582h access: ro size: 16 bits this register, combined with the vendor identification register, uniquely identifies any pci device. bit access & default description 15:0 ro 2582h device identification number (did): this is a 16 bit value assigned to the gmch graphic device integrated graphics device registers (d2:f0) (intel? 82915g/82915gv/82915GL/ 82910gl gmch only) r 176 datasheet 9.1.3 pcicmd2?pci command (d2:f0) pci device: 2 address offset: 04h default value: 0000h access: ro, r/w size: 16 bits this 16-bit register provides ba sic control over the igd?s ability to respond to pci cycles. the pcicmd register in the igd disables the igd pci compliant master accesses to main memory. bit access & default description 15:11 reserved 10 r/w 0b interrupt disable: this bit disables the devic e from asserting intx#. 0 = enable the assertion of this device?s intx# signal. 1 = disable the assertion of this dev ice?s intx# signal. do_intx messages will not be sent to the dmi. 9 ro 0b fast back-to-back (fb2b) : not implemented. hardwired to 0. 8 ro 0b serr enable (serre): not implemented. hardwired to 0. 7 ro 0b address/data stepping enable (adstep): not implemented. hardwired to 0. 6 ro 0b parity error enable (perre): not implemented. hardwired to 0. since the igd belongs to the category of devices that does not corrupt programs or data in system memory or hard drives, the igd i gnores any parity error that it detects and continues with normal operation. 5 ro 0b video palette snooping (vps): this bit is hardwired to 0 to disable snooping. 4 ro 0b memory write and invalidate enable (mwie): hardwired to 0. the igd does not support memory write and invalidate commands. 3 ro 0b special cycle enable (sce): this bit is hardwired to 0. the igd ignores special cycles. 2 r/w 0b bus master enable (bme): 0 = disable igd bus mastering. 1 = enable the igd to function as a pci compliant master. 1 r/w 0b memory access enable (mae) : this bit controls the igd?s response to memory space accesses. 0 = disable. 1 = enable. 0 r/w 0 b i/o access enable (ioae): this bit controls the ig d?s response to i/o space accesses. 0 = disable. 1 = enable. integrated graphics device registers (d2:f0) (intel? 82915g/82915gv/82915GL/ 82910gl gmch only) r datasheet 177 9.1.4 pcists2?pci status (d2:f0) pci device: 2 address offset: 06h default value: 0090h access: ro size: 16 bits pcists is a 16-bit status register that reports the occurrence of a pci compliant master abort and pci compliant target abort. pcis ts also indicates the devsel# tim ing that has been set by the igd. bit access & default description 15 ro 0b detected parity error (dpe): since the igd does not detect parity; this bit is always hardwired to 0. 14 ro 0b signaled system error (sse): the igd never asserts serr#, therefore this bit is hardwired to 0. 13 ro 0b received master abort status (rmas): the igd never gets a master abort, therefore, this bit is hardwired to 0. 12 ro 0b received target abort status (rtas): the igd never gets a target abort, therefore this bit is hardwired to 0. 11 ro 0b signaled target abort status (stas): hardwired to 0. the igd does not use target abort semantics. 10:9 ro 00b devsel timing (devt): n/a. these bits are hardwired to 00. 8 ro 0b master data parity error detected (dpd): since parity error response is hardwired to disabled (and the igd does not do any parity detection), this bit is hardwired to 0. 7 ro 1b fast back-to-back (fb2b): hardwired to 1. the igd accepts fast back-to-back when the transactions are not to the same agent. 6 ro 0b user defined format (udf). hardwired to 0. 5 ro 0b 66 mhz pci capable (66c). n/a; hardwired to 0. 4 ro 1b capability list (clist): this bit is set to 1 to indicate that the register at 34h provides an offset into the function? s pci configuration space containing a pointer to the location of the first item in the list. 3 ro 0b interrupt status: this bit reflects the state of t he interrupt in the device. only when the interrupt disable bit in the co mmand register is a 0 and this interrupt status bit is a 1, will the devices intx # signal be asserted. setting the interrupt disable bit to a 1 has no effect on the state of this bit. 2:0 reserved integrated graphics device registers (d2:f0) (intel? 82915g/82915gv/82915GL/ 82910gl gmch only) r 178 datasheet 9.1.5 rid2?revision identification (d2:f0) pci device: 2 address offset: 08h default value: see bit description access: ro size: 8 bits this register contains the revision number for device 2 functions 0 and 1 bit access & default description 7:0 ro 00h revision identification number (rid): this field indicates the number of times that this device in this component has been ?stepped? through the manufacturing process. refer to the intel ? 82915g/82915p/82915gv/82910gl express chipset specification update for the value of the revision id register. 9.1.6 cc?class code (d2:f0) pci device: 2 address offset: 09h default value: 030000h access: ro size: 24 bits this register contains the de vice programming interface information related to the sub-class code and base class code definition for the igd. th is register also contai ns the base class code and the function sub-class in relation to the base class code. bit access & default description 23:16 ro 03h base class code (bcc). this is an 8-bit value that indicates the base class code for the gmch. 03h = display controller. 15:8 ro 00h sub-class code (subcc): value will be determined based on device 0 ggc register, bit 1. 00h = vga compatible 80h = non vga 7:0 ro 00 h programming interface (pi) 00h = hardwired as a display controller. integrated graphics device registers (d2:f0) (intel? 82915g/82915gv/82915GL/ 82910gl gmch only) r datasheet 179 9.1.7 cls?cache line size (d2:f0) pci device: 2 address offset: 0ch default value: 00h access: ro size: 8 bits the igd does not support this register as a pci slave. bit access & default description 7:0 ro 00h cache line size (cls): this field is hardwired to 0s. the igd, as a pci compliant master, does not use the memory write and invalidate command and, in general, does not perform operat ions based on cache line size. 9.1.8 mlt2?master latency timer (d2:f0) pci device: 2 address offset: 0dh default value: 00h access: ro size: 8 bits the igd does not support the programmability of the master latency timer because it does not perform bursts. bit access & default description 7:0 ro 00h master latency timer count value: hardwired to 0s. integrated graphics device registers (d2:f0) (intel? 82915g/82915gv/82915GL/ 82910gl gmch only) r 180 datasheet 9.1.9 hdr2?header type (d2:f0) pci device: 2 address offset: 0eh default value: 80h access: ro size: 8 bits this register contains the header type of the igd. bit access & default description 7 ro 1b multi function status (mfunc): this bit indicates if the device is a multi- function device. the value of this register is determined by device 0, offset 54h, deven[4]. if device 0 deven[4] is set, the mfunc bit is also set. 6:0 ro 00h header code (h): this is a 7-bit value that indicates the header code for the igd. this code has the value 00h, indica ting a type 0 configuration space format. 9.1.10 mmadr?memory mapped range address (d2:f0) pci device: 2 address offset: 10h default value: 00000000h access: ro, r/w size: 32 bits this register requests allocation for the igd registers and instruction ports. the allocation is for 512 kb and the base address is defined by bits [31:19]. bit access & default description 31:19 r/w 0000h memory base address: set by the os, these bits correspond to address signals [31:19]. 18:4 ro 0000h address mask: hardwired to 0s to indicate 512 kb address range. 3 ro 0b prefetchable memory: hardwired to 0 to prevent prefetching. 2:1 ro 00b memory type: hardwired to 0s to indicate 32-bit address. 0 ro 0b memory / io space: hardwired to 0 to indicate memory space. integrated graphics device registers (d2:f0) (intel? 82915g/82915gv/82915GL/ 82910gl gmch only) r datasheet 181 9.1.11 iobar?i/o base address (d2:f0) pci device: 2 address offset: 14h default value: 00000001h access: ro, r/w size: 32 bits this register provides the base offset of the i/o registers within device 2. bits 15:3 are programmable allowing the i/o base to be located anywhere in 16 bit i/o address space. bits 2:1 are fixed and return 0s; bit 0 is hardwired to a 1 indicating that 8 bytes of i/o space are decoded. access to the 8bs of i/o space is allowed in pm state d0 when io enable (pcicmd bit 0) set. access is disallowed in pm states d1?d3 or if io enable is clear or if device 2 is turned off. note that access to this i/o bar is independent of vga functionality with in device 2. also note that this mechanism in available only through function 0 of device 2 and is not duplicated in function 1. if accesses to this i/o bar are allowed, the gmch claims all 8, 16, or 32 bit i/o cycles from the processor that falls within the 8b claimed. bit access & default description 31:16 reserved 15:3 r/w 0000h io base address: set by the os, these bits correspond to address signals [15:3]. 2:1 ro 00b memory type: hardwired to 0s to indicate 32-bit address. 0 ro 1b memory / i/o space: hardwired to 1 to indicate i/o space. integrated graphics device registers (d2:f0) (intel? 82915g/82915gv/82915GL/ 82910gl gmch only) r 182 datasheet 9.1.12 gmadr?graphics memory range address (d2:f0) pci device: 2 address offset: 18h default value: 00000008h access: ro, r/w/l size: 16 bits igd graphics memory base address is specified in this register. bit access & default description 31:28 r/w 0h memory base address: set by the os, these bits correspond to address signals [31:28]. 27 r/w/l 0b 256-mb address mask: this bit is either part of the memory base address (r/w) or part of the address mask (ro), depending on the value of msac[1]. see msac (dev 2, func 0, offset 62) for details. 26:4 ro 000000h address mask: hardwired to 0s to indicate at least 128-mb address range 3 ro 1b prefetchable memory: hardwired to 1 to enable prefetching 2:1 ro 00b memory type: hardwired to 0 to indicate 32-bit address. 0 ro 0b memory/io space: hardwired to 0 to indicate memory space. integrated graphics device registers (d2:f0) (intel? 82915g/82915gv/82915GL/ 82910gl gmch only) r datasheet 183 9.1.13 gttadr?graphics translation table range address (d2:f0) pci device: 2 address offset: 1ch default value: 00000000h access: ro, r/w size: 32 bits this register requests allocation for graphics translation table range. the allocation is for 256 kb and the base address is defined by bits [31:18]. bit access & default description 31:18 r/w 0000h memory base address: set by the os, these bits correspond to address signals [31:18]. 17:4 ro 0000h address mask: hardwired to 0s to indicate 256-kb address range. 3 ro 0b prefetchable memory: hardwired to 0 to prevent prefetching. 2:1 ro 00b memory type: hardwired to 0s to indicate 32-bit address. 0 ro 0b memory/io space: hardwired to 0 to indicate memory space. 9.1.14 svid2?subsystem vendor identification (d2:f0) pci device: 2 address offset: 2ch default value: 0000h access: r/wo size: 16 bits bit access & default description 15:0 r/wo 0000h subsystem vendor id. this value is used to identify the vendor of the subsystem. this register should be pr ogrammed by bios during boot-up. once written, this register becomes read-only . this register can only be cleared by a reset. integrated graphics device registers (d2:f0) (intel? 82915g/82915gv/82915GL/ 82910gl gmch only) r 184 datasheet 9.1.15 sid2?subsystem identification (d2:f0) pci device: 2 address offset: 2eh default value: 0000h access: r/wo size: 16 bits bit access & default description 15:0 r/wo 0000h subsystem identification: this value is used to ident ify a particular subsystem. this field should be programmed by bios during boot-up. once written, this register becomes read only. this r egister can only be cleared by a reset. 9.1.16 romadr?video bios rom base address (d2:f0) pci device: 2 address offset: 30h default value: 00000000h access: ro size: 32 bits the igd does not use a separate bios rom; therefore, this register is hardwired to 0s. bit access & default description 31:18 ro 0000h rom base address: hardwired to 0s. 17:11 ro 00h address mask: hardwired to 0s to indicate 256-kb address range. 10:1 reserved 0 ro 0b rom bios enable: 0 = rom not accessible. integrated graphics device registers (d2:f0) (intel? 82915g/82915gv/82915GL/ 82910gl gmch only) r datasheet 185 9.1.17 cappoint?capabilities pointer (d2:f0) pci device: 2 address offset: 34h default value: d0h access: ro size: 8 bits bit access & default description 7:0 ro d0h capabilities pointer value: this field contains an offs et into the function?s pci configuration space for t he first item in the new capabilities linked list; the power management capabilities id registers at address d0h. 9.1.18 intrline?interrupt line (d2:f0) pci device: 2 address offset: 3ch default value: 00h access: r/w size: 8 bits bit access & default description 7:0 r/w 00h interrupt connection: this field is used to comm unicate interrupt line routing information. post software writes the routi ng information into this register as it initializes and configures the system. the value in this register indicates which input of the system interrupt controller t hat the device?s interrupt pin is connected to. 9.1.19 intrpin?interrupt pin (d2:f0) pci device: 2 address offset: 3dh default value: 01h access: ro size: 8 bits bit access & default description 7:0 ro 01h interrupt pin: as a device that only has interrupts associated with a single function, the igd specifies inta# as its interrupt pin. 01h = inta#. integrated graphics device registers (d2:f0) (intel? 82915g/82915gv/82915GL/ 82910gl gmch only) r 186 datasheet 9.1.20 mingnt?minimum grant (d2:f0) pci device: 2 address offset: 3eh default value: 00h access: ro size: 8 bits bit access & default description 7:0 ro 00h minimum grant value: the igd does not burst as a pci compliant master. 9.1.21 maxlat?maximum latency (d2:f0) pci device: 2 address offset: 3fh default value: 00h access: ro size: 8 bits bit access & default description 7:0 ro 00h maximum latency value: the igd has no specific requirements for how often it needs to access the pci bus. 9.1.22 mcapptr?mirror of dev0 capability pointer (d2:f0) (mirrored_d0_34) pci device: 2 function: 0 address offset: 44h size: 8 bits this register is a read-only copy of device 0 , offset 34h register. 9.1.23 mcapid?mirror of dev0 capability identification (d2:f0) (mirrored_d0_e0) pci device: 2 function: 0 address offset: 48h size: 72 bits this register is a read-only copy of device 0 , offset e0h register. integrated graphics device registers (d2:f0) (intel? 82915g/82915gv/82915GL/ 82910gl gmch only) r datasheet 187 9.1.24 mggc?mirror of dev0 gmch graphics control (d2:f0) (mirrored_d0_52) pci device: 2 function: 0 address offset: 52h size: 16 bits this register is a read-only copy of device 0 , offset 52h register. 9.1.25 mdevendev0f0?mirror of dev0 device enable (d2:f0) (mirrored_d0_54) pci device: 2 function: 0 address offset: 54h size: 32 bits this register is a read-only copy of device 0 , offset 54h register. 9.1.26 bsm?base of stolen memory (d2:f0) pci device: 2 address offset: 5ch default value: 07800000h access: ro size: 32 bits graphics stolen memory and tseg are with in dram space defined under tolud. from the top of low used dram, gmch claims 1 to 64 mbs of dram for internal graphics, if enabled. bit access & default description 31:20 ro 078h base of stolen memory (bsm): this register contains bits 31:20 of the base address of stolen dram memory. the host interface determines the base of graphics stolen memory by subtracting the graphics stolen memory size from tolud. see device 0 tolud for more explanation. 19:0 reserved integrated graphics device registers (d2:f0) (intel? 82915g/82915gv/82915GL/ 82910gl gmch only) r 188 datasheet 9.1.27 msac?multi size aperture control (d2:f0) pci device: 2 address offset: 62h default value: 00h access: r/w size: 8 bits this register determines the size of the graphics memory aperture in function 0 and in the trusted space. by default, the aperture size is 256 mb (bit 27 read only). if bit 1 is set to a 1, then the aperture size is limited to 128 mb. only the syst em bios will write this register based on pre- boot address allocation efforts, but the graphics may read this register to determine the correct aperture size. system bios needs to save this value on boot so that it can reset it correctly during s3 resume. bit access & default description 7:4 r/w 0h scratch bits only. these bits have no physical effect on hardware. 3:2 reserved 1 r/w 0b 256-mb aperture disable 0 = bit 27 of gmadr and the equivalent tr usted memory aperture is read-only, allowing 256 mb of address space to be mapped. 1 = bit 27 of gmadr and the equivalent trusted memory aperture is read-write, limiting the address space to 128 mb. 0 reserved 9.1.28 pmcapid?power management capabilities id (d2:f0) pci device: 2 address offset: d0h default value: 0001h access: ro size: 16 bits bit access & default description 15:8 ro 00h next_ptr: this field contains a pointer to nex t item in capabilities list. this is the final capability in the list and must be set to 00h. 7:0 ro 01h cap_id: sig defines this id is 01h for power management. integrated graphics device registers (d2:f0) (intel? 82915g/82915gv/82915GL/ 82910gl gmch only) r datasheet 189 9.1.29 pmcap?power management capabilities (d2:f0) pci device: 2 address offset: d2h default value: 0022h access: ro size: 16 bits bit access & default description 15:11 ro 00h pme support: this field indicates the power states in which the igd may assert pme#. hardwired to 0 to indicate that the igd does not assert the pme# signal. 10 ro 0b d2: the d2 power management state is not supported. this bit is hardwired to 0. 9 ro 0b d1: hardwired to 0 to indicate that the d1 power management state is not supported. 8:6 reserved 5 ro 1b device specific initialization (dsi): hardwired to 1 to indicate that special initialization of the igd is required before generic class device driver is to use it. 4 ro 0b auxiliary power source: hardwired to 0. 3 ro 0b pme clock: hardwired to 0 to indicate igd does not support pme# generation. 2:0 ro 010b version: hardwired to 010b to indicate that there are 4 bytes of power management registers implemented and that this device complies with revision 1.1 of the pci power management interface specification integrated graphics device registers (d2:f0) (intel? 82915g/82915gv/82915GL/ 82910gl gmch only) r 190 datasheet 9.1.30 pmcs?power management control/status (d2:f0) pci device: 2 address offset: d4h default value: 0000h access: ro, r/w size: 16 bits bit access & default description 15 ro 0b pme_status: this bit is 0 to indicate that igd does not support pme# generation from d3 (cold). 14:9 reserved 8 ro 0b pme_en: this bit is 0 to indicate that pme# assertion from d3 (cold) is disabled. 7:2 reserved 1:0 r/w 00b power state: this field indicates the current power state of the igd and can be used to set the igd into a new power state. if software attempts to write an unsupported state to this field, the write operation must complete normally on the bus, but the data is discarded and no state change occurs. on a transition from d3 to d0 the graphics controller is optionally reset to initial values. behavior of the graphics controller in supported states is detailed in the power management section. 00 = d0 (default) 01 = d1 (not supported) 10 = d2 (not supported) 11 = d3 integrated graphics device registers (d2:f0) (intel? 82915g/82915gv/82915GL/ 82910gl gmch only) r datasheet 191 9.1.31 swsmi?software smi (d2:f0) pci device: 2 address offset: e0h default value: 0000h access: r/w size: 16 bits as long as there is the potential that dvo port legacy drivers exist that expect this register at this address, dev2, f0, address e0h?e1h must be reserved for this register. bit access & default description 15:8 r/w 00h sw scratch bits 7:1 r/w 00h software flag: this field is used to indicate caller and smi function desired, as well as return result. 0 r/w 0b gmch software smi event: when set, this bit will trigger an smi. software must write a 0 to clear this bit 9.1.32 asle?system display event register (d2:f0) pci device: 2 address offset: e4h default value: 00000000h access: r/w size: 32 bits byte, word, or double word pci configur ation cycles can access this register. bit access & default description 31:8 r/w 00h asle scratch trigger 3: when written, this scratch byte triggers an interrupt when ier bit 0 is enabled and imr bit 0 is unmasked. if written as part of a 16- bit or 32-bit write, only one interrupt is generated in common. 23:16 r/w 00h asle scratch trigger 2: when written, this scratch byte triggers an interrupt when ier bit 0 is enabled and imr bit 0 is unmasked. if written as part of a 16- bit or 32-bit write, only one interrupt is generated in common. 15:8 r/w 00h asle scratch trigger 1: when written, this scratch byte triggers an interrupt when ier bit 0 is enabled and imr bit 0 is unmasked. if written as part of a 16- bit or 32-bit write, only one interrupt is generated in common. 7:0 r/w 00h asle scratch trigger 0: when written, this scratch byte triggers an interrupt when ier bit 0 is enabled and imr bit 0 is unmasked. if written as part of a 16- bit or 32-bit write, only one interrupt is generated in common. integrated graphics device registers (d2:f0) (intel? 82915g/82915gv/82915GL/ 82910gl gmch only) r 192 datasheet 9.1.33 asls?asl storage (d2:f0) pci device: 2 address offset: fch default value: 00000000h access: r/w size: 32 bits this sw scratch register only needs to be read/w rite accessible. the exact bit register usage must be worked out in common between system bios and driver software, but storage for switching/indicating up to 6 devi ces is possible with this amount. for each device, the asl control method requires two bits for _dod (bios detectable yes or no, vga/non vga); one bit for _dgs (enable/disable requested) and two bits for _dcs (enabled now/disabled now, connected or not). bit access & default description 31:0 r/w 00000000 h rw according to a software contro lled usage to support device switching device 2 function 1 (d2:f1) configuration registers (intel? 82915g/82915gv/82915GL/ 82910gl only) r datasheet 193 10 device 2 function 1 (d2:f1) configuration registers (intel ? 82915g/82915gv/82915GL/ 82910gl only) table 10-1. device 2 function 1 register address map summary address offset register symbol register name default value access 00?01h vid2 vendor identification 8086h ro 02?03h did2 device identification 2780h ro 04?05h pcicmd2 pci command 0000h ro, r/w 06?07h pcists2 pci status 0090h ro 08h rid2 revision identification see register description ro 09?0bh cc class code register 03800h ro 0ch cls cache line size 00h ro 0dh mlt2 master latency timer 00h ro 0eh hdr2 header type register 80h ro 0fh ? reserved ? ? 10?13h mmadr memory mapped range address 00000000h ro, r/w 14?2bh ? reserved ? ? 2c?2dh svid2 subsystem vendor identification 0000h r/wo 2e?2fh sid2 subsystem identification 0000h r/wo 30?33h romadr video bios rom base address 00000000h ro 34h cappoint capabilities pointer d0h ro 35?3dh ? reserved ? ? 3eh mingnt minimum grant register 00h ro 3fh maxlat maximum latency 00h ro 40?43h ? reserved ? ? 44h mcapptr mirror of dev0 capability pointer 45?47h ? reserved ? ? device 2 function 1 (d2:f1) configuration registers (intel? 82915g/82915gv/82915GL/ 82910gl only) r 194 datasheet address offset register symbol register name default value access 48?50h mcapid mirror of dev0 capability identification 51h ? reserved ? ? 52?53h mggc mirror of dev0 gmch graphics control 54?57h mdevendev0f0 mirror of dev0 device enable 58?5bh ? reserved ? ? 5c?5fh bsm base of stolen memory register 07800000h ro 60?cfh ? reserved 0000h ? d0?d1h pmcapid power management capabilities id 0001h ro d2?d3h pmcap power management capabilities 0022h ro d4?d5h pmcs power management control/status 0000h ro, r/w d6?dfh ? reserved ? ? e0?e1h swsmi software smi 0000h r/w e2?fbh ? reserved ? ? fc?ffh asls asl storage 00000000h r/w 10.1 device 2 function 1 configuration register details (d2:f1) 10.1.1 vid2?vendor identification (d2:f1) pci device: 2 address offset: 00h default value: 8086h access: ro size: 16 bits this register is a copy of device 2, function 0. it has the same read, write attributes as d2:f0. it is implemented as common hardware with two access addresses. 10.1.2 did2?device identification (d2:f1) pci device: 2 address offset: 02h default value: 2782h access: ro size: 16 bits this register is unique in device 2, function 1 (t he device 2, function 0 did is separate). this difference in device id is necessary for allowing distinct plug and play enumeration of function 1 when both function 0 and function 1 have the same class code. device 2 function 1 (d2:f1) configuration registers (intel? 82915g/82915gv/82915GL/ 82910gl only) r datasheet 195 10.1.3 pcicmd2?pci command (d2:f1) pci device: 2 address offset: 04h default value: 0000h access: ro, r/w size: 16 bits this 16-bit register provides ba sic control over the igd?s ability to respond to pci cycles. the pcicmd register in the igd disables the igd pci compliant master accesses to main memory. bit access & default description 15:10 reserved 9 ro 0b fast back-to-back (fb2b) : not implemented. hardwired to 0. 8 ro 0b serr enable (serre): not implemented. hardwired to 0. 7 ro 0b address/data stepping enable (adstep): not implemented. hardwired to 0. 6 ro 0b parity error enable (perre): not implemented. hardwired to 0. since the igd belongs to the category of devices that does not corrupt programs or data in system memory or hard drives, the igd i gnores any parity error that it detects and continues with normal operation. 5 ro 0b vga palette snoop enable (vgasnoop): this bit is hardwired to 0 to disable snooping. 4 ro 0b memory write and invalidate enable (mwie): hardwired to 0. the igd does not support memory write and invalidate commands. 3 ro 0b special cycle enable (sce): this bit is hardwired to 0. the igd ignores special cycles. 2 r/w 0b bus master enable (bme): 0 = disable 1 = enable the igd to function as a pci compliant master. 1 r/w 0b memory access enable (mae): this bit controls the igd?s response to memory space accesses. 0 = disable. 1 = enable. 0 r/w 0b i/o access enable (ioae): this bit controls the ig d?s response to i/o space accesses. 0 = disable. 1 = enable. device 2 function 1 (d2:f1) configuration registers (intel? 82915g/82915gv/82915GL/ 82910gl only) r 196 datasheet 10.1.4 pcists2?pci status (d2:f1) pci device: 2 address offset: 06h default value: 0090h access: ro size: 16 bits pcists is a 16-bit status register that reports the occurrence of a pci compliant master abort and pci compliant target abort. pcis ts also indicates the devsel# tim ing that has been set by the igd. bit access & default description 15 ro 0b detected parity error (dpe): since the igd does not detect parity; this bit is always hardwired to 0. 14 ro 0b signaled system error (sse): the igd never asserts serr#; therefore, this bit is hardwired to 0. 13 ro 0b received master abort status (rmas): the igd never gets a master abort, therefore this bit is hardwired to 0. 12 ro 0b received target abort status (rtas): the igd never gets a target abort, therefore this bit is hardwired to 0. 11 ro 0b signaled target abort status (stas): hardwired to 0. the igd does not use target abort semantics. 10:9 ro 00b devsel timing (devt): these bits are hardwired to 00. 8 ro 0b master data parity error detected (dpd): since parity error response is hardwired to disabled (and the igd does not do any parity detection), this bit is hardwired to 0 . 7 ro 1b fast back-to-back (fb2b): hardwired to 1. the igd accepts fast back-to-back when the transactions are not to the same agent. 6 ro 0b user defined format (udf). hardwired to 0. 5 ro 0b 66 mhz pci capable (66c). hardwired to 0. 4 ro 1b capability list (clist): this bit is set to 1 to indicate that the register at 34h provides an offset into the function? s pci configuration space containing a pointer to the location of the first item in the list. 3 ro 0b interrupt status: hardwired to 0. 2:0 reserved device 2 function 1 (d2:f1) configuration registers (intel? 82915g/82915gv/82915GL/ 82910gl only) r datasheet 197 10.1.5 rid2?revision identification (d2:f1) pci device: 2 address offset: 08h default value: see description below access: ro size: 8 bits this register is a copy of device 2, function 0. it has the same read, write attributes as d2:f0. it is implemented as common hardware with two access addresses. 10.1.6 cc?class code register (d2:f1) pci device: 2 address offset: 09h default value: 038000h access: ro size: 24 bits this register contains the de vice programming interface information related to the sub-class code and base class code definition for the igd. th is register also contai ns the base class code and the function sub-class in relation to the base class code. bit access & default description 23:16 ro 03h base class code (bcc): this is an 8-bit value that indicates the base class code for the gmch. 03h = display controller. 15:8 ro 80h sub-class code (subcc) 80h = non vga 7:0 ro 00h programming interface (pi) 00h = hardwired as a display controller. 10.1.7 cls?cache line size (d2:f1) pci device: 2 address offset: 0ch default value: 00h access: ro size: 8 bits this register is a copy of device 2, function 0. it has the same read, write attributes as d2:f0. it is implemented as common hardware with two access addresses. device 2 function 1 (d2:f1) configuration registers (intel? 82915g/82915gv/82915GL/ 82910gl only) r 198 datasheet 10.1.8 mlt2?master latency timer (d2:f1) pci device: 2 address offset: 0dh default value: 00h access: ro size: 8 bits this register is a copy of device 2, function 0. it has the same read, write attributes as d2:f0. it is implemented as common hardware with two access addresses. 10.1.9 hdr2?header type register (d2:f1) pci device: 2 address offset: 0eh default value: 80h access: ro size: 8 bits this register is a copy of device 2, function 0. it has the same read, write attributes as d2:f0. it is implemented as common hardware with two access addresses. 10.1.10 mmadr?memory mapped range address (d2:f1) pci device: 2 address offset: 10h default value: 00000000h access: ro, r/w size: 32 bits this register requests allocation for the igd registers and instruction ports. the allocation is for 512 kb and the base address is defined by bits [31:19]. bit access & default description 31:19 r/w 0000h memory base address: set by the os, these bits correspond to address signals [31:19]. 18:4 ro 0000h address mask: hardwired to 0s to indicate 512-kb address range. 3 ro 0b prefetchable memory: hardwired to 0 to prevent prefetching. 2:1 ro 00b memory type: hardwired to 0s to indicate 32-bit address. 0 ro 0b memory / io space: hardwired to 0 to indicate memory space. device 2 function 1 (d2:f1) configuration registers (intel? 82915g/82915gv/82915GL/ 82910gl only) r datasheet 199 10.1.11 svid2?subsystem vendor identification (d2:f1) pci device: 2 address offset: 2ch default value: 0000h access: r/wo size: 16 bits this register is a copy of device 2, function 0. it has the same read, write attributes as d2:f0. it is implemented as common hardware with two access addresses. 10.1.12 sid2?subsystem identification (d2:f1) pci device: 2 address offset: 2eh default value: 0000h access: r/wo size: 16 bits this register is a read only copy of device 2, function 0. 10.1.13 romadr?video bios rom base address (d2:f1) pci device: 2 address offset: 30h default value: 00000000h access: ro size: 32 bits this register is a copy of device 2, function 0. it has the same read, write attributes as d2:f0. it is implemented as common hardware with two access addresses. 10.1.14 cappoint?capabilities pointer (d2:f1) pci device: 2 address offset: 34h default value: d0h access: ro size: 8 bits this register is a copy of device 2, function 0. it has the same read, write attributes as d2:f0. it is implemented as common hardware with two access addresses. device 2 function 1 (d2:f1) configuration registers (intel? 82915g/82915gv/82915GL/ 82910gl only) r 200 datasheet 10.1.15 mingnt?minimum grant register (d2:f1) pci device: 2 address offset: 3eh default value: 00h access: ro size: 8 bits this register is a copy of device 2, function 0. it has the same read, write attributes as d2:f0. it is implemented as common hardware with two access addresses. 10.1.16 maxlat?maximum latency (d2:f1) pci device: 2 address offset: 3fh default value: 00h access: ro size: 8 bits this register is a copy of device 2, function 0. it has the same read, write attributes as d2:f0. it is implemented as common hardware with two access addresses. 10.1.17 mcapptr?mirror of dev0 capability pointer (d2:f1) (mirrored_d0_34) pci device: 2 function: 1 address offset: 44h size: 8 bits this register is a read only copy of device 0, offset 34h register. 10.1.18 mcapid?mirror of dev0 capability identification (d2:f1) (mirrored_d0_e0) pci device: 2 function: 1 address offset: 48h size: 72 bits this register is a read-only copy of device 0, offset e0h register. 10.1.19 mggc?mirror of dev0 gmch graphics control (d2:f1) (mirrored_d0_52) pci device: 2 address offset: 52h size: 16 bits this register is a read only copy of device 0, offset 52h register. device 2 function 1 (d2:f1) configuration registers (intel? 82915g/82915gv/82915GL/ 82910gl only) r datasheet 201 10.1.20 mdevendev0f0?mirror of dev0 device enable (d2:f1) (mirrored_d0_54) pci device: 2 function: 1 address offset: 54h size: 32 bits this register is a read only copy of device 0, offset 54h register. 10.1.21 bsm?base of stolen memory register (d2:f1) pci device: 2 address offset: 5ch default value: 07800000h access: ro size: 32 bits this register is a copy of device 2, function 0. it has the same read, write attributes as d2:f0. it is implemented as common hardware with two access addresses. 10.1.22 pmcapid?power management capabilities id (d2:f1) pci device: 2 address offset: d0h default value: 0001h access: ro size: 16 bits this register is a copy of device 2, function 0. it has the same read, write attributes as d2:f0. it is implemented as common hardware with two access addresses. 10.1.23 pmcap?power management capabilities (d2:f1) pci device: 2 address offset: d2h default value: 0022h access: ro size: 16 bits this register is a copy of device 2, function 0. it has the same read, write attributes as d2:f0. it is implemented as common hardware with two access addresses. device 2 function 1 (d2:f1) configuration registers (intel? 82915g/82915gv/82915GL/ 82910gl only) r 202 datasheet 10.1.24 pmcs?power management control/status (d2:f1) pci device: 2 address offset: d4h default value: 0000h access: ro, r/w size: 16 bits bit access & default description 15 ro 0 b pme_status: this bit is 0 to indicate that igd does not support pme# generation from d3 (cold). 14:9 reserved 8 ro 0 b pme_en: this bit is 0 to indicate that pme# assertion from d3 (cold) is disabled. 7:2 reserved 1:0 r/w 00 b power state: this field indicates the current power state of the igd and can be used to set the igd into a new power state. if software attempts to write an unsupported state to this field, write operation must complete normally on the bus, but the data is discarded and no state change occurs. on a transition from d3 to d0 the graphics controller is optionally reset to initial values. behavior of the graphics controller in supported states is detailed in the power management section. 00 = d0 (default) 01 = d1 (not supported) 10 = d2 (not supported) 11 = d3 10.1.25 swsmi?software smi (d2:f1) pci device: 2 address offset: e0h default value: 0000h access: r/w size: 16 bits this register is a copy of device 2, function 0. it has the same read, write attributes as d2:f0. it is implemented as common hardware with two access addresses. device 2 function 1 (d2:f1) configuration registers (intel? 82915g/82915gv/82915GL/ 82910gl only) r datasheet 203 10.1.26 asls?asl storage (d2:f1) pci device: 2 address offset: fch default value: 00000000h access: r/w size: 32 bits this software scratch register onl y needs to be read/write accessibl e. the exact bit register usage must be worked out in common between system bios and driver software, but storage for switching/indicating up to 6 devi ces is possible with this amount. for each device, the asl control method with require two bits for _dod (bios detectable yes or no, vga/nonvga), one bit for _dgs (enable/disable requested), and two bits for _dcs (enabled now/disabled now, connected or not). bit access & default description 31:0 r/w 00000000 h r/w according to a software contro lled usage to support device switching device 2 function 1 (d2:f1) configuration registers (intel? 82915g/82915gv/82915GL/ 82910gl only) r 204 datasheet 10.2 device 2 ? pci i/o registers the following are not pci configurations registers; they are i/o registers. 10.2.1 mmio_index?mmio address register i/o address: iobar + 0h size: 32 bits mmio_index : a 32 bit i/o write to this port loads the offset of the memory-mapped i/o (mmio) register that needs to be accessed. an i/o read returns the current value of this register. an 8/16-bit i/o write to this register is completed by the gmch but does not update this register. this mechanism to access internal graphics mmi o registers must not be used to access vga i/o registers that are mapped through the mmio sp ace. vga registers must be accessed directly through the dedicated vga io ports. bit access & default description 31:2 r/w 00000000 h register offset : this field selects any one of the dword registers within the mmio register space of device 2. 1:0 reserved 10.2.2 mmio_data?mmio data register i/o address: iobar + 4h size: 32 bits mmio_data: a 32 bit i/o write to this port is re-directed to the mmio register pointed to by the mmio-index register. a 32 bit i/o read to this port is re-directed to the mmio register pointed to by the mmio-index register. 8 or 16 bit i/o writes are completed by the gmch and may have un-intended side effects; hence, they must not be used to access the data port. 8 or 16 bit i/o reads are completed normally. bit access & default description 31:0 r/w 00000000 h mmio data window system address map r datasheet 205 11 system address map the (g)mch supports 4 gb of addressable me mory space (see figure 11-1) and 64 kb+3 bytes of addressable i/o space. a programmable me mory address space under the 1-mb region is divided into regions that can be individually c ontrolled with programmable attributes such as disable, read/write, write only, or read only. this section focuses on how the memory space is partitioned and what the separate memory regions are used for. i/o address space has simpler mapping and is explained near the end of this section. note: address mapping information for the integrated graphics device applies to the 82915g/82915gv/82915GL/82910gl gmch only. the 82915p/82915pl mch does not have an igd. note: address mapping information for the pci express device applies to the 82915g/82915p/82915pl (g)mch only. the 82915gv/82915GL/82910gl gmch does not support pci express. addressing of memory ranges larger than 4 gb is not supported. the hreq[4:3] fsb pins are decoded to determine whether th e access is above or below 4 gb. the (g)mch does not support the pci dual address cycle (dac) mechanism, pci express 64-bit prefetchable memory transactions, or any other addressing mechanism that allows addressing of greater than 4 gb on either the dmi or pci express interface. the (g)mch does not limit system memory space in hardware. ther e is no hardware lock to stop someone from inserting more memory than is addressable. in the following sections, it is assumed that all of the compatibility memory ranges reside on the dmi. the exception to this rule is vga ranges that may be mapped to pci express, dmi, or to the internal graphics device (igd) . in the absence of more specifi c references, cycle descriptions referencing pci should be interpreted as the dmi/ pci, while cycle descriptions referencing pci express or igd are related to the pci express bus or the internal graphics device respectively. the (g)mch does not remap apic or any ot her memory spaces above tolud (top of low usable dram). the tolud register is set to the appropriate value by bios. the address map includes a number of programmable ranges: ? device 0 ? epbar ? egress port registers. necessary fo r setting up vc1 as an isochronous channel using time based weighted round robin arbitration. (4-kb window) ? mchbar ? memory mapped range for intern al (g)mch registers. for example, memory buffer register controls. (16-kb window) ? pciexbar ? flat memory -mapped address space to access device configuration registers. this mechanism can be used to access pci configuration space (0h?ffh) and extended configuration space (100h?fffh) for pci express devices. this enhanced configuration access mechanism is defined in the pci express specification. (256-mb window) ? dmibar ?this window is used to access registers associat ed with the (g)mch/ich6 (dmi) register memory range. (4-kb window) system address map r 206 datasheet ? ifpbar ? any write to this window will tri gger a flush of the (g)mch?s global write buffer to let software guarantee coherenc y between writes from an isochronous agent and writes from the processor (4-kb window). ? ggc ? 82915g/82915gv/82910gl gmch graphics control register. used to select the amount of main memory that is pre-allocated to support the internal graphics device in vga (non-linear) and native (linear) modes (0?64-mb options). ? device 1: function 0: ? mbase1/mlimit1 ? pci express port non- prefetchable memory access window. ? pmbase1/pmlimit1 ? pci express por t prefetchable memory access window. ? iobase1/iolimit1 ? pci express port i/o access window. ? device 2: function 0 (82915g/82915gv/82915GL/82910gl gmch only) ? mmadr ? igd registers and internal graphics instruction port. (512-kb window) ? iobar ? i/o access window for the gmch in ternal graphics. through this window address/data register pair, using i/o semantic s, the igd and internal graphics instruction port registers can be accessed. note, this allows accessing the same registers as mmadr. in addition, the iobar can be used to issue writes to the gttadr table. ? gmadr ? internal graphics translation window. (256-mb window) ? gttadr ? internal graphics translation table location. (256-kb window). note that the pgtbl_ctl register (mmio 2020) indicates the physical address base which is 4 kb aligned. ? device 2: function 1 (82915g/82915gv/82915GL/82910gl gmch only) ? mmadr ? function 1 igd registers and internal graphics instruction port. (512-kb window) the rules for the above programmable ranges are: ? all of these ranges must be unique and non- overlapping. it is the bios or system designer?s responsibility to limit memory population so that adequate pc i, pci express, high bios, pci express memory mapped space, a nd apic memory space can be allocated. ? in the case of overlapping ranges with memory, the memory decode will be given priority. ? there are no hardware interlocks to prevent problems in the case of overlapping ranges. ? accesses to overlapped ranges may produce indeterminate results. ? the only peer-to-peer cycles allowed below the top of memory (register tolud) are dmi to pci express vga range writes. note that peer to peer cycles to the internal graphics vga range are not supported. figure 11-1 shows the system memory address map in a simplified form. system address map r datasheet 207 figure 11-1. system address ranges pci memory address range (subtractively decoded to dmi) main memory address range legacy address range 0 1 mb tolud 4 gb device 0 bars (epbar, mchbar, pciexbar, dmibar) device 1 bars (mbase1/ mlimit1, pmbase1/ pmlimit1) device 2 1 bars (mmadr, gmadr, gttadr) device 0 ggc (graphics stolen memory) independently programmable non-overlapping windows notes: 1. device 2 is not on the 82915p/82915pl mch. 2. device 1 is not on the 82915gv/82910gl/82915GL gmch. 11.1 legacy address range this area is divided into the following address regions: ? 0 ? 640 kb: dos area ? 640 ? 768 kb: legacy video buffer area ? 768 ? 896 kb in 16-kb sections (total of 8 sections): expansion area ? 896 ? 960 kb in 16-kb sections (total of 4 sections): extended system bios area ? 960-kb ? 1-mb memory: system bios area system address map r 208 datasheet figure 11-2. microsoft ms-dos* legacy address range expansion area 128kb (16kbx8) 000c_0000h 000d_ffffh 896kb extended system bios (lower) 64kb (16kbx4) 000e_0000h 000e_ffffh 960kb legacy video area (smm memory) 128kb 000a_0000h 000b_ffffh 768kb dos area 0000_0000h 0009_ffffh 640kb system bios (upper) 64kb 000f_0000h 000f_ffffh 1mb 11.1.1 dos range (0h ? 9_ffffh) the dos area is 640 kb (0000_0000h ? 0009_ffffh) in si ze and is always mapped to the main memory controlled by the (g)mch. 11.1.2 legacy video area (a_0000h?b_ffffh) the legacy 128-kb vga memory range, fra me buffer, (000a_0000h ? 000b_ffffh) can be mapped to igd, to pci express, and/or to the dmi. the appropriate mapping is programmable. based on the programming, priority for vga mappi ng is constant. the (g)mch always decodes internally mapped devices first. internal to the 82915g/82915gv/82915GL/82910gl gmch, decode precedence is always given to the igd. the (g)mch always positively decodes internally mapped devices, namely the igd (82915g/82915gv/82915GL/82910gl only) and pci express. subsequent decoding of regions mapped to pci express or the dmi depends on the programming. this region is also the default for smm space. system address map r datasheet 209 compatible smram address range (a_0000h?b_ffffh) when compatible smm space is en abled, smm-mode processor accesse s to this range are routed to physical system dram at 000a 0000h?000b ffffh. non-smm-mode processor accesses to this range are considered to be to the vide o buffer area as described above. pci express and dmi originated cycles to enab led smm space are not allowed and are considered to be to the video buffer area if igd (82915g/82915gv/82915GL/82910gl gmch only) is not enabled as the vga device. pci express and dmi initiated cycl es are attempted as peer cycles, and will master abort on pci if no exte rnal vga device claims them. monochrome adapter (mda) range (b_0000h?b_7fffh) legacy support requires the ability to have a s econd graphics controller (monochrome) in the system. accesses in the standard vga range are forwarded to igd, pci express, or the dmi (depending on the programming of the on-chip registers). since the monochrome adapter may be mapped to any one of these devices, the (g)m ch must decode cycles in the mda range (000b_0000h ? 000b_7fffh) and forward either to igd, pci express, or the dmi. in addition to the memory range b0000h to b7fffh, the (g)mch decodes i/o cycles at 3b4h, 3b5h, 3b8h, 3b9h, 3bah and 3bfh and forwards them to the either igd, pci express, and/or the dmi. 11.1.3 expansion area (c_0000h?d_ffffh) this 128-kb isa expansion region (000c_0000h ? 000d_ffffh) is divided into eight, 16-kb segments. each segment can be assigned one of four read/write states: read only, write only, read/write, or disabled. typically, these blocks are mapped through the (g)mch and are subtractively decoded to isa space. memory that is disabled is not remapped. non-snooped accesses from pci express or dmi to this region are always sent to main memory. table 11-1. expansion area memory segments memory segments attributes comments 0c0000h?0c3fffh w/r add-on bios 0c4000h?0c7fffh w/r add-on bios 0c8000h?0cbfffh w/r add-on bios 0cc000h ?0cffffh w/r add-on bios 0d0000h?0d3fffh w/r add-on bios 0d4000h?0d7fffh w/r add-on bios 0d8000h?0dbfffh w/r add-on bios 0dc000h?0dffffh w/r add-on bios system address map r 210 datasheet 11.1.4 extended system bios area (e_0000h?e_ffffh) this 64-kb area (000e_0000h ? 000e_ffffh) is divi ded into four, 16-kb segments. each segment can be assigned independent read and write attributes so it can be mapped either to main dram or to the dmi. typically, this area is us ed for ram or rom. memory segments that are disabled are not remapped elsewhere. non-snooped accesses from pci express or dmi to this region are always sent to main memory. table 11-2. extended system bios area memory segments memory segments attributes comments 0e0000h?0e3fffh w/r bios extension 0e4000h?0e7fffh w/r bios extension 0e8000h?0ebfffh w/r bios extension 0ec000h?0effffh w/r bios extension 11.1.5 system bios area (f_0000h?f_ffffh) this area is a single, 64-kb segment (000f_0000h ? 000f_ffffh). this segment can be assigned read and write attributes. it is by default (after reset) read/write disabled and cycles are forwarded to the dmi. by programming the read /write attributes, the (g)mch can ?shadow? bios into main memory. when disabled, this segment is not remapped. non-snooped accesses from pci express or dmi to this region are always sent to main memory. table 11-3. system bios area memory segments memory segments attributes comments 0f0000h?0fffffh we re bios area 11.1.6 programmable attribute map (pam) memory area details the 13 sections from 768 kb to 1 mb comprise what is also known as the pam memory area. the (g)mch does not handle iwb (implicit write -back) cycles targeting dmi. since all memory residing on dmi should be set as non-cacheable, there will normally not be iwb cycles targeting dmi. however, dmi becomes the default target for pr ocessor and dmi originated accesses to disabled segments of the pam region. if the mtrrs covering the pam regions are set to wb or rc, it is possible to get iwb cycles targeting dmi. this may occur for dmi-originated cycles to disabled pam regions. warning: for example, assume that a particular pam region is set for ?read disabled? and the mtrr associated with this region is set to wb. a dmi master generates a memory read targeting the pam region. a snoop is generated on the fsb and the result is an iwb. since the pam region is ?read disabled?, the default ta rget for the memory read beco mes dmi. the iwb associated with this cycle will cause the (g)mch to hang. system address map r datasheet 211 11.2 main memory address range (1 mb to tolud) this address range extends from 1 mb to the top of physical memory that is permitted to be accessible by the (g)mch (as progr ammed by in the tolud register). all accesses to addresses within this range will be forwarded by the (g)mch to the main memory unless they fall into the optional tseg, optional isa hole, or optional igd stolen vga memory. the (g)mch provides a maximum main memory address decode space of 4 gb. the (g)mch does not remap apic or pci expr ess memory space. this means that as the amount of physical memory populated in the system reaches 4 gb, th ere will be physical memory that exists, yet non- addressable; therefore, this memory is unusable by the system. the (g)mch does not limit main memory address space in hardware. figure 11-3. main memory address range flash 0h contains programmable windows, ich6/pci ranges. tolud main_mem_addr_g-p_only apic pci memory range 0010_000h igd (1?32 mb, optional) tseg (1 mb / 2 mb / 8 mb, optional) main memory isa hole (optional) main memory dos compatibility memory 00f0_000h 0100_000h 0 mb 1 mb 15 mb 16 mb 4 gb maximum ffff_ffffh 11.2.1 isa hole (15 mb?16 mb) bios can create a hole at 15 mb?16 mb. accesses w ithin this hole are forwarded to the dmi. the range of physical main memory disabled by opening the hole is not remapped to the top of the memory; that physical main memory space is not accessible. this 15 mb?16 mb hole is an optionally enabled isa hole. system address map r 212 datasheet 11.2.2 tseg tseg is optionally 1 mb, 2 mb, or 8 mb in size. tseg is below igd stolen memory, which is at the top of physical memory. smm-mode processor accesses to enabled tseg access the physical dram at the same addr ess. non-processor originated accesses are not allowed to smm space. pci express, dmi, and in ternal graphics originated cy cles to enabled smm space are handled as invalid cycle type with reads and writes to location 0 and byte enables turned off for writes. when the extended smram space is enab led, processor accesses to the tseg range without smm attribute or without wb attribute are also forwarded to memory as invalid accesses. non-smm-mode write-back cycles that target tseg space are completed to main memory for cache coherency. when smm is enabled, the maximum amount of memory available to the system is equal to the amount of physical main memory minus the value in the tseg register which is fixed at 1 mb, 2 mb or 8 mb. 11.2.3 pre-allocated memory voids of physical addresses that are not accessible as general syst em memory and reside within system memory address range (< tolud) are created for smm-mode and legacy vga graphics compatibility. it is the responsibility of bios to properly initialize these regions . table 11-4 details the location and attributes of the regions. table 11-4. pre-allocated memory example for 64-mb dram, 1-mb vga and 1-mb tseg memory segments attributes comments 0000_0000h ? 03df_ffffh r/w available system memory 62 mb 03e0_0000h ? 03ef_ffffh smm mode only - processor reads tseg address range and pre-allocated memory 03f0_0000h ? 03ff_ffffh r/w pre-allocated graphics vga memory. 1 mb (or 4/8/16/32/64 mb) when igd is enabled. 11.3 pci memory address range (tolud ? 4 gb) this address range, from the top of physical memory to 4 gb (t op of addressable memory space supported by the (g)mch) is normally mapped via the dmi to pci. exceptions to this mapping include bar memory mapped regions that include: ? epbar, mchbar, dmibar. ? the second exception to the mapping rule deals with the pci express port: ? addresses decoded to the pci express memory window defined by the mbase1, mlimit1, pmbase1, and pmlimit1 registers are mapped to pci express. ? addresses decoded to pci express conf iguration space are mapped based on bus, device, and function number. (pciexbar range). ? the third exception to the mapping rule occurs in an internal graphics configuration (82915g gmch only): ? addresses decoded to the graphics memory range. (gmadr range) ? addresses decoded to the graphics tr anslation table range (gttadr range). system address map r datasheet 213 ? addresses decoded to the memory mapped range of the internal graphics device (mmadr range). there is a mmadr range for device 2 function 0 and a mmadr range for device 2 function 1. both ranges are forwarded to the internal graphics device. the exceptions listed above for internal graphics and the pci express ports must not overlap with apci configuration, fsb interr upt space and high bios address range. figure 11-4. pci memory address range high bios e000_0000h pci_address_ranges_g-p-only dmi interface (subtractively decode) fsb interrupts dmi interface (subtractively decode) local (processor) apic i/o apic dmi interface (subtractively decode) pci express configuration space dmi interface (subtractively decode) f000_0000h fec0_0000h fec8_0000h fed0_0000h fee0_0000h fef0_0000h ffe0_0000h ffff_ffffh 4 gb 4 gb ? 2 mb 4 gb ? 17 mb 4 gb ? 18 mb 4 gb ? 19 mb 4 gb ? 20 mb 4 gb ? 256 mb 4 gb ? 512 mb tolud optional hseg feda_0000h to fedb_ffffh possible address range (not guaranteed) programmable windows, graphics ranges, pci express* port could be here system address map r 214 datasheet 11.3.1 apic configuration space (fec0_0000h-fecf_ffffh) this range is reserved for apic configuration space. the i/o apic (s) usually reside in the ich6 portion of the chipset, but may also exist as stand-alone components. the ioapic spaces are used to communicate with ioapic interrupt controllers that may be populated in the system. since it is difficult to relocate an interrupt controller using plug-and-play software, fixed address decode regions have been allocated fo r them. processor accesses to the default ioapic region (fec 0_0000h to fec7_ffffh) are always forwarded to dmi. 11.3.2 hseg (feda_0000h?fedb_ffffh) this optional segment from feda_0000h to fe db_ffffh provides a remapping window to smm memory. it is sometimes called the hi gh smm memory space. smm-mode processor accesses to the optionally enabled hseg are remapped to 000a_0000h ? 000b_ffffh. non- smm-mode processor accesses to enabled hseg are considered invalid and are terminated immediately on the fsb. the exceptions to this ru le are non-smm-mode write-back cycles that are remapped to smm space to maintain cache c oherency. pci express and dmi originated cycles to enabled smm space are not allowed. physical main memory behind the hseg transaction address is not rema pped and is not accessible. all cacheline writes with wb attribute or implicit write backs to the hseg range are completed to dram like an smm cycle. 11.3.3 fsb interrupt memory space (fee0_0000?feef_ffff) the fsb interrupt space is the address used to deliver interrupts to the fsb. any device on pci express or dmi may issue a memory write to 0feex_xxxxh. the (g)mch will forward this memory write along with the data to the fsb as an interrupt message transaction. the (g)mch terminates the fsb transaction by providing the response and asserting htrdy#. this memory write cycle does not go to dram. 11.3.4 high bios area the top 2 mb (ffe0_0000h -ffff_ffffh) of the pci memory address range is reserved for system bios (high bios), extended bios for pci devices, and the a20 alias of the system bios. the processor begins execution from the high bios after reset. this region is mapped to the dmi so that the upper subset of this region aliases to the 16-mb?256-kb range . the actual address space required for the bios is less than 2 mb, but the minimum processor mtrr range for this region is 2 mb; thus, that full 2 mb must be considered. system address map r datasheet 215 11.3.5 pci express* configuration address space (intel ? 82915g/82915p only) a configuration register defines the base addre ss for the 256-mb block of addresses below top of addressable memory (4 gb) for th e configuration space associated with all devices and functions that are potentially a part of the pci express root complex hierarchy. this range will be aligned to a 256-mb boundary. bios must assign this address range such that it will not conflict with any other address ranges. 11.3.6 pci express* graphics attach (intel ? 82915g/82915p only) the (g)mch can be programmed to direct memo ry accesses to the pci express interface when addresses are within either of two programmed ranges specified via registers in the (g)mch?s device 1 configuration space. ? the first range is controlled via the memory base register (mbase) and memory limit register (mlimit) registers. ? the second range is controlled via the prefetchable memory base (pmbase) and prefetchable memory limit (pmlimit) registers. the (g)mch positively decodes memory accesses to pci express memory address space as defined by the following equations: memory_base_address address memory_limit_address prefetchable_memory_base_address address prefetchable_memory_limit_address it is essential to support a separate prefetchable range to apply uswc attribute (from the processor point of view) to that range. the uswc attribute is used by the processor for write combining. note: the programmable ranges are used to allocate me mory address space for any pci express devices sitting on pci express that require such a window. the pcicmd1 register can override the routing of memory accesse s to pci express. in other words, the memory access enable bit must be set in the device 1 pcicmd1 register to enable the memory base/limit and prefetchable base/limit windows. 11.3.7 agp dram graphics aperture unlike agp4x, pci express has no concept of aperture for pci express devices. as a result, there is no need to translate addresses from pci express. therefore, the (g)mch has no apbase and apsize registers. system address map r 216 datasheet 11.3.8 graphics memory address ranges (intel ? 82915g/82915gv/82915GL/82910gl gmch only) the gmch can be programmed to direct memory accesses to igd when addr esses are within any of three programmable ranges. ? the memory map base register (mmadr) is us ed to access graphics control registers. ? the graphics memory aperture base register (gmadr) is used to access graphics memory allocated via the graphics translation table. ? the graphics translation table base register (gttadr) is used to access the translation table. normally these ranges will reside above the top-of-main-dram and below high bios and apic address ranges. they normally reside above the top of memory (tolud) so that physical dram memory space is not allocate to them. the memory allocated via the graphics translati on table is a prefetchable range to apply uswc attribute (from the processor point of view) to th at range. the uswc attribute is used by the processor for write combining. 11.4 system management mode (smm) system management mode uses main memory for system management ram (smm ram). the (g)mch supports: compatible smram (c_smram), high segment (hseg), and top of memory segment (tseg). system management ram space provides a memory area that is available for the smi handlers and code and data storage. this memory resource is normally hidden from the system os so that the proce ssor has immediate access to this memory space upon entry to smm. (g)mch provides three smram options: ? below 1-mb option that supports compatible smi handlers. ? above 1-mb option that allows new smi ha ndlers to execute with write-back cacheable smram. ? optional tseg area of 1 mb, 2 mb, or 8 mb in size. for the 82915g/82915gv/82915GL/82910gl gmch, the tseg area lies below igd stolen memory. the above 1-mb solutions require changes to compatible smram handler?s code to properly execute above 1 mb. note: dmi and pci express masters are not allowed to access the smm space. system address map r datasheet 217 11.4.1 smm space definition smm space is defined by its addressed smm space and its dram smm space. the addressed smm space is defined as the range of bus addre sses used by the processor to access smm space. dram smm space is defined as the range of phy sical dram memory lo cations containing the smm code. smm space can be accessed at one of th ree transaction address ranges: compatible, high, and tseg. the compatible and tseg smm space is not remapped; therefore, the addressed and dram smm space is the same address range. since the high smm space is remapped, the addressed and dram smm space are different address ranges. note that the high dram space is the same as the compatible transaction address space. the following table describes three unique address ranges: ? compatible transaction address ? high transaction address ? tseg transaction address smm space enabled transaction address space dram space (dram) compatible (c) 000a_0000h to 000b_ffffh 000a_0000h to 000b_ffffh high (h) feda_0000h to fedb_ffffh 000a_0000h to 000b_ffffh tseg (t) (tolud-stolen-tseg) to tolud-stolen (tolud-stolen-tseg) to tolud-stolen 11.4.2 smm space restrictions if any of the following conditions are violated, the results of smm accesses are unpredictable and may cause the system to hang: ? the compatible smm space must not be set-up as cacheable. ? high or tseg smm transaction address space must not overlap address space assigned to system main memory, or to any ?pci? devices (including dmi, pci express, and graphics devices). this is a bios responsibility. ? both d_open and d_close capability must not be enabled at the same time. ? when tseg smm space is enabled, the tseg space must not be reported to the os as available main memory. this is a bios responsibility. ? any address translated through the internal graphics device?s tlb must not target main memory from a_0000-f_ffff. system address map r 218 datasheet 11.4.3 smm space combinations when high smm is enabled, the compatible smm space is effectivel y disabled. processor originated accesses to the comp atible smm space are forwarded to pci express if this vga capability is enabled; otherwise, they are forwarded to the dmi. pci express and dmi originated accesses are never allowed to access smm space. table 11-5. smm space table global enable g_smrame high enable h_smram_en tseg enable tseg_en compatible (c) range high (h) range tseg (t) range 0 x x disable disable disable 1 0 0 enable disable disable 1 0 1 enable disable enable 1 1 0 disabled enable disable 1 1 1 disabled enable enable 11.4.4 smm control combinations the g_smrame bit provides a global enable for all smm memory. the d_open bit allows software to write to the smm ranges without bei ng in smm mode. bios software can use this bit to initialize smm code at powerup. the d_lc k bit limits the smm range access to only smm mode accesses. the d_cls bit causes smm data accesses to be forwarded to the dmi or pci express. the smm software can use this bit to write to video memory while running smm code out of dram. table 11-6. smm control table g_smrame d_lck d_cls d_open processor in smm mode smm code access smm data access 0 x x x x disable disable 1 0 x 0 0 disable disable 1 0 0 0 1 enable enable 1 0 0 1 x enable enable 1 0 1 0 1 enable disable 1 0 1 1 x invalid invalid 1 1 x x 0 disable disable 1 1 0 x 1 enable enable 1 1 1 x 1 enable disable system address map r datasheet 219 11.4.5 smm space decode and transaction handling only the processor is allowed to access s mm space. pci express and dmi originated transactions are not allowed to smm space. 11.4.6 processor wb transaction to an enabled smm address space processor write-back transactions (hreq1# = 0) to enabled smm address space must be written to the associated smm dram, even though the space is not open and the transaction is not performed in smm mode. this ensures smm space cache coherency when cacheable extended smm space is used. 11.4.7 smm access through gtt tlb (intel ? 82915g/82915gv/82910gl gmch only) accesses through gtt tlb address translation to enabled smm dram space are not allowed. writes will be routed to memory address 0h with byte enables de-asserted and reads will be routed to memory address 0h. if a gtt tlb tran slated address hits enabled smm dram space, an invalid translation table entry flag is reported to bios. pci express and dmi originated accesses are never allowed to access smm space directly or through the gtt tlb address translation. if a gtt tlb translated address hits enabled smm dram space, an invalid translation tabl e entry flag is reported to bios. pci express and dmi write accesses through graphi cs memory range set up by bios will be snooped. if, when translated, th e resulting physical address is to enabled smm dram space, the request will be remapped to address 0h with de-asserted byte enables. pci express and dmi read accesses to the gra phics memory range set up by bios are not supported; therefore, users/systems will have no address translation con cerns. pci express and dmi reads to the graphics memory range will be remapped to address 0h. the read will complete with ur (unsupported request) completion status. gtt fetches are always decoded (at fetch time) to ensure they are not in smm (actually, anything above base of tseg or 640 kb ? 1 mb). thus, they will be invalid and go to address 0h. this is not specific to pci express or dmi; it applies to the processor or internal graphics engines. also, since the graphics memory range snoop would not be directly to smm space, there would not be a writeback to smm. in fact, the writeback would also be i nvalid (because it uses the same translation) and goes to address 0h. 11.4.8 memory shadowing any block of memory that can be designated as ?read only? or ?write only? can be ?shadowed? into (g)mch main memory. typically, this is done to allow rom code to execute more rapidly out of main dram memory. rom is used as read-only during the copy process while dram at the same time is designated write-only. after copying, the dram is designated read-only so that rom is shadowed. processor bus tran sactions are routed accordingly. system address map r 220 datasheet 11.4.9 i/o address space the (g)mch does not support the existence of any other i/o devices beside itself on the processor bus. the (g)mch generates either dmi or pci express bus cycles for all processor i/o accesses that it does not claim. within the host bridge, the (g)mch c ontains two internal registers in the processor i/o sp ace. these locations are used to implement a configuration space access mechanism. the processor allows 64 kb+3 bytes to be addressed within the i/o space. the (g)mch propagates the processor i/o address without any tr anslation on to the destination bus; therefore, providing addressability for 64 kb +3 byte locations. note that the upper 3 locations can be accessed only during i/o address wrap-around when processor bus ha16# address signal is asserted. ha16# is asserted on the processor bus when an i/o access is made to 4 bytes from address 0fffdh, 0fffeh, or 0ffffh. ha16# is also asserted when an i/o access is made to 2 bytes from address 0ffffh. for the 828915g gmch, a set of i/o accesses (oth er than ones used for configuration space access) are consumed by the internal graphics devi ce if it is enabled. the mechanisms for internal graphics i/o decode and the associ ated control are explained later. the i/o accesses (other than ones used for conf iguration space access) are forwarded normally to the dmi bus unless they fall within the pci e xpress i/o address range as defined by the mechanisms explained below. i/o writes are not posted. memory writes to the ich6 or pci express are posted. the (g)mch responds to i/o cycles initiated on pc i express or dmi with a ur status. upstream i/o cycles and configura tion cycles should never occur. if one does occur, the request will route as a read to memory address 0h so a completion is naturally generated (whether the original request was a read or write). the transaction will complete with a ur completion status. 11.4.10 pci express* i/o address mapping (intel ? 82915g/82915p/82915pl only) the (g)mch can be programmed to direct non- memory (i/o) accesses to the pci express bus interface when processor-initiated i/o cycle addr esses are within the pci express i/o address range. 11.4.11 (g)mch decode rules and cross-bridge address mapping the following are (g)mch decode rules and cross-bridge address mapping used in this chipset: ? vgaa = 000a_0000h ? 000a_ffffh ? mda = 000b_0000h ? 000b_7fffh ? vgab = 000b_8000h ? 000b_ffffh ? mainmem = 0100_0000 to tolud system address map r datasheet 221 11.4.12 legacy vga and i/o range decode rules the legacy 128-kb vga memory range 000a_0000h-000b_ffffh can be mapped to igd (82915g/82915gv/82915GL/82910gl gmch only), to pci express (device #1), and/or to the dmi depending on bios programming. priority for vga mapping is constant in that the (g)mch always decodes internally mapped devices first. internal to the gmch, decode precedence is always given to igd. the (g)mch always positively decodes internally mapped devices, namely the igd and pci express. system address map r 222 datasheet functional description r datasheet 223 12 functional description this chapter describes the (g)mch in terfaces and major functional units. 12.1 host interface the (g)mch supports the pentium 4 processor subset of the enhanced mode scaleable bus. the cache line size is 64 bytes. source synchronous transf er is used for the address and data signals. the address signals are double pumped, and a ne w address can be generated every other bus clock. at 133/200 mhz bus clock, the address signals run at 266/400 mt/s for a maximum address queue rate of 66/100 m illion addresses/sec. the data is quad pumped and an entire 64 byte cache line can be transferred in two bus clocks. at 133/200 mh z bus clock the data signals run at 533/800 mt/s for a maximum bandwidth of 4.2 gb/s or 6.4 gb/s. note: the host interface on the 82910gl gmch runs at 133 mhz only. the fsb interface supports up to 12 simultane ous outstanding trans actions. the (g)mch supports only one outstanding deferred transaction on the fsb. 12.1.1 fsb gtl+ termination the (g)mch integrates gtl+ termination resistors on die. also, approximately 2.8 pf (fast) ? 3.3 pf (slow) per pad of on die capacitance will be implemented to provide better fsb electrical performance. 12.1.2 fsb dynamic bus inversion the (g)mch supports dynamic bus inversion (db i) when driving and when receiving data from the processor. dbi limits the number of data signa ls that are driven to a low voltage on each quad pumped data phase. this decreases the worst-case power consumption of the (g)mch. hdinv[3:0]# indicate if the corre sponding 16 bits of data are i nverted on the bus for each quad pumped data phase: hdinv[3:0]# data bits hdinv0# hd[15:0] hdinv1# hd[31:16] hdinv2# hd[47:32] hdinv3# hd[63:48] when the processor or the (g)mch drives data, each 16-bit segment is analyzed. if more than 8 of the 16 signals would normally be driven low on the bus, the corresponding hdinvx# signal will be asserted and the data will be inverted prior to being driven on the bus. when the processor or the (g)mch receives data, it monitors hdinv[ 3:0]# to determine if the corresponding data segment should be inverted. functional description r 224 datasheet 12.1.3 apic cluster mode support this is required for backwards compatibility with existing software, including various operating systems. as one example, beginning with microsoft windows 2000 there is a mode (boot.ini) that allows an end user to enable the use of cluster addressing support of the apic. the (g)mch supports three types of interrupt re-direction: ? physical ? flat-logical ? clustered-logical 12.2 system memory controller this section describes the (g)mch system memory interface for bot h ddr memory and ddr2 memory. the (g)mch supports both ddr and ddr2 memory and either one or two dimms per channel. note: the 82915g/82915gv gmch and 82915p mch support both ddr memory and ddr2 memory, and either one or two dimms per channel. the 82910gl only supports ddr memory and a maximum of one dimm per channel. the 82915pl and 82915GL support only ddr and either one or two dimms per channel. 12.2.1 memory organization modes the system memory controller supports two styles of memory organization (interleaved and asymmetric) and two modes of operation (ddr and ddr2). rules for populating dimm slots are included in this chapter. interleaved mode this mode provides maximum performance on real applications. addresses are ping-ponged between the channels, and the switch happens after each cache line (64 byte boundary). if two consecutive cache lines are requested, both may be retrieved simultaneously, since they are guaranteed to be on opposite channels. the drawbacks of interleaved mode are that the system designer must populate both channels of memory such that they have equal capacity, but the technology and device width may vary from one ch annel to the other. refer to figure 12-1 for further clarification. asymmetric mode this mode trades performance for system design flexibility. unlike the previous mode, addresses start in channel a and stay there until the end of the highest rank in channel a; then, addresses continue from the bottom of channel b to the top. real world applications are unlikely to make requests that alternate between addresses that sit on opposite channels with this memory organization, so in most cases, bandwidth will be limited to that of a single channel. the system designer is free to populate or not to populate any rank on either channel, including either degenerate single channel case. refer to figure 12-1 for further clarification. functional description r datasheet 225 figure 12-1. system memory styles sy s_mem_sty les single channel cl cl cl dual channel interleaved (channels do not have to match) dual channel asymmetric (channels do not have to match) ch b ch a ch b ch a ch b ch a 00 scheme xor bit 6 => cl ch a or ch b ch b ch a tom tom ch b0 ch a tom ch a0 ch b tom table 12-1. sample system memory organization with interleaved channels rank channel a population cumulative top address in channel a channel b population cumulative top address in channel b 3 0 mb 2560 mb 0 mb 2560 mb 2 256 mb 2560 mb 256 mb 2560 mb 1 512 mb 2048 mb 512 mb 2048 mb 0 512 mb 1024 mb 512 mb 1024 mb table 12-2. sample system memory organization with asymmetric channels rank channel a population cumulative top address in channel a channel b population cumulative top address in channel b 3 0 mb 1280 mb 0 mb 2560 mb 2 256 mb 1280 mb 256 mb 2560 mb 1 512 mb 1024 mb 512 mb 2304 mb 0 512 mb 512 mb 512 mb 1792 mb functional description r 226 datasheet 12.3 system memory configuration registers overview the configuration registers locat ed in the pci configuration sp ace of the (g)mch control the system memory operation. following is a brief description of configuration registers. ? dram rank boundary (cxdrby): the x represents a channel, either a (where x = 0) or b (where x = 1). the y represents a rank, 0 through 3. drb registers define the upper addresses for a rank of dram devices in a channel. when the (g)mch is configured in asymmetric mode, each register represents a si ngle rank. when the (g)mch is configured in a dual interleaved mode, each register repres ents a pair of corresponding ranks in opposing channels. there are 4 drb registers for each channel. ? dram rank architecture (cxdray): the x represents a channel, either a (where x = 0) or b (where x = 1). the y represents a rank, 0 through 3. dra registers specify the architecture features of each rank of devices in a channel. the onl y architecture feature specified is page size. when the (g)mch is configured in asymmetric mode, each dra represents a single rank in a single channel. when the (g)mch is configured in a dual- channel lock-step or interleaved mode, each dr a represents a pair of corresponding ranks in opposing channels. there are 4 dra registers per channel. each requires only 3 bits, so there are two dras packed into a byte. ? clock configuration (clkcfg): specifies dram frequency. the same clock frequency will be driven to all dimms. ? dram timing (cxdrty): the x represents a channel, a (where x = 0) or b (where x = 1). a second register for a channel is differentiated by y, a or b. the drt registers define the timing parameters for all devices in a channel. the bios programs this register with ?least common denominator? valu es after reading the spd registers of each dimm in the channel. ? dram control (cxdrcy): the x represents a channel, a (where x = 0) or b (where x = 1). a second register for a channel is differentiated by y, a or b. dram refresh mode, rate, and other controls are selected here. functional description r datasheet 227 12.3.1 dram technologies and organization all standard 256-mb, 512-mb, and 1-gb technol ogies and addressing are supported for x16 and x8 devices. ? all supported ddr devices have 4 banks; all supported ddr2 devices have 4 or 8 banks. ? the (g)mch supports various page sizes. page size is individually selected for every rank. ? 4 kb, 8 kb, and 16 kb for asymmetric, interleaved, or single-channel modes. ? the dram sub-system supports single or dual channels, 64-b wide per channel. ? there can be a maximum of four ranks populated (two double-sided dimms) per channel. ? mixed mode double-sided dimms (x8 and x16 on the same dimm) are not supported ? by using 1-gb technology, the largest memory capacity is 8 gb 32m rows/bank * 4 banks/device * 8 column s * 8 devices/rank * 4 ranks/channel * 2 channel * 1b/(row*column) * 1g/1024m * 1b/8b = 8 gb. though it is possible to put 8 gb in system by stuffing both channels this way, the (g)mch is still limited to 4 gb of addressable space due to the number of address pins on the fsb. ? by using 256-mb technology, the smallest memory capacity is 128 mb (4m rows/bank * 4banks/device * 16 columns * 4 devices/rank * 1 rank * 1b/8b =128 mb) 12.3.1.1 rules for p opulating dimm slots ? in all modes, the frequency of system memory will be the lowest frequency of all dimms in the system, as determined through the spd registers on the dimms. ? in the single channel mode, any dimm slot within the channel may be populated in any order. either channel may be used. to sa ve power, do not populate the unused channel. ? in dual-channel asymmetric mode, any dimm slot may be populated in any order. ? in dual-channel interleaved mode, any dimm slot may be populated in any order, but the total memory in each channel must be the same. functional description r 228 datasheet 12.3.1.2 system memory supported configurations the (g)mch supports the 256-mbit, 512-mbit and 1-gbit technology based dimms from table 12-3. table 12-3. ddr / ddr2 dimm supported configurations technology configuration # of row address bits # of column address bits # of bank address bits page size rank size 256mbit 16m x 16 13 9 2 4k 128 mb 256mbit 32m x 8 13 10 2 8k 256 mb 512mbit 32m x 16 13 10 2 8k 256 mb 512mbit 64m x 8 13 11 2 16k 512 mb 512mbit 64m x 8 14 10 2 8k 512 mb 1gbit 64m x 16 14 10 2 8k 512 mb 1gbit 128m x 8 14 11 2 16k 1 gb 1gbit 64m x 16 13 10 3 8k 512 mb 1gbit 128m x 8 14 10 3 8k 1 gb 12.3.1.3 main memory dram a ddress translation and decoding table 12-4 and table 12-5 specify the host inte rface to memory interface address multiplex for the (g)mch. refer to the details of the various dimm configurations as described in table 12-3. the address lines specified in the column header refer to th e host (processor) address lines. functional description r datasheet 229 table 12-4. dram address translation (single channel/dual asymmetric mode) tech banks page size rank size 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 256 mb x16 4i 4 kb 128 mb r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 r11 r12 b0 b1 c8 c7 c6 c5 c4 c3 c2 c1 c0 256 mb x8 4i 8 kb 256 mb r12 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 r11 b1 b0 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 512 mb x16 4i 8 kb 256 mb r12 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 r11 b1 b0 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 512 mb x8 4i 16 kb 512 mb r11 r12 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 b0 b1 c11 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 512 mb x16 4i 8 kb 256 mb r12 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 r11 b1 b0 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 512 mb x8 4i 8 kb 512 mb r13 r12 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 r11 b1 b0 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 1 gb x16 4i 8 kb 512 mb r13 r12 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 r11 b1 b0 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 1 gb x8 4i 16 kb 1 gb r13 r11 r12 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 b0 b1 c11 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 1 gb x16 8i 8 kb 512 mb r11 r12 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 b0 b1 b2 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 1 gb x8 8i 8 kb 1 gb r13 r11 r12 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 b0 b1 b2 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 notes: 1. b ? ?bank? select bit 2. c ? ?column? address bit 3. r ? ?row? address bit functional description r 230 datasheet table 12-5. dram address translation (dual channel symmetric mode) tech banks page size rank size 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 256 mb x16 4i 4 kb 128 mb r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 r11 r12 b0 b1 c8 c7 c6 c5 c4 c3 h c2 c1 c0 256 mb x8 4i 8 kb 256 mb r12 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 r11 b1 b0 c9 c8 c7 c6 c5 c4 c3 h c2 c1 c0 512 mb x16 4i 8 kb 256 mb r12 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 r11 b1 b0 c9 c8 c7 c6 c5 c4 c3 h c2 c1 c0 512 mb x8 4i 16 kb 512 mb r11 r12 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 b0 b1 c11 c9 c8 c7 c6 c5 c4 c3 h c2 c1 c0 512 mb x16 4i 4 kb 256 mb r12 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 r11 b1 b0 c9 c8 c7 c6 c5 c4 c3 h c2 c1 c0 512 mb x8 4i 8 kb 512 mb r13 r12 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 r11 b1 b0 c9 c8 c7 c6 c5 c4 c3 h c2 c1 c0 1 gb x16 4i 8 kb 512 mb r13 r12 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 r11 b1 b0 c9 c8 c7 c6 c5 c4 c3 h c2 c1 c0 1 gb x8 4i 16 kb 1 gb r13 r11 r12 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 b0 b1 c11 c9 c8 c7 c6 c5 c4 c3 h c2 c1 c0 1 gb x16 8i 4 kb 512 mb r11 r12 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 b0 b1 b2 c9 c8 c7 c6 c5 c4 c3 h c2 c1 c0 1 gb x8 8i 8 kb 1 gb r13 r11 r12 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 b0 b1 b2 c9 c8 c7 c6 c5 c4 c3 h c2 c1 c0 notes: 1. b ? ?bank? select bit 2. c ? ?column? address bit 3. h ? channel select bit 4. r ? ?row? address bit functional description r datasheet 231 12.3.2 dram clock generation the (g)mch generates three differential clock pairs for every supported dimm. there are a total of 6 clock pairs driven directly by the (g)mch to 2 dimms per channel (82915g/82915gv/82915GL and 82915p) and to 1 dimm per channel (82910gl/82915pl). 12.3.3 suspend-to-ram and resume when entering the suspend-to-ram (str) state, the sdram controller will flush pending cycles and then enter all sdram rows into self refresh. in str, the cke signals remain low so the sdram devices will perform self-refresh.n 12.3.4 ddr2 on-die termination on-die termination (odt) is a feature that allows a dram to turn on/off internal termination resistance for each dq, dm, dqs, and dqs# signa l for x8 and x16 configurations via the odt control signals. the odt feature is designed to improve signal integrity of the memory channel by allowing the termination resistance for the dq, dm, dqs, and dqs# signals to be located inside the dram devices themselves, instead of on the motherboard. the (g)mch drives out the required odt signals, based on memory configuration and which rank is being written to or read from, to the dram devices on a targeted dimm rank to enable or disable their termination resistance. 12.3.5 ddr2 off-chip driver impedance calibration the ocd impedance adjustment mode allows the (g)mch to measure and adjust the pull-up and pull-down strength of the dram devices. it uses a series of emrs commands to guide the dram through measurement and calibration cycles. this feature is described in more detail in the jedec ddr2 device specification. the algorithm and sequence of the adjustment cy cles is handled by software. the (g)mch adjusts the dram driver impedance by issuing ocd commands to the dimm and looking at the analog voltage on the dq lines. functional description r 232 datasheet 12.4 pci express* (intel ? 82915g/82915p82915pl only) refer to chapter 0 a for list of pci express feat ures, and the pci express specification for further details . the (g)mch is part of a pci express root complex. this means it connects a host processor/memory subsystem to a pci express hierarchy. the pci express architecture is specified in layers. compatibility with the pci addressing model (a load-store architecture with a flat address space) is maintain ed to ensure that all existing applications and drivers operate unchanged. th e pci express configuration uses standard mechanisms as defined in the pci plug-and-play specification. the initial speed of 1.25 ghz (250 mhz internally) results in 2.5 gb/s/direction that provides a 250 mb/s communications channel in each direction (500 mb/s total) per lane that is close to twice the data rate of classic pci. note: the pci express graphics port will operate in x1 mode if a non-graphics card is plugged in. 12.4.1 transaction layer the upper layer of the pci express architecture is the transaction layer. the transaction layer?s primary responsibility is the assembly and disa ssembly of transaction layer packets (tlps). tlps are used to communicate transactions (such as read and write as well as certain types of events). the transaction layer also manages flow control of tlps. note: if the (g)mch receives two back-t o-back malformed packets, the second malformed packet is not trapped or logged. the (g)mch will not log or identify the second malformed packet. however, the 1 st malformed tlp is logged, and is considered a fatal error. link behavior is not guaranteed at that point whether a 2 nd malformed tlp is detected or not. 12.4.2 data link layer the middle layer in the pci express stack, the data link layer, serves as an intermediate stage between the transaction layer and the physi cal layer. responsibilities of data link layer include link management, error de tection, and error correction. 12.4.3 physical layer the physical layer includes all circuitry for interface operation, incl uding driver and input buffers, parallel-to-serial and serial-to-paralle l conversion, pll(s), and impedance matching circuitry. functional description r datasheet 233 12.5 intel ? serial digital video output (sdvo) (intel ? 82915g/82915gv/82915GL/82910gl gmch only) the 82915g/82915gv/82915GL/82910gl gmch sdvo por ts are multiplexed with the pci express x16 interface. pci express and sdvo si multaneous operation is not supported, even though sdvo does not require all of the pci express lanes. the intel ? sdvo port is the second generation of digital video output from compliant gmch. the electrical interface is based on the pci expr ess interface, although the protocol and timings are completely unique. where pci express runs at a fixed frequency, the frequency of the sdvo interface is dependant upon the active display reso lution and timing. the port can be dynamically configured in several modes to support display configurations. essentially, an sdvo port will tr ansmit display data in a high speed, serial format across differential ac coupled signals. an sdvo port cons ists of a sideband differential clock pair and a number of differential data pairs. 12.5.1 intel ? sdvo capabilities sdvo ports can support a variety of display types including lvds, dvi, analog crt, tv-out and external ce type devices. the gmch uses an external sdvo device to translate from sdvo protocol and timings to the desired display format and timings. the internal graphics device on the 82915g/82915gv/82915GL/82910gl gmch can have one or two sdvo ports multiplexed on the x16 pci e xpress interface. when an external x16 pci express graphics accelerator is not in use, an add2 card may be plugged into the x16 connector or if a x16 slot is not present, the sdvo(s) ma y be located ?down? on the motherboard to access the multiplexed sdvo ports and provide a variety of digital display options. the add2 card is designed to fit in a x16 pci express connector. the add2 card can support one or two devices. if a single channel sdvo device is used, it should be attached to the channel b sdvo pins. the add2 card can support two separa te sdvo devices when the interface is in dual independent (82915g only) or dual simultaneous standard modes. the sdvo port defines a two-wire point-to-point comm unication path between the sdvo device and gmch. the sdvo control clock and da ta provide similar functionality to i 2 c. however, unlike i 2 c, this interface is intended to be point-t o-point (from the gmch to the sdvo device) and will require the sdvo device to act as a switc h and direct traffic from the sdvo control bus to the appropriate receiver. additionally, this contro l bus will be able to run at faster speeds (up to 1 mhz) than a traditional i 2 c interface would. functional description r 234 datasheet 12.5.2 intel ? sdvo modes the port can be dynamically configured in several modes: ? standard. this mode provides baseline sdvo func tionality. supports pixel rates between 25 and 200 mp/s. utilizes three data pairs to transfer rgb data. ? extended. this mode adds alpha support to data stream. extended mode supports pixel rates between 25 mp/s and 200 mp/s. the mode uses four data channels and is only supported on sdvob. leverages channel c (sdvoc) red pair as the alpha pair for channel b (sdvob). note: operating in extended sdvo mode is mutually exclusive to the use of a second display on sdvo. ? dual standard. this mode uses standard data streams across both sdvob and sdvoc. both channels can only run in standard mode (3 data pairs) and each channel supports pixel rates between 25 and 200 mp/s. ? dual independent sta ndard (82915g only). in dual i ndependent standard mode, each sdvo channel will see a different pixel str eam. the data stream across sdvob will not be the same as the data stream across sdvoc. ? dual simultaneous standard. in dual simultaneous standa rd mode, both sdvo channels will see the same pixel stream. the data stream across sdvob will be the same as the data stream across sdvoc. the display timings will be identi cal, but the transfer timings may not be (i.e., sdvob clocks and data may not be perfectly aligned with sdvoc clock and data as seen at the sdvo device(s)). since this mode uses just a single data stream, it uses a single pixel pipeline within the gmch. functional description r datasheet 235 12.6 integrated graphics device (intel ? 82915g/82915gv/82915GL/82910gl gmch only) the gmch provides a highly integrated graphi cs accelerator and chipset while allowing a flexible integrated system graphics solution. figure 12-2 shows a simplified block diagram of the igd in the gmch. figure 12-2. integrated graphics device block diagram m e m o r y 3d engine 2d engine display engine port mux control dac (analog) sdvoc (digital) sdvob (digital) video engine gfx_blk_dia high bandwidth access to data is provided through th e graphics and system memory ports. the gmch can access graphics data located in system memory at 4.2 gb/s ? 8.5 gb /s (depending on memory configuration). the gmch uses intel?s direct memory execution model to fetch textures from system memory. the gmch includes a cache controller to a void frequent memory fetc hes of recently used texture data. the gmch is able to drive an integrated dac, and/or two s dvo ports (multiplexed with pci express) capable of driving an add2 card. ex ternal sdvo devices are capable of driving a standard progressive scan analog monitor with resolutions up to 2048x1536 @ 75 hz. the sdvo ports are capable of driving a variety of tv-out, tmds, and lvds transmitters. the gmch?s internal graphics device (igd) cont ains several types of components. the major components in the igd are the engines, planes, pipes and ports. the gmch has a 3d/2d instruction processing unit to control the 3d and 2d engines. the igd?s 3d and 2d engines are fed with data through the memory controller. th e outputs of the engines are surfaces sent to memory, which are then retrieved and processed by the gmch planes. the gmch contains a variety of planes (such as display, ove rlay, cursor and vga). a plane consists of rectangular shaped image that ha s characteristics such as source, size, position, method, and format. these planes get attached to source surfaces that are rectangular memory surfaces with a similar set of char acteristics. they are also associat ed with a particular destination pipe. a pipe consists of a set of combined planes and a timing generator. the gmch has two independent display pipes, allowing for support of two independent display streams. a port is the destination for the result of the pipe. the gmch contains three display ports, 1 analog (dac) functional description r 236 datasheet and two digital (sdvo ports b and c). the ports w ill be explained in more detail later in the chapter. the entire igd is fed with data from its memory controller. the gmch?s graphics performance is directly related to the amount of bandwidth av ailable. if the engines ar e not receiving data fast enough from the memory controller (e.g., single-channel ddr333), the rest of the igd will also be affected. the rest of this chapter will focus on explai ning the igd components, their limitations and dependencies. 12.6.1 3d engine the 3d engine of gmch has been designed with a deep pipelined architecture, where performance is maximized by allowing each stage of the pipeline to simultaneously operate on different primitives or portions of the same primitive. gmch supports perspective-correct texture mapping, multitextures, bump-mapping, cubic environment maps, bilinear, trilinear and anisotropic mip mapped filtering, gouraud shading, alpha-blending, vertex and per pixel fog and z/w buffering. the 3d pipeline subsystem performs the 3d re ndering acceleration. the main blocks of the pipline are the setup engine, scan converter, texture pipeline, and raster pipeline. a typical programming sequence would be to send instructions to set the state of the pipeline followed by rending instructions containing 3d primitive vertex data. the engine?s performance is dependent on the memo ry bandwidth available. systems that have more bandwidth available will outperform systems with less bandwidth. the engine?s performance is also dependent on the core cloc k frequency. the higher the frequency, the more data is processed. 12.6.2 setup engine the setup stage of the pipeline takes the input data associated with each ve rtex of a 3d primitive and computes the various paramete rs required for scan conversion. in formatting this data, the gmch maintains sub-pixel accuracy. 12.6.2.1 3d primitives and data formats support the 3d primitives rendered by gmch are points, lines, discrete triangles, line strips, triangle strips, triangle fans a nd polygons. in addition to this, gmch supports the microsoft directx* flexible vertex format (fvf), which enables th e application to specify a variable length of parameter list obviating the need for sending unused information to the hardware. strips, fans and indexed vertices as well as fvf, improve the vertex rate delivered to the setup engine significantly. functional description r datasheet 237 12.6.2.2 pixel accurate ?fast? sc issoring and clipping operation the gmch supports 2d clipping to a scissor rectangle within the drawing window. objects are clipped to the scissor rectangle, avoiding processing pixels that fall outside the rectangle. the gmch?s clipping and scissoring in hardware redu ce the need for software to clip objects, and thus improve performance. during the setup stage, gmch clips objects to the scissor window. a scissor rectangle accelerates th e clipping process by allowing th e driver to clip to a bigger region than the hardware renders to. the sci ssor rectangle needs to be pixel accurate, and independent of line and point width. the gmch will support a single scissor box rectangle that can be enabled or disabled. the rectangle is defined as an inclusive box. inclusive is defined as ?draw the pixel if it is inside the scissor rectangle?. 12.6.2.3 depth bias the gmch supports source depth biasing in the setup engine. the depth bias value is specified in the vertex command packet on a per primitive basis. the value ranges from -1 to 1. the depth bias value is added to the z or w valu e of the vertices. this is used for coplanar polygon priority. if two polygons are to be rendered that are coplanar, due to the inherent precision differences induced by unique x, y and z values, there is no guarantee which polygon will be closer or farther. by using depth bias, it is possible to offset the destination z value (compare value) before comparing with the new z value. 12.6.2.4 backface culling as part of the setup, the gmch discards polygons from further processing, if they are facing away from or towards the user?s viewpoint. this operation, referred to as ?back face culling? is accomplished based on the ?clockwise? or ?counter-c lockwise? orientation of the vertices on a primitive. this can be enabled or disabled by the driver. 12.6.2.5 scan converter working on a per-polygon basis, the scan converter uses the vertex and edge information is used to identify all pixels affected by features being rendered. 12.6.2.6 pixel rast erization rules the gmch supports both opengl and d3d pixel rasterization rules to determine whether a pixel is filled by the triangle or line. for both d3d and opengl modes, a top-left filling convention for filling geometry will be used. pixel rasterization rule on rectangle primitive is also supported using the top- left fill convention. 12.6.2.7 2d functionality the stretch blt function can stretch source data in the x and y directions to a destination larger or smaller than the source. stretch blt functionality expands a region of memory into a larger or smaller region using replication and interpolation. the stretch blt function also provides format conversion and data alignment. functional description r 238 datasheet 12.6.3 texture engine the gmch allows an image, pattern, or video to be placed on the surface of a 3d polygon. the texture processor receives the texture coordi nate information from th e setup engine and the texture blend information from the scan converter. the texture processor performs texture color or chromakey matching, texture filtering (anisotropic, trilinear, and bilinear interpolation), and yuv to rgb conversions. 12.6.3.1 perspective correct texture support a textured polygon is ge nerated by mapping a 2d texture patte rn onto each pixel of the polygon. a texture map is like wallpaper pasted onto the polygon. since polygons are rendered in perspective, it is important that texture be ma pped in perspective as well. without perspective correction, texture is distorted when an object recedes in to the distance. 12.6.3.2 texture formats and storage the gmch supports up to 32 bits of color for textures. 12.6.3.3 texture decompression directx supports texture compression to reduce the bandwidth required to deliver textures. as the textures? average size gets larger with higher color depth and multiple textures become the norm, it becomes increasingly important to provide a mechanism for compressing textures. texture decompression formats supported include dxt1, dxt2, dxt3, dxt4, dxt5 and fxt1. 12.6.3.4 texture chromakey chromakey describes a method of removing a specific color or range of colors from a texture map before it is applied to an object. for ?nearest? texture filter modes, removing a color simply makes those portions of the object transparent (the previous contents of the back buffer show through). for ?linear? texture filtering modes, the te xture filter is modified if only the non-nearest neighbor texels match the key (range). 12.6.3.5 anti-aliasing aliasing is one of the artifacts that degrade image quality. in its simplest manifestation, aliasing causes the jagged staircase effects on sloped lines and polygon edges. another artifact is the moir patterns that occur as a result of a very small number of pixels available on screen to contain the data of a high resolution texture map. more subtle effects are observed in animation, where very small primitives blink in and out of view. 12.6.3.6 texture map filtering the gmch supports many texture mapping modes. perspective correct mapping is always performed. as the map is fitted across the polygon, the map can be tiled, mirrored in either the u or v directions, or mapped up to the end of the texture and no longer placed on the object (this is known as clamp mode). the way a texture is combined with other object attributes is also definable. functional description r datasheet 239 the gmch supports up to 12 levels-of-detail (lods) ranging in size from 2048x2048 to 1x1 texels. textures need not be s quare. included in the texture pro cessor is a texture cache, which provides efficient mip-mapping. the gmch supports 7 types of texture filtering: ? nearest (aka point filtering): texel with coordinates nearest to the desired pixel is used. (this is used if only one lod is present). ? linear (aka bilinear filtering): a weighted average of a 2x2 area of texels surrounding the desired pixel is used. (this is used if only one lod is present). ? nearest mip nearest (aka point filtering): this is used if many lods are present. the nearest lod is chosen and the texel with coor dinates nearest to the desired pixel is used. ? linear mip nearest (bilinear mip mapping): this is used if many lods are present. the nearest lod is chosen and a weighted average of a 2x2 area of texels surrounding the desired pixel is used (four texels). this is also referred to as bilinear mip mapping. ? nearest mip linear (point mip mapping): this is used if many lods are present. two appropriate lods are selected and within each lod the texel with coor dinates nearest to the desired pixel is selected. the final texture valu e is generated by linear interpolation between the two texels selected from each of the mip maps. ? linear mip linear (trilinear mip mapping): this is used if many lods are present. two appropriate lods are selected and a weighted average of a 2x2 area of texels surrounding the desired pixel in each mip map is generated (f our texels per mip map). the final texture value is generated by linear interpolation betw een the two texels generated for each of the mip maps. trilinear mip mapping is used minimize the visibility of lod transitions across the polygon. ? anisotropic mip nearest (anisotropic filtering): th is is used if many lods are present. the nearest lod-1 level will be determined for each of four sub-samples for the desired pixel. these four sub-samples are then bilinear filtered and averaged together. both d3d (directx 6.0 and later) and opengl (rev ision 1.1) allow support for all these filtering modes. 12.6.3.7 multiple texture composition the gmch also performs multiple texture composition. this allows the combination of two or greater mip maps to produce a new one with new lods and texture attributes in a single or iterated pass. flexible vertex format support a llows multitexturing because it makes it possible to pass more than one texture in the vertex structure. 12.6.3.8 bi-cubic filter (4x4 programmable texture filter) a bi-cubic texture filter can be selected instead of the bilinear filter. the implementation is of a 4x4 separable filter with loadable coefficients. a 4x4 filter can be used for providing high-quality up/ down scaling of 2d or 3d rendered images. functional description r 240 datasheet 12.6.3.9 cubic environment mapping environment maps allow applications to render scenes with complex lighting and reflections while significantly decreasing processor load. there are several methods to generate environment maps (such as, spherical, circular and cubic) . the gmch supports cubic reflection mapping over spherical and circular since it is the best choice to provide real-time environment mapping for complex lighting and reflections. cubic mapping requires a texture ma p for each of the 6 cube faces. these can be generated by pointing a camera with a 90-degree field-of-view in the appropriate direction. per-vertex vectors (normal, reflection or refraction) are interpolated across the polygon and the intersection of these vectors with the cube texture faces is calculated. texel values are then read from the intersection point on the appropriate face and filtered accordingly. 12.6.4 raster engine the raster engine is where the color data (such as fogging, specular rgb, texture map blending, etc.) is processed. the final color of the pixel is calculated and the rgba value combined with the corresponding components resulting from the te xture engine. these textured pixels are modified by the specular and fog parameters. these specular highlighted, fogged, textured pixels are color blended with the existing values in the fra me buffer. in parallel, stencil, alpha and depth buffer tests are conducted which will determine whether the frame and depth buffers will be updated with the new pixel values. 12.6.4.1 texture map blending multiple textures can be blended together in an iterative process and applied to a primitive. the gmch allows up to four texture coordinates and texture maps to be specified onto the same polygon. also, the gmch supports using a texture coordinate set to access multiple texture maps. state variables in multiple texture are bound to texture coordinates, te xture map or texture blending. 12.6.4.2 combining intrinsic and specular color components the gmch allows an independently specified and interpolated ?specular rgb? attribute to be added to the post-texture blended pixel color. this feature provides a full rgb specular highlight to be applied to a textured surface, permitting a high-quality reflective colo red lighting effect not available in devices which apply texture after the lighting components have been combined. if specular-add state variable is disabled, only the resultant colors from the map blending are used. if this state variable is enabled, rgb values from the output of the map blending are added to values for rs, gs, bs on a component by component basis. 12.6.4.3 color shading modes the raster engine supports the flat and gouraud shading modes. these shading modes are programmed by the appropriate state variables issued through the command stream. flat shading is performed by smoothly interpolating the vertex intrinsic color components (red, green, blue), specular highlights(r,g,b), fog, a nd alpha to the pixel, where each vertex color has the same value. the setup engine substitutes one of the vertex?s attribute values for the other functional description r datasheet 241 two vertices attribute values ther eby creating the correct flat shad ing terms. this condition is set up by the appropriate state variables issued prior to rendering the primitive. opengl and d3d use a different vert ex to select the flat shaded co lor. this vertex is defined as the ?provoking vertex?. in the case of strips/fans, after the first triangle, attributes on every vertex that define a primitive are used to select the flat color of the primitive. a state variable is used to select the ?flat color? prior to rendering the primitive. gouraud shading is performed by smoothly interpolating the vertex intrinsic color components (red, green, blue). specular highli ghts (r,g,b), fog, and alpha to the pixel, where each vertex color has a different value. all the attributes can be selected independently from one of the shading modes by setting the appropriate value state variables. 12.6.4.4 color dithering color dithering helps to hide color quantization errors. color dithering takes advantage of the human eye?s propensity to ?average? the colors in a small area. input color, alpha, and fog components are converted from 8-bit components to 5- or 6- bit component by dithering. dithering is performed on blended textured pixels. in 32-bit mode, dithering is not performed on the components 12.6.4.5 vertex and per pixel fogging fogging is used to create atmosphe ric effects (such as low visibility conditions in flight simulator- type games). it adds another level of realism to computer-generated scenes. fog can be used for depth cueing or hiding distant objects. with fog, distant objects can be rendered with fewer details (fewer polygons), thereby improving the re ndering speed or frame rate. fog is simulated by attenuating the color of an object with the fog color as a function of distance. higher fog density produces lower visibility for distant objects. there are tw o ways to implement the fogging technique: per-vertex (linear) fogging and per-pix el (non-linear) fogging. the per-vertex method interpolates the fog value at the vertices of a polygon to determine the fog factor at each pixel within the polygon. this method provides realistic fogging as long as the polygons are small. with large polygons (such as a ground plane depicting an airport runway), the per-vertex technique results in unnatural fogging. the gmch supports both types of fog operations, ve rtex and per pixel or table fog. if fog is disabled, the incoming color intensities are passed unchanged to the destination blend unit. 12.6.4.6 alpha blending (frame buffer) alpha blending adds the material property of transparency or opacity to an object. alpha blending combines a source pixel color (r s g s b s ) and alpha (a s ) component with a destination pixel color (r d g d b d ) and alpha (a d ) component. for example, this is so that a glass surface on top (source) of a red surface (destination) would allow much of the red base color to show through. blending allows the source and destination color values to be multiplied by programmable factors and then combined via a programmable blend func tion. the combined and independent selection of factors and blend functions for color and alpha are supported. functional description r 242 datasheet 12.6.4.7 microsoft directx* api and sgi opengl* api logic ops both apis provide a mode to use bitwise ops in place of alpha blending. th is is used for rubber- banding (i.e., draw a rubber band outline over th e scene using an xor operation). drawing it again restores the original image without having to do a potentially expensive redraw. 12.6.4.8 color buffer formats: 8-, 16-, or 32-bits per pixel (destination alpha) the raster engine supports 8-bit, 16-bit, and 32-bit color buffer formats. the 8-bit format is used to support planar yuv420 format, which used only in motion compensation and arithmetic stretch format. the bit format of color and z will be allowed to mix. the gmch supports both double and triple buffering, where one buffer is the primary buffer used for display and one or two are the back buffer(s) used for rendering. the frame buffer of the gmch contains at least two hardware buffers: the front buffer (display buffer) and the back buffer (rendering buffer). while the back buffer may act ually coincide with (or be part of) the visible displa y surface, a separate (screen or window-sized) back buffer is used to permit double-buffered drawing. that is, the imag e being drawn is not visible until the scene is complete and the back buffer made visible (via an instruction) or copied to the front buffer (via a 2d blt operation). rendering to one and displaying from the other remove the possibility of image tearing. this also speeds up the display process over a single buffer. additionally, triple back buffering is also supported. the instruction set of the gmch provides a variety of controls for the buffers (e.g., initializing, flip, clear, etc.). 12.6.4.9 depth buffer the raster engine can read and write from this buffer and use the data in per fragment operations that determine whether resultant color and depth value of the pixel for the fragment are to be updated or not. typical applications for en tertainment or visual simulations with exterior scenes require far/near ratios of 1000 to 10000. at 1000, 98% of the range is spent on the first 2% of the depth. this can cause hidden surface artifacts in di stant objects, especially when using 16-bit depth buffers. a 24-bit z-buffer provides 16 million z-values, as opposed to only 64 k with a 16-bit z buffer. with lower z-resolution, two distant overlapping objects may be assigned the same z-value. as a result, the rendering hardware may have a problem resolving the order of the objects, and the object in the back may appear through the object in the front. by contrast, when w (or eye-relative z) is used , the buffer bits can be more evenly allocated between the near and far clip planes in world sp ace. the key benefit is that the ratio of far and near is no longer an issue, allo wing applications to support a maximum range of miles, yet still get reasonably accurate depth buffering w ithin inches of the eye point. the gmch supports a flexible format for the floating-point w buffer, wherein the number of exponent bits is programmable. this allows the driver to determine variable precision as a function of the dynamic range of the w (screen-space z) parameter. the selection of depth buffer size is relatively independent of the color buffer. a 16-bit z/w or 24-bit z/w buffer can be selected with a 16-bit color buffer. z buffer is not supported in 8-bit mode. functional description r datasheet 243 12.6.4.10 stencil buffer the raster engine provides 8-bit stencil buffer storage in 32-bit mode and the ability to perform stencil testing. stencil testing controls 3d draw ing on a per pixel basis, conditionally eliminating a pixel on the outcome of a comparison between a stencil reference value and the value in the stencil buffer at the location of the source pixel being processed. they are typically used in multipass algorithms to achieve special effect s, such as decals, outlining, shadows and constructive solid geometry rendering. 12.6.4.11 projective textures the gmch supports two simultaneous projective textures at full rate processing, and four textures at half rate. these textures require thr ee floating point texture coordinates to be included in the flexible vertex format (fvf). projective te xtures enable special e ffects (such as projecting spot light textures obliquely onto walls, etc.). 12.6.5 2d engine the gmch contains blt functionality, and an extensive set of 2d instructions. to take advantage of the 3d drawing engine?s functionality, some blt functions (such as alpha blts, arithmetic (bilinear) stretch blts, rotations, transposing pixel maps, limited color space conversion, and dibs) make use of the 3d renderer. 12.6.5.1 gmch vga registers the 2d registers are a combination of registers defined by ibm when the video graphics array (vga) was first introduced and others that intel has added to support graphics modes that have color depths, resolutions, and hardware acceleration features that go beyond the original vga standard. 12.6.5.2 logical 128-bit fixed blt and 256 fill engine use of this blt engine accelerates the graphi cal user interface (gui) of microsoft windows* operating systems. the 128-bit gmch blt engi ne provides hardware acceleration of block transfers of pixel data for many common windows operations. the term blt refers to a block transfer of pixel data between memory locations. the blt engine can be used for the following: ? move rectangular blocks of data between memory locations ? data alignment ? perform logical operations (raster ops) the rectangular block of data does not change as it is transferred between memory locations. the allowable memory transfers ar e between: cacheable system memory and frame buffer memory, frame buffer memory and frame buffer memory, and within system memory. data to be transferred can consist of regions of memory, patterns, or solid color fills. a pattern will always be 8x8 pixels wide and may be 8, 16, or 32 bits per pixel. the gmch blt engine has the ability to expand monoc hrome data into a color depth of 8, 16, or 32 bits. blts can be either opaque or transparent. opaque transfers move th e data specified to the functional description r 244 datasheet destination. transparent transf ers compare destination color to source color and write according to the mode of transparency selected. data is horizontally and vertically aligned at the destination. if the destination for the blt overlaps with the source memory location, the gm ch can specify which area in memory to begin the blt transfer. hardware is included for all 256 raster operations (source, pattern, and destination) defined by microsoft, including transparent blt. the gmch has instructions to invoke blt and stretch blt operati ons, permitting software to set up instruction buffers and use batch processi ng. the gmch can perform hardware clipping during blts. 12.6.6 video engine 12.6.6.1 hardware motion compensation the motion compensation (mc) process consists of reconstructing a new picture by predicting (either forward, backward, or bi-directionally) the resulting pixel colors from one or more reference pictures. the gmch receives the vide o stream and implements motion compensation and subsequent steps in hardware. performing motion compensation in hardware reduces the processor demand of software-based mpeg-2 d ecoding, and thus improves system performance. the motion compensation functiona lity is overloaded onto the text ure cache and texture filter. the texture cache is used to typically access the da ta in the reconstruction of the frames and the filter is used in the actual motion compensation process. to support this overloaded functionality the texture cache additionally support the yuv420 planar input formats. 12.6.6.2 sub-picture support sub-picture is used for two purposes; one is subtitles for movie captions, etc. (that are superimposed on a main picture), and the other is menus used to provide some visual operation environments the user of a content player. dvd allows movie subtitles to be recorded as s ub-pictures. on a dvd disc, it is called "subtitle" because it has been prepared for storing captions. since the disc can have a maximum of 32 tracks for subtitles, they can be used for various applications, for example, as subtitles in different languages or other information to be displayed. there are two kinds of menus; the system menus and other in-title menus. first, the system menus are displayed and operated at startup of or during the playback of the disc or from the stop state. second, in-title menus can be programmed as a combination of s ub-picture and highlight commands to be displayed during playback of the disc. the gmch supports sub-picture for dvd and dbs by mixing the two video streams via alpha blending. unlike color keying, al pha blending provides a softer e ffect and each pixel that is displayed is a composite between the two video stream pixels. the gmch can use four methods when dealing with sub-pictures. the flexibility enables the gmch to work with all sub- picture formats. functional description r datasheet 245 12.6.7 planes a plane consists of rectangular shaped image that has characteristics such as source, size, position, method, and format. these planes get a ttached to source surfaces, which are rectangular memory surfaces with a similar set of characteristics. they are also associated with a particular destination pipe. 12.6.7.1 cursor plane the cursor planes are one of the simplest displa y planes. with a few exceptions, the cursor plane has a fixed size of 64x64 and a fixed z-order (top). in legacy modes, cursor can cause the display data below it to be inverted. 12.6.7.2 overlay plane the overlay engine provides a method of merging either video capture data (from an external video capture device) or data delivered by the processor, with the graphics data on the screen. the source data can be mirrored horizontally or vertically or both. source/destination color keying/chromakeying overlay source/destination chromakeying enables blending of the overlay with the underlying graphics background. destination color keying/ chromakeying can be used to handle occluded portions of the overlay window on a pixel by pixel basis that is actually an underlay. destination chromakeying would only be used for yuv passthrough to tv. destination color keying supports a specific color (8- or 15-bit) mode as well as 32-bit alpha blending. source color keying/chromakeying is used to handle transparency based on the overlay window on a pixel by pixel basis. this is used when ?b lue screening? an image to overlay the image on a new background later. gamma correction to compensate for overlay color intensity loss due to the non-linear response between display devices, the overlay engine supports independent ga mma correction. this allows the overlay data to be converted to linear data or corrected for the display device when not blending. yuv to rgb conversion the format conversion can be bypassed in the case of rgb source data. the format conversion assumes that the yuv data is input in the 4:4:4 format and uses the full range scale. maximum resolution and frequency the maximum frequency supported by the overlay logic is 180 mhz. the maximum resolution is dependent on a number of variables (e.g., memory speed, memory latency, port selected, pipe selected, mode definition). functional description r 246 datasheet deinterlacing support for display on a progressive computer monitor, inte rlaced data that has been formatted for display on interlaced monitors (tv) needs to be de-inter laced. the simple appro aches to de-interlacing create unwanted display artifacts. more advanced de-interlacing techniques have a large cost associated with them. the compro mise solution is to provide a low cost but effective solution and enable both hardware and software based external solutions. software based solutions are enabled through a high bandwidth transfer to system memory and back. 12.6.7.3 advanced deinterlacing and dynamic bob and weave interlaced data that originates from a video camera cr eates two fields that ar e temporally offset by 1/60 of a second. there are several schemes to deinterlace the video stream: line replication, vertical filtering, field merging, and vertical te mporal filtering. field merging takes lines from the previous field and inserts them into the current field to construct the frame; this is known as weaving. this is the best solution for images with little motion however, showing a frame that consists of the two fields will have serration or feathering of moving edges when there is motion in the scene. vertical filtering or ?bob? interpol ates adjacent lines rather than replicating the nearest neighbor. this is the best solution for im ages with motion; however, it will have reduced spatial resolution in areas that have no motion and introduces aliasing. in the absence of any other deinterlacing, these form the baseline and are supported by the gmch. scaling filter and control the scaling filter has three vertical taps and five horizontal taps. arbitrary scaling (per pixel granularity) for any video source (yuv422 or yuv420) format is supported. the overlay logic can scale an input image up to 1600x1200with no major degradation in the filter used as long as the maximum frequency limitati on is met. display resolution and refresh rate combinations where the dot clock is greater than the maximum frequency require the overlay to use pixel replication. 12.6.8 pipes the display consists of two pipes. the pipes can operate in a single-wide or ?double-wide? mode at 2x graphics core clock though they are effectively limited by the respective display port. the display planes and the cursor plane will provi de a ?double wide? mode to feed the pipe. 12.6.8.1 clock generator units (dpll) the clock generator units provide a stable freque ncy for driving display devices. it operates by converting an input reference frequency into an output frequency. the timing generators take their input from internal dpll devices that are programmable to generate pixel clocks in the range of 25?400 mhz. accuracy for vesa timing modes is required to be within 0.5%. the dpll can take a reference frequency from the external reference input (drefclkinn/p), the tv clock input (tvclkin). functional description r datasheet 247 12.7 display interfaces (intel ? 82915g/82915gv/82915GL/ 82910gl gmch only) the gmch has three display ports; one analog and two digital. each port can transmit data according to one or more protocols. the digital ports are connected to an external device that converts one protocol to another. examples of this are tv encoders, external dacs, lvds transmitters, and tmds transmitters. each display port has control signals that may be used to control, configure and/or determine the capabilities of an external device. the analog port is a dedicated port ( not multiplexed) on the 82915gv/82915GL/82910gl gmch. for the 82915g gmch, the sdvo ports b a nd c are multiplexed with the pci express graphics interface and are not available if an extern al pci express graphics device is in use. when a 915g express chipset system uses a pci express graphics connector, sdvo ports b and c can be used via an add2 (advanced digital display 2) card. ports b and c can also operate in dual- channel mode, where the data bus is connected to both display ports, allowing a single device to take data at twice the pixel rate. ? the gmch?s analog port uses an integrated 400 mhz ramdac that can directly drive a standard progressive scan analog monitor up to a resolution of 2048x1536 pixels with 32-bit color at 85 hz. ? the gmch?s sdvo ports are each capable of driving a 200-mp pixel rate. each port is capable of driving a digital display up to 1600x1200 @ 60hz. when in dual-channel mode, the gmch can drive a flat panel up to 2048x1536 @ 85 hz or dcrt/hdtv up to 1920x1080 @ 85 hz. the gmch is compliant with dvi specification 1.0. when combined with a dvi compliant external device and connector, the gmch has a high speed interface to a digital display (e.g., flat panel or digital crt). functional description r 248 datasheet table 12-6. display port characteristics analog digital port b digital port c interface protocol rgb dac dvo 1.0 dvo 1.0 hsync yes enable/polarity vsync yes enable/polarity blank no yes 1 yes 1 stall no yes yes field no yes yes signals display_enable no no 1 image aspect ratio programmable and typically 1.33:1 or 1.78:1 pixel aspect ratio square voltage rgb 0.7 v p-p pci express* pci express* clock na differential max rate 400 mpixel 200/400 mpixel format analog rgb rgb 8:8:8 yuv 4:4:4 control bus ddc1/ddc2b ddc2b external device no tmds/lvds transmitter /tv encoder connector vga/dvi-i dvi/cvbs/s-video/component/scart notes: 1. single signal software selectabl e between display enable and blank#. functional description r datasheet 249 12.7.1 analog display port characteristics the analog display port provides a rgb signal output along with a hsync and vsync signal. there is an associated ddc signal pair that is implemented using gpio pins dedicated to the analog port. the intended target device is for a crt based monitor with a vga connector. display devices (such as lcd panels) with analog inputs may work satisfactory but no functionality has been added to the signals to enhance that capability. table 12-7. analog port characteristics signal port characteristic support voltage range 0.7 v p-p only monitor sense analog compare analog copy protection no rgb sync on green no voltage 2.5 v enable/disable port control polarity adjust vga or port control composite sync support no special flat panel sync no hsync vsync stereo sync no voltage externally buffered to 5v ddc control through gpio interface 12.7.1.1 integrated ramdac the display function contains a ram-based digital-to-analog converter (ramdac) that transforms the digital data from the graphics and video subsystems to analog data for the crt monitor. the gmch?s integrated 400 mhz ramdac supports resolutions up to 2048 x 1536 @ 85hz. three 8-bit dacs provide the red, green, and blue signals to the monitor. 12.7.1.2 sync signals hsync and vsync signals are dig ital and conform to ttl signal levels at the connector. since these levels cannot be generated internal to the de vice, external level shifting buffers are required. these signals can be polarity adjusted and individually disabled in one of the two possible states. the sync signals power up disabled in the high state. no composite sync or special flat panel sync support is included. 12.7.1.3 vesa/vga mode vesa/vga mode provides compatibility for pre-ex isting software that set the display mode using the vga crtc registers. timings are genera ted based on the vga register values and the timing generator registers are not used. functional description r 250 datasheet 12.7.1.4 ddc (display data channel) ddc is a standard defined by vesa. its purpose is to allow communication between the host system and display. both configuration and cont rol information can be exchanged allowing plug- and-play systems to be realized. support for ddc 1 and 2 is implemented. the gmch uses the ddc_clk and ddc_data signals to communicate with the analog monitor. the gmch generates these signals at 2.5 v. external pull- up resistors and level shifting circuitry should be implemented on the board. the gmch implements a hardware gmbus controlle r that can be used to control these signals allowing for transactions speeds up to 400 khz. 12.7.2 digital display interface the gmch has several options for driving di gital displays. the gmch contains two sdvo ports that are multiplexed on the pci express* x16 graphics interface. when an external pci express* x16 graphics interface graphics accelerat or is not present, the gmch can use the multiplexed sdvo ports to provide extra digital di splay options. these additional digital display capabilities may be provided through an add2 card that is designed to plug in to a pci express connector. 12.7.2.1 digital display cha nnels ? sdvob and sdvoc the gmch has the capability to support digital display devices through two sdvo ports. when an external graphics accelerator is used via th e pci express* x16 graphics interface port, these sdvo ports are not available. the shared sdvo ports each support a pixel cloc k up to 200 mhz and can support a variety of transmission devices. when using a dual-channel external transmitter, it will be possible to pair the two sdvo ports in dual-channel mode to support a single digital display with higher resolutions and refresh rates. in this mode, gmch is capable of driving pixel clock up to 400 mhz. sdvo_ctrldata is an open-drain signal that will act as a strap during reset to tell the gmch whether the interface is a pci express interf ace or an sdvo interface. when implementing sdvo, either via add2 cards or with a down devi ce, a pull-up is placed on this line to signal to the gmch to run in sdvo mode and for proper gmbus operation. 12.7.2.2 add2 card when a 915g express chipset platform uses a pci express* x16 graphics interface connector, the multiplexed sdvo ports may be used via an add2 card. the add2 card will be designed to fit a standard pci express (x16) connector. 12.7.2.2.1 tmds capabilities the gmch is compliant with dvi specification 1.0. when combined with a dvi compliant external device and connector, the gmch has a high speed interface to a digital display (e.g., flat panel or digital crt). when comb ining the two multiplexed sdvo ports, the gmch can drive a flat panel up to 2048x1536 or a dcrt/hdtv up to 1920x1080. flat panel is a fixed resolution display. the gmch supports panel fitti ng in the transmitter, r eceiver or an external functional description r datasheet 251 device, but has no native panel fitting capabilities. the gmch will, however, provide unscaled mode where the display is centered on the panel. 12.7.2.2.2 lvds capabilities the gmch may use the multiplexed sdvo ports to drive a lvds transmitter. flat panel is a fixed resolution display. the gm ch supports panel fitting in th e transmitter, receiver or an external device, but has no native panel fitting capabilities. the gmch will, however, provide unscaled mode where the display is centered on the panel. the gmch supports scaling in the lvds transmitter through the sdvo stall input pair. 12.7.2.2.3 tv-out capabilities although traditional tvs are not digital displays, the gmch uses a digital display channel to communicate with a tv-out transmitter. for that reason, the gmch considers a tv-output to be a digital display. gmch supports ntsc and pal standard definiti on formats. the gmch generates the proper timing for the external enc oder. the external encoder is responsible for generation of the proper format signal. since the multiplexed sdvo interface is a ntsc/pal/secam display on the tv-out port , it can be configured to be the boot device. it is necessary to ensure that appropriate bios support is provided. if easylink is supported in the gmch, then this mechanism could be used to interrogate the display device. the tv-out interface on the gmch is addressable as a master device. this allows an external tv encoder device to drive a pixel clock signal on sdvo_tvclk[+/-] that the gmch uses as a reference frequency. the frequency of this clock is dependent on the output resolution required. flicker filter and overscan compensation the overscan compensation scaling and the flicker f ilter is done in the external tv encoder chip. care must be taken to allow for support of tv sets with high performance de-interlacers and progressive scan displays connected to by way of a non-interlaced signal. timing will be generated with pixel granularity to allo w more overscan ratios to be supported. direct yuv from overlay when source material is in the yuv format and is destined for a device that can take yuv format data in, it is desired to send the data without converting it to rgb. this avoids the truncation errors associated with multiple color conversi on steps. the common situation will be that the overlay source data is in the yuv format and will bypass the conversion to rbg as it is sent to the tv port directly. sync lock support sync lock to the tv will be done using the exte rnal encoders pll comb ined with the display phase detector mechanism. the availability of this feature will be used to determine which external encoder is in use. functional description r 252 datasheet analog content protection analog content protection is provided through the external encoder using macrovision 7.01. dvd software must verify the presence of a macrovision tv encoder before playback continues. simple attempts to disable the macrovision operation must be detected. connectors target tv connectors support includes the cvbs, s-video, component, and scart connectors. the external tv encoder in use w ill determine the method of support. 12.7.2.2.4 control bus communication to sdvo registers and if u tilized, add2 proms and monitor ddcs, are accomplished by using the sdvo_ctrldata and sdvo_ctrlclk signals through the sdvo device. these signals run up to 1 mhz and connect directly to the sdvo device. the sdvo device is then responsible for routing the ddc and prom data streams to the appropriate location. consult sdvo device datasheets for le vel shifting requirements of these signals. intel ? sdvo modes the port can be dynamically configured in several modes: ? standard ? this mode provides baseline sdvo functionality. the mode supports pixel rates between 25 and 200 mp/s. it uses three data pairs to transfer rgb data. ? extended (82915g only) ? this mode adds al pha support to data stream. extended mode supports pixel rates between 25 mhz and 200 mp/s. the mode uses four data channels and is only supported on sdvob. it leverages channel c (sdvoc) red pair as the alpha pair for channel b (sdvob). ? dual standard ? this mode uses standard data stream s across both sdvob and sdvoc. both channels can only run in standard mode (3 data pairs) and each channel supports pixel rates between 25 and 200 mp/s. ? dual independent sta ndard (82915g only) - in dual i ndependent standard mode, each sdvo channel will see a different pixel str eam. the data stream across sdvob will not be the same as the data stream across sdvoc. this mode is only supported on the 82915g/82915gv/82915GL/82910gl gmch. ? dual simultaneous standard - in dual simultaneous standa rd mode, both sdvo channels will see the same pixel stream. the data stream across sdvob will be the same as the data stream across sdvoc. the display timings will be identi cal, but the transfer timings may not be (i.e., sdvob clocks and data may not be perfectly aligned with sdvoc clock and data as seen at the sdvo devi ce(s)). since this uses just a single data stream, it uses a single pixel pipeline within the gmch. 12.7.3 multiple display configurations microsoft windows* 2000 and windows* xp opera ting systems have enabled support for multi- monitor display. since the gmch has several display ports available for its two pipes, it can support up to two different images on different di splay devices. timings and resolutions for these two images may be different. the gmch supports intel dual display clone, intel dual display twin, and extended desktop. functional description r datasheet 253 intel dual display clone uses both display pipes to drive the same content, at the same resolution and color depth to two different displays. this c onfiguration allows for di fferent refresh rates on each display. intel dual display twin uses one of the display pipes to drive the same content, at the same resolution, color depth, and refresh rates to two different displays. extended desktop (82915g only) uses both display pipes to drive different content, at potentially different resolutions, refresh rates, and color depths to two different displays. this configuration allows for a larger windows desktop by using both displays as a work surface. note: the gmch graphics engine is also incapable of operating in parallel with an external pci express graphics device. the gmch graphics e ngine can, however, work in conjunction with a pci graphics adapter. 12.8 power management power management capabilities of the (g)mch include the following: ? acpi 1.0b support ? acpi s0, s3, s4, s5, c0, c1, c2, c3, c4 ? enhanced power management state transitions for increasing time the processor spends in low power states ? internal graphics display de vice control d0, d1, d2, d3 (82915g/82915gv/82915GL/82910gl gmch only) ? graphics adapter states: d0, d3. ? pci express link states: l0, l0s, l1, l2/l3 ready, l3 ? conditional memory self-refresh during c2, c3, and c4 states 12.9 clocking the (g)mch has a total of 5 plls providing the internal clocks. the plls are: ? host pll ? this pll generates the main core clocks in the host clock domain. the host pll is used to generate memory and internal gr aphics core clocks. it uses the host clock (h_clkin) as a reference. ? pci express pll (82915g/92915p/82915pl (g)mch only) ? this pll generates all pci express related clocks, including the direct media interface that connects to the ich6. this pll uses the 100 mhz (g_clkin) as a reference. ? display pll a pll (82915g/92915gv/82915GL/82910gl gmch only) ? this pll generates the internal clocks for display a. it uses d_refclkin as a reference. ? display pll b (82915g/92915gv/82915GL/82910gl gmch only) ? this pll generates the internal clocks for display b. it uses d_refclkin as a reference. figure 12-3 illustrates the various clocks in the platform. functional description r 254 datasheet figure 12-3. system clocking example ck410 48pin ssop ck410 56pin ssop it p pci express gfx fwh lpc processor processor diff pair pci express dev 14.000 mhz processor diff pair processor diff pair di ff pai r pci express diff pair pci express diff pair pci express dev pci express dev pci express dev pci express diff pair pci express diff pair pci express diff pair pci express diff pair pci express diff pair sata diff pair 25 mhz diff pair pci slot port80 pci glue chip pci slot pci slot 96 mhz dot diff pair pci 33 mhz pci 33 mhz pci 33 mhz pci 33 mhz pci 33 mhz pci 33 mhz pci 33 mhz pci 33 mhz memory slot 0 slot 1 slot 2 slot 3 lan sio lpc pci 33 mhz ref 14 mhz 25 mhz 66 mhz diff pair 32.768 khz 48 mhz usb main pll ssc sata pll ssc 48/14 mhz pll 66/33 buffer 25 mhz oscillator 66 mhz 66 mhz 66 mhz lci bit clock ac97 ref 14 mhz high def audio bit clock tpm lpc pci 33 mhz hpll mpll dpll dpll 4 x1 pci exp dmi x16 pci exp usb pll sata pll pci express pll high def audi o pci slot pci slot pci slot pci 33 mhz pci 33 mhz ref 14 mhz 24 mhz bit cl ock osc (g)mch intel ? ich6 pci express pll electrical characteristics r datasheet 255 13 electrical characteristics this chapter contains the (g)m ch absolute maximum electrical ratings, power dissipation values, and dc characteristics. 13.1 absolute maximum ratings table 13-1 lists the (g)mch?s maximum environm ental stress ratings. functional operation at the absolute maximum and minimum is neither implied nor guaranteed. functional operating parameters are listed in the dc characteristics tables. warning: stressing the device beyond the ?absolute maximum ratings? may cause permanent damage. these are stress ratings only. operating bey ond the ?operating conditi ons? is not recommended and extended exposure bey ond ?operating conditions? may affect reliability. table 13-1. absolute maximum ratings symbol parameter min max uni t notes t storage storage temperature -55 150 c 1 (g)mch core vcc 1.5 v core supply voltage with respect to v ss -0.3 1.65 v host interface (533 mhz/800 mhz) vtt 1.2 v system bus input voltage with respect to v ss -0.3 1.65 v vcca_hpll 1.5 v host pll analog supply voltage with respect to v ss -0.3 1.65 v ddr interface (333 mhz/400 mhz) vccsm (ddr) 2.6 v ddr system memory supply voltage with respect to v ss -0.3 4.0 v vcca_smpll (ddr) 1.5 v system memory pll analog supply voltage with respect to v ss -0.3 1.65 v ddr2 interface (400 mhz/533 mhz) vccsm (ddr2) 1.8 v ddr2 system memory supply voltage with respect to v ss -0.3 4.0 v vcca_smpll (ddr2) 1.5 v system memory pll analog supply voltage with respect to v ss -0.3 1.65 v electrical characteristics r 256 datasheet symbol parameter min max uni t notes pci express*/intel ? sdvo/dmi interface vcc_exp 1.5 v pci express and dmi supply voltage with respect to v ss -0.3 1.65 v vcca_exppll 1.5 v pci express pll analog supply voltage with respect to v ss -0.3 1.65 v rgb/crt dac display interface (8 bit) (intel ? 82915g/82915gv/82910gl gmch only) vcca_dac 2.5 v display dac analog supply voltage with respect to v ss -0.3 2.65 v vcca_dplla 1.5 v display pll a analog supply voltage with respect to v ss -0.3 1.65 v vcca_dpllb 1.5 v display pll b analog supply voltage with respect to v ss -0.3 1.65 v cmos interface vcc2 2.5 v cmos supply voltage with respect to v ss -0.3 2.65 v notes: 1. possible damage to the (g)mch may occur if the (g)mch temperature exceeds 150 c. intel does not guarantee functionality for parts that have exceeded temperatures above 150 c due to specification violation. electrical characteristics r datasheet 257 13.2 power characteristics table 13-2. non-memory power characteristics symbol parameter signal names min typ max unit notes i vtt 1.2 v system bus supply bus current vtt ? ? 1.0 a 1, 4 i vcc 1.5 v core supply current (integrated) vcc ? ? 9.7 a 2,3,4 i vcc 1.5 v core supply current (discrete) vcc ? ? 7.7 a 2,3,4 i vcc_exp 1.5 v pci express and dmi supply current vcc_exp ? ? 1.4 a i vcca_dac 2.5 v display dac analog supply current vcca_dac ? ? 70 ma i vcc2 2.5 v cmos supply current vcc2 ? ? 2 ma i vcca_exppll 1.5 v pci express and dmi pll analog supply current vcca_exppl l ? ? 45 ma i vcca_hpll 1.5 v host pll supply current vcca_hpll ? ? 45 ma i vcca_dplla i vcca_dpllb 1.5 v display pll a and pll b supply current vcca_dplla vcca_dpllb ? ? 55 ma notes: 1. estimate is only for max current coming through chipset?s supply balls 2. rail includes pll current 3. includes worst case leakage 4. calculated for highest frequencies electrical characteristics r 258 datasheet table 13-3. ddr power characteristics symbol parameter min max unit notes i vccsm (ddr) ddr system memory interface (2.6 v) supply current ? 4.1 a i sus_vccsm (ddr) ddr system memory interface (2.6 v) standby supply current ? 25 ma i smvref (ddr) ddr system memory interface reference voltage (1.3 v) supply current ? 10 a i sus_smvref ddr system memory interface reference voltage (1.3 v) standby supply current ? 10 a i ttrc (ddr) ddr system memory interface resistor compensation voltage (2.6 v) supply current ? 42 ma i sus_ttrc (ddr) ddr system memory interface resistor compensation voltage (2.6 v) standby supply current ? 0 a i vcca_smpll (ddr) system memory pll analog (1.5 v) supply current ? 60 ma table 13-4. ddr2 power characteristics symbol parameter min max unit notes i vccsm (ddr2) ddr2 system memory interface (1.8 v) supply current ? 4.7 a i sus_vccsm (ddr2) ddr2 system memory interface (1.8 v) standby supply current ? 25 ma i smvref (ddr2) ddr2 system memory interface reference voltage (0.90 v) supply current ? 10 a i sus_smvref (ddr2) ddr2 system memory interface reference voltage (0.90 v) standby supply current ? 10 a i ttrc (ddr2) ddr2 system memory interface resister compensation voltage (1.8 v) supply current ? 32 ma i sus_ttrc (ddr2) ddr2 system memory interface resister compensation voltage (1.8 v) standby supply current ? 0 a i vcca_smpll (ddr2) system memory pll analog (1.5 v) supply current ? 60 ma electrical characteristics r datasheet 259 13.3 signal groups the signal description includes the type of buffer used for the particular signal: gtl+ open drain gtl+ interface signal. refer to the gtl+ i/o specification for complete details. the (g)mch integrates most gtl+ termination resistors. ddr ddr system memory (2.6 v cmos buffers) ddr2 ddr2 system memory (1.8 v cmos buffers) pci express/sdvo pci express interface signals. these signals are compatible with pci express 1.0a signaling environment ac specifications. the buffers are not 3.3 v tolerant. analog analog signal interface ref voltage reference signal hvcmos 2.5 v tolerant high voltage cmos buffers sstl-2 2.6 v tolerant stub series termination logic sstl-1.8 1.8 v tolerant stub series termination logic table 13-5. signal groups signal group signal type signals notes host interface signal groups (a) gtl+ input/outputs hads#, hbnr#, hbreq0#, hdbsy#, hdrdy#, hdinv[3:0]#, ha[31:3]#, hadstb[1:0]#, hd[63:0], hdstbp[3:0]#, hdstbn[3:0]#, hhit#, hhitm#, hreq[4:0]#, hlock# (b) gtl+ common clock outputs hbpri#, hcpurst#, hdefer#, htrdy#, hrs[2:0]#, hdpwr#, hedrdy# (c) gtl+ asynchronous input bsel[2:0], hpcreq# (d) analog host i/f ref & comp. signals hvref, hswing hrcomp, hscomp pci-express graphics and sdvo interface signal groups (e) pci express/sdvo input pci express interface (82915g/82915p/82915pl (g)mch only): exp_rxn[15:0], exp_rxp[15:0], sdvo interface ( 82915g/82915gv/82915GL/82910gl gmch only): sdvo_tvclkin#, sdvo_tvclkin, sdvob_int#, sdvob_int, sdvo_stall#, sdvo_stall, sdvoc_int#, sdvoc_int electrical characteristics r 260 datasheet signal group signal type signals notes (f) pci express/sdvo output pci express interface (82915g/82915p/82915pl (g)mch only): exp_txn(15:0), exp_txp(15:0) sdvo interface ( 82915g/82915gv/82915GL/82910gl gmch only): sdvob_red#, sdvob_red, sdvob_green#, sdvob_green, sdvob_blue#, sdvob_blue, sdvob_clk, sdvob_clk#, sdvoc_red#/sdvob_alpha#, sdvoc_red/sdvob_alpha, sdvoc_green#, sdvoc_green sdvoc_blue#, sdvoc_blue, sdvoc_clk, sdvoc_clk# (g) analog pci express / sdvo interface compensation signals exp_comp0 exp_compi ddr interface signal groups (h) sstl- 2 ddr cmos i/o sdq_a[63:0], sdq_b[63:0], sdqs_a[7:0], sdqs_b[7:0] (i) sstl ? 2 ddr cmos output sdm_a[7:0], sdm_b[7:0], sma_a[13:0], sma_b[13:0], sbs_a[1:0], sbs_b[1:0], sras_a#, sras_b#, scas_a#, scas_b#, swe_a#, swe_b# scke_a[3:0], scke_b[3:0], scs_a[3:0]#, scs_b[3:0]#, sclk_a[5:0], sclk_a[5:0]#, sclk_b[5:0], sclk_b[5:0]# (j) ddr reference voltage smvref[1:0] (ddr) ddr2 interface signal groups (intel ? 82915g/82915gv gmch and 82915p mch only) (k) sstl ? 1.8 ddr2 cmos i/o sdq_a[63:0]#, sdq_b[63:0]#, sdqs_a[7:0], sdqs_a[7:0]#, sdqs_b[7:0]#, sdqs_b[7:0]# (l) sstl ? 1.8 ddr2 cmos output sdm_a[7:0], sdm_b[7:0], sma[13:0], sma_b[13:0], sbs_a[2:0], sbs_b[2:0], sras_a#, sras_b#, scas_a#, scas_b#, swe_a#, swe_b#, sodt_a[3:0], sodt_b[3:0], scke_a[3:0], scke_b[3:0], scs_a[3:0]#, scs_b[3:0]#, sclk_a[5:0], sclk_a[5:0]#, sclk_b[5:0], sclk_b[5:0]# (m) ddr2 reference voltage smvref[1:0] (ddr2) electrical characteristics r datasheet 261 signal group signal type signals notes rgb/crt dac display signal groups (intel ? 82915g/82915gv/82915GL/82910gl gmch only) analog current outputs red, red#, green, green#, blue, blue# analog/ref dac miscellaneous refset current mode reference pin. dc spec. not required cmos type hsync, vsync clocks, reset, and miscellaneous signal groups (n) hvcmos input extts# (n1) miscellaneous inputs rstin#, pwrok (0) low voltage diff. clock input hclkn, hclkp, drefclkp, drefclkn, gclkp, gclkn (p) hvcmos i/o sdvo_crtlclk, sdvo_ctrldata, ddc_clk, ddc_data i/o buffer supply voltages (q) 1.2 v system bus input supply voltage vtt (r) 1.5 v sdvo, pci express supply voltages vcc_exp (s) 2.6 v ddr supply voltage vccsm (ddr) (t) 1.8 v ddr2 supply voltage vccsm (ddr2) (u) 1.5 v ddr pll analog supply voltage vcca_smpll (ddr) (v) 1.5 v ddr2 pll analog supply voltage vcca_smpll (ddr2) (w) 1.5 v (g)mch core supply voltage vcc (x) 2.5 v cmos supply voltage vcc2 (y) 2.5 v rgb/crt dac display analog supply voltage vcca_dac (z) pll analog supply voltages vcca_hpll, vcca_exppll, vcca_dplla, vcca_dpllb electrical characteristics r 262 datasheet 13.4 dc characteristics 13.4.1 general dc characteristics table 13-6. dc characteristics 3 symbol signal group parameter min nom max unit notes i/o buffer supply voltage (ac noise not included) vccsm (ddr) (s) ddr i/o supply voltage 2.5 2.6 2.7 v vccsm (ddr2) (t) ddr2 i/o supply voltage 1.7 1.8 1.9 v vcca_smpll (ddr) (u) ddr i/o pll analog supply voltage 1.425 1.5 1.575 v vcca_smpll (ddr2) (v) ddr2 i/o pll analog supply voltage 1.425 1.5 1.575 v vcc_exp (r) sdvo, pci-express supply voltage 1.425 1.5 1.575 v vtt (q) system bus input supply voltage 1.09 1.2 1.26 v vcc (w) (g)mch core supply voltage 1.425 1.5 1.575 v vcc2 (x) cmos supply voltage 2.375 2.5 2.625 v vcca_dac (y) crt display dac supply voltage 2.375 2.5 2.625 v vcca_hpll, vcca_exppll, vcca_dplla, vcca_dpllb (z) various pll?s analog supply voltages 1.425 1.5 1.575 v reference voltages hvref (d) host address, data, and common clock signal reference voltage 2/3 x v tt1 ? 2% 2/3 x v tt 2/3 x v tt + 2% v hswing (d) host compensation reference voltage 1/4 x v tt ? 2% 1/4 x vtt 1/4 x v tt + 2% v smvref (ddr) (j) ddr reference voltage 0.50 x vccsm(ddr) ? 0.05 0.50 x vccsm (ddr) 0.50 x vccsm(ddr) + 0.05 v smvref (ddr2) (m) ddr2 reference voltage 0.49 x vccsm (ddr2) 0.50 x vccsm (ddr2) 0.51 x vccsm (ddr2) v host interface v il_h (a, c) host gtl+ input low voltage -0.10 0 (2/3 x v tt ) ? 0.1 v v ih_h (a, c) host gtl+ input high voltage (2/3 x v tt ) + 0.1 v tt v tt + 0.1 v electrical characteristics r datasheet 263 symbol signal group parameter min nom max unit notes v ol_h (a, b) host gtl+ output low voltage ? ? (0.25 x v tt )+0.1 v v oh_h (a, b) host gtl+ output high voltage v tt ? 0.1 ? v tt v i ol_h (a, b) host gtl+ output low current ? ? v ttmax / (1-0.25)rttmin ma rtt min = 54 ? i leak_h (a, c) host gtl+ input leakage current ? ? 20 a v ol electrical characteristics r 266 datasheet ballout and package information r datasheet 267 14 ballout and package information the (g)mch ballout supports platforms using ddr2 and ddr system memory. the (g)mch?s system memory interface ballout diffe rs between ddr2 and ddr modes. note: the ddr and ddr2 signals are multiplexed so that they are supported on the same package. 14.1 ddr2 ballout figure 14-1, figure 14-2, and figure 14-3 show the 82915g gmch ballout for platforms using ddr2 system memory, as viewed from the top side of the package. figure 14-1 shows columns 1?12; figure 14-2 shows columns 13?24; figure 14-3 shows columns 25?35. the complete ddr2 ballout for the 82915g/82915gv/82910gl gmch and 82915p mch are listed in table 14-1 and table 14-2. table 14-1 is sorted by ball number. table 14-2 is sorted alphabetically by signal name based on the signal names of the 82915g gmch. note that the first table has more entries than the second table. the second table does not include unpopulated balls whereas the first table does. note: balls that are listed as rsv are reserved. board traces should not be routed to these balls. note: balls that are listed as nc are no connects. boar d traces to these balls are permitted as specified. ballout and package information r 268 datasheet figure 14-1. intel ? 82915g gmch ballout for ddr2 (top view: columns 1?12) 1 2 3 4 5 6 7 8 9 10 11 12 a nc vss vss exp_txn3 exp_txp3 exp_txn1 exp_txp1 vss gclkp vcca_ dplla b nc vss exp_rxp4 exp_rxn4 vss vss vss vss vss vss gclkn vss c vss exp_txp5 vss vss exp_txn4 exp_txp4 exp_ txn2 exp_txp2 exp_txn0 exp_txp0 vss d exp_txn5 vss vss exp_rxp5 vss vss vss vss vss vss vsync e vss vss exp_txp6 vss exp_rxn5 vss exp_rxn3 vss exp_rxn2 vss exp_rxp0 hsync f exp_txp7 vss exp_txn6 vss vss vss exp_rxp3 vss exp_rxp2 vss exp_rxn0 nc g exp_txn7 vss exp_txp8 vss exp_rxn6 exp_rxp6 vss vss vss vss vss nc h exp_txp9 vss exp_txn8 vss vss vss exp_rxn7 exp_rxp7 vss vss exp_rxn1 nc j exp_txn9 vss exp_ txp10 vss exp_rxn8 exp_rxp8 vss vss vss vss exp_rxp1 nc k exp_ txp11 vss exp_ txn10 vss vss vss exp_rxn9 exp_rxp9 vss vss vss nc l exp_ txn11 vss exp_ txp12 vss exp_ rxn10 exp_ rxp10 vss vss vss vcc vss nc m exp_ txp13 vss exp_txn1 2 vss vss vss exp_ rxn12 exp_ rxp12 vss vss vss drefclkn n exp_ txn13 vss exp_ txp14 vss exp_ rxn13 exp_ rxp13 vss vss vss vss vss nc p exp_ txp15 vss exp_ txn14 vss vss vss exp_ rxp14 exp_ rxn14 vss exp_ rxp11 vss nc r exp_ txn15 vss dmi_txp0 vss exp_ rxn15 exp_ rxp15 vss vss vss exp_ rxn11 vss nc t dmi_txp1 vss dmi_txn0 vss vss vss vss dmi_rxn1 dmi_rxp1 vss vss nc u dmi_txn1 vss dmi_txp2 vss dmi_rxp0 dmi_rxn0 vss vss vss dmi_rxn3 vss nc v vss vss dmi_txn2 vss dmi_txp3 vss dmi_rxp2 dmi_rxn2 vss dmi_rxp3 vss nc w vcc_exp vcc_exp vcc_exp vcc_exp dmi_txn3 vcc_exp vcc_exp vcc_exp vcc_exp exp_ compi vss nc y vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp exp_ compo vss nc aa vss vss vss vss vss vss vss vss vss vss vss nc ab vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc nc ac vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc rsv ad vcc vcc vcc vcc v cc vcc vcc vcc vcc vcc vss sdq_b20 ae sdq_a5 sdq_a4 sdq_a0 vss so comp1 vss smvref0 smvref1 vss sm_slew out1 sdq_b11 vss af vss sdm_a0 sdq_a1 vss socomp0 vss rstin# vss sm_ slewin1 vss sdq_b10 vss ag sdqs_a0 sdqs_a0# sdq_a6 srcomp0 vss nc pwrok srcomp1 sdq_b4 sdq_b14 sdq_b15 vss ah vss sdq_a7 sdq_a2 sdq_ b0 vss vss sdq_b5 vss sdm_b1 sdqs_b1# vss sdq_b17 aj sdq_a12 sdq_a3 sdq_a13 vss sdm_b0 sd q_b1 sdq_b12 sdq_b8 vss vss sclk_b4 sm_ slewin0 ak vss sdq_a8 sdq_a9 vss sdqs_b 0 vss vss vss sclk_b1 sdqs_b1 vss sm_slew out0 al sdm_a1 sdqs_a1# sdqs_a1 sdqs_b 0# sdq_b6 sdq_b2 sdq_b13 sdq_ b9 sclk_b1# vss sclk_b4# sma_b7 am sclk_a1 sclk_a1# vss sdq_b7 vss vss vss scke_b3 vccsm vccsm sma_b5 an vss sclk_a4# sclk_a4 sdq_a10 sdq_a20 sdq_b3 sdm_a2 sdq_a22 sdq_a19 scke_b1 sbs_b2 ap nc sdq_a14 sdq_a15 sdq_a11 sdq_a21 sdq_a17 sdqs_a2 vss sdq_a18 scke_b0 sma_b11 vccsm ar nc nc vss sdq_a16 vss sdqs_a2# sdq_a23 scke_b2 vccsm sma_b12 sma_b9 1 2 3 4 5 6 7 8 9 10 11 12 ballout and package information r datasheet 269 figure 14-2. intel ? 82915g gmch ballout for ddr2 (top view: columns 13?24) 13 14 15 16 17 18 19 20 21 22 23 24 a vcc2 vcca_ exppll refset exp_slr vcca_ hpll vss vtt vtt vtt vtt hswing hvref b vcca_ dpllb vss rsv vss vcca_ smpll vss vtt vtt vtt vtt hrcomp vss c vss rsv mtype nc vss vss vtt vtt vtt vtt vss d vcca_dac green vss vss bsel2 vss vtt vtt vtt vtt vss hscomp e vcca_dac green# bsel1 nc vss vss vtt vtt vtt vtt vss hd62 f vssa_dac red rsv vss hd47 vss hdstbn2# vtt vtt vtt vss nc g vss red# vss rsv vss hd45 vss vss vtt vtt vss hcpurst# h vss blue nc bsel0 nc hd46 hd41 hd40 vss vtt hd37 vss j sdvo_ ctrlclk blue# vss vss vss vss hdstbp2# vss hd35 hd32 vss hd33 k sdvo_ ctrldata vss rsv extts# hd44 hd43 hdinv2# vss hd39 hd34 hd31 vss l vss ddc_data vss vss vss vss nc vss vss vss hd30 vss m drefclkp ich_sync# ddc_clk rsv vss hd42 hd38 vss hd36 hclkn hclkp vss n vcc vcc vcc vcc vss v cc vss vcc vcc nc nc nc p vcc vcc vcc vss vcc vss vcc vss vcc vcc nc nc r vcc vcc vcc vcc vss v cc vss vcc vss vcc vcc nc t vcc vcc vcc vcc vcc vss vcc vcc vcc vss vcc vcc u vcc vcc vss vcc vss vcc vss vcc vss vcc vss vcc v vcc vcc vcc vss vcc vss vcc vss vcc vss vcc vcc w vcc vcc vss vcc vss vcc vss vcc vss vcc vss vcc y vcc vcc vcc vcc vcc vss vcc vcc vcc vss vcc vcc aa vcc vcc vss vcc vss vcc vss vcc vcc vcc vcc vcc ab vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc ac rsv rsv rsv rsv rsv r sv rsv rsv rsv rsv nc nc ad vss sdq_b18 sdq_b19 vss sdq_a30 sdq_b28 vss sdqs_b3 sdq_b27 vss sdq_b37 sdm_b6 ae sdq_b21 vss vss rsv_tp0 vss vss sdq_a31 vss vss sdq_b30 vss vss af sdq_b16 sdq_b23 vss sdq_a29 sdqs_a3 vss sdq_ a26 sdqs_b3# vss sdq_b31 sdq_b36 sdq_b32 ag vss sdq_b22 vss vss sdqs_a3# vss vss sd m_b3 vss vss sclk_b0# sdm_b4 ah sdm_b2 vss rsv_tp1 sdm_a3 vss sdq_a 27 sdq_b25 vss sdq_b26 sclk_b0 vss nc aj vss nc vss vss sdq_a25 rsv vss rsv rsv vss rsv rsv ak sdqs_b2 vss rsv_tp3 sdq_a28 vss r sv sdq_b24 vss rsv sclk_b3# vss rsv al vss sdqs_b2# sma_b3 vss sdq_a24 sdq_ b29 vss rsv rsv vss sclk_b3 sma_a2 am vccsm vccsm sma_b0 vccsm vccsm scke_a1 vccsm vccsm sma_a11 vccsm vccsm sclk_a3# an sma_b8 rsv_tp2 sma_b2 sbs_b1 sras_b# sc ke_a2 nc sbs_a2 sma_a9 sma_a8 sma_a6 ap sma_b6 sma_b4 sma_b10 vccsm swe_b# scas_b# scke_a0 vccsm sma_a7 sma_a5 sma_a3 vccsm ar vss vccsm sma_b1 sbs_b0 vss vccsm scke_a3 sma_a12 vss vccsm sma_a4 sma_a1 13 14 15 16 17 18 19 20 21 22 23 24 ballout and package information r 270 datasheet figure 14-3. intel ? 82915g gmch ballout for ddr2 (top view: columns 25?35) 25 26 27 28 29 30 31 32 33 34 35 hd48 vss hd61 hd57 hd55 vss hd53 vss nc nc a hd63 hdinv3# hd54 vss hdstbp3# hd51 hd52 hd15 hd13 hd11 nc b hd58 hd59 hd49 hd56 hdstbn3# hd17 hd50 hd14 hd9 hd12 vss c vss vss hd60 vss hd18 vss vss vss hd10 hd8 d hd25 vss hd24 hd16 vss hbpri# hpcreq# hreq1# hdstbp0# hdinv0# hdstbn0# e vss hdstbn1# hd23 hd22 vss vss hreq4# vss hreq0# hd6 vss f hd26 vss vss vss hd20 ha6# hreq3# ha7# hd7 hd5 hd3 g vss hdstbp1# vss hd19 ha3# vss hreq2# vss hd1 vss hd4 h hd27 hdinv1# hd21 ha13# ha5# vss hads tb0# hrs2# hd0 hd2 hdefer# j hd28 vss ha14# vss ha4# ha8# vss vss ha15# hrs0# vss k hd29 ha18# vss ha12# ha9# vss ha11# vss hlock# hhit# hdbsy# l vss ha20# vss ha16# vss ha10# hads# hdrdy# vss hbnr# m vss ha19# hadstb1# vss ha23# vss ha21# vss ha26# htrdy# hhitm# n vss ha22# vss ha24# vss nc vss vss hedrdy# hrs1# vss p vss vss vss ha25# ha17# rsv rsv sdq_a58 hbreq0# sdq_a59 rsv r vss ha30# ha27# vss ha31# vss ha28# vss sdq_a62 vss sdq_a63 t vss sdq_b63 vss ha29# vss rsv vss vss sdm_a7 sdqs_a7 sdqs_a7# u vss vss vss sdq_b58 sdq_b59 rsv r sv rsv sdq_a57 sdq_a56 vss v vss sdq_b62 sdqs_b7 vss sdq_b57 vss sdm_ b7 vss sdq_a61 sdq_a51 sdq_a60 w vss sdq_b60 vss sdqs_b7# vss rsv vss vss sdq_a50 vss sdq_a55 y vss vss vss sdq_b56 sdq_b61 rsv rsv sd q_a54 sdm_a6 sdqs_a6 sdqs_a6# aa vss sdq_b51 sdq_b55 vss rsv vss sdqs_b6 vss rsv sclk_a5# vss ab vss sdq_b50 vss sdq_b54 vss sdqs_b6# vss vss sclk_a5 sclk_a2 sclk_a2# ac vss vss vss sclk_b5 sclk_b5# nc sdq_a48 rsv vss sdq_a49 ad sclk_b2# sclk_b2 sdq_b49 vss sdq_b53 vss sdq_b52 vss sdq_a43 sdq_a53 sdq_a52 ae sdq_b33 vss sdq_b48 sdq_b43 vss vss vss vss sdq_a42 sdq_a47 vss af vss sdqs_b4# sdq_b47 vss vss sdq_b46 sdq_b42 sdq_a46 sdqs_a5# sdm_a5 sdqs_a5 ag sdqs_b4 vss sdq_a36 sdqs_b5 vss sdqs_b 5# sdm_b5 vss sdq_a40 vss sdq_a41 ah sdq_b39 sdq_b35 vss sdq_a33 sdq_b44 vss sdq_b41 vss sdq_a44 sdq_a45 vss aj vss vss sdq_a32 vss sdm_a4 vss sdq_a35 sdq_b40 sdq_b45 sodt_b3 vccsm ak sdq_b38 sdq_b34 sdq_a37 nc sdqs_a4# sdq_a39 sdq_a34 vss sma_b13 sodt_b1 sodt_b2 al vccsm vccsm sma_a10 vccsm vss sd qs_a4 vss vccsm sodt_b0 scs_b1# am sclk_a3 sclk_a0 sbs_a1 swe_a# scas_a# sdq_a38 scs_a3# sodt_a 1 scs_b0# scs_b3# vccsm an sclk_a0# sma_a0 sras_a# vccsm sodt_a2 sodt_a0 sma_a13 scs_a1# sodt_a3 scs_b2# nc ap vss vccsm sbs_a0 scs_a2# scs_a0# vss vccsm vccsm nc nc ar 25 26 27 28 29 30 31 32 33 34 35 ballout and package information r datasheet 271 table 14-1. gmch/mch ballout for ddr2 systems (sorted by ball number) ball # intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 a1 ? ? ? a2 nc nc nc a3 vss vss vss a4 ? ? ? a5 vss vss vss a6 exp_txn3 exp_txn3 sdvob_clk- a7 exp_txp3 exp_txp3 sdvob_clk+ a8 exp_txn1 exp_txn1 sdvob_green- a9 exp_txp1 exp_txp1 sdvob_green+ a10 vss vss vss a11 gclkp gclkp gclkp a12 vcca_dplla vcca_dplla vcca_dplla a13 vcc2 vcc2 vcc2 a14 vcca_exppll vcca_exppll vcca_exppll a15 rsv refset refset a16 exp_slr exp_slr rsv a17 vcca_hpll vcca_hpll vcca_hpll a18 vss vss vss a19 vtt vtt vtt a20 vtt vtt vtt a21 vtt vtt vtt a22 vtt vtt vtt a23 hswing hswing hswing a24 hvref hvref hvref a25 hd48 hd48 hd48 a26 vss vss vss a27 hd61 hd61 hd61 a28 hd57 hd57 hd57 a29 hd55 hd55 hd55 a30 vss vss vss a31 hd53 hd53 hd53 a32 ? ? ? a33 vss vss vss a34 nc nc nc a35 nc nc nc b1 nc nc nc b2 vss vss vss b3 exp_rxp4 exp_rxp4 rsv b4 exp_rxn4 exp_rxn4 rsv b5 vss vss vss b6 vss vss vss b7 vss vss vss b8 vss vss vss ballout and package information r 272 datasheet table 14-1. gmch/mch ballout for ddr2 systems (sorted by ball number) ball # intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 b9 vss vss vss b10 vss vss vss b11 gclkn gclkn gclkn b12 vss vss vss b13 vcca_dpllb vcca_dpllb vcca_dpllb b14 vss vss vss b15 rsv rsv rsv b16 vss vss vss b17 vcca_smpll vcca_smpll vcca_smpll b18 vss vss vss b19 vtt vtt vtt b20 vtt vtt vtt b21 vtt vtt vtt b22 vtt vtt vtt b23 hrcomp hrcomp hrcomp b24 vss vss vss b25 hd63 hd63 hd63 b26 hdinv3# hdinv3# hdinv3# b27 hd54 hd54 hd54 b28 vss vss vss b29 hdstbp3# hdstbp3# hdstbp3# b30 hd51 hd51 hd51 b31 hd52 hd52 hd52 b32 hd15 hd15 hd15 b33 hd13 hd13 hd13 b34 hd11 hd11 hd11 b35 nc nc nc c1 vss vss vss c2 exp_txp5 exp_txp5 sdvoc_green+ c3 vss vss vss c4 vss vss vss c5 exp_txn4 exp_txn4 sdvoc_red-/ sdvob_alpha- c6 exp_txp4 exp_txp4 sdvoc_red+/ sdvob_alpha+ c7 exp_txn2 exp_txn2 sdvob_blue- c8 exp_txp2 exp_txp2 sdvob_blue+ c9 exp_txn0 exp_txn0 sdvob_red- c10 exp_txp0 exp_txp0 sdvob_red+ c11 vss vss vss c12 ? ? ? c13 vss vss vss c14 rsv rsv rsv ballout and package information r datasheet 273 table 14-1. gmch/mch ballout for ddr2 systems (sorted by ball number) ball # intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 c15 mtype mtype mtype c16 nc nc nc c17 vss vss vss c18 vss vss vss c19 vtt vtt vtt c20 vtt vtt vtt c21 vtt vtt vtt c22 vtt vtt vtt c23 vss vss vss c24 ? ? ? c25 hd58 hd58 hd58 c26 hd59 hd59 hd59 c27 hd49 hd49 hd49 c28 hd56 hd56 hd56 c29 hdstbn3# hdstbn3# hdstbn3# c30 hd17 hd17 hd17 c31 hd50 hd50 hd50 c32 hd14 hd14 hd14 c33 hd9 hd9 hd9 c34 hd12 hd12 hd12 c35 vss vss vss d1 ? ? ? d2 exp_txn5 exp_txn5 sdvoc_green- d3 vss vss vss d4 vss vss vss d5 exp_rxp5 exp_rxp5 sdvoc_int+ d6 vss vss vss d7 vss vss vss d8 vss vss vss d9 vss vss vss d10 vss vss vss d11 vss vss vss d12 rsv vsync vsync d13 rsv vcca_dac vcca_dac d14 rsv green green d15 vss vss vss d16 vss vss vss d17 bsel2 bsel2 bsel2 d18 vss vss vss d19 vtt vtt vtt d20 vtt vtt vtt d21 vtt vtt vtt d22 vtt vtt vtt ballout and package information r 274 datasheet table 14-1. gmch/mch ballout for ddr2 systems (sorted by ball number) ball # intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 d23 vss vss vss d24 hscomp hscomp hscomp d25 vss vss vss d26 vss vss vss d27 hd60 hd60 hd60 d28 vss vss vss d29 hd18 hd18 hd18 d30 vss vss vss d31 vss vss vss d32 vss vss vss d33 hd10 hd10 hd10 d34 hd8 hd8 hd8 d35 ? ? ? e1 vss vss vss e2 vss vss vss e3 exp_txp6 exp_txp6 sdvoc_blue+ e4 vss vss vss e5 exp_rxn5 exp_rxn5 sdvoc_int- e6 vss vss vss e7 exp_rxn3 exp_rxn3 rsv e8 vss vss vss e9 exp_rxn2 exp_rxn2 sdvoc_stall- e10 vss vss vss e11 exp_rxp0 exp_rxp0 sdvoc_tvclkin+ e12 rsv hsync hsync e13 rsv vcca_dac vcca_dac e14 rsv green# green# e15 bsel1 bsel1 bsel1 e16 nc nc nc e17 vss vss vss e18 vss vss vss e19 vtt vtt vtt e20 vtt vtt vtt e21 vtt vtt vtt e22 vtt vtt vtt e23 vss vss vss e24 hd62 hd62 hd62 e25 hd25 hd25 hd25 e26 vss vss vss e27 hd24 hd24 hd24 e28 hd16 hd16 hd16 e29 vss vss vss e30 hbpri# hbpri# hbpri# ballout and package information r datasheet 275 table 14-1. gmch/mch ballout for ddr2 systems (sorted by ball number) ball # intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 e31 hpcreq# hpcreq# hpcreq# e32 hreq1# hreq1# hreq1# e33 hdstbp0# hdstbp0# hdstbp0# e34 hdinv0# hdinv0# hdinv0# e35 hdstbn0# hdstbn0# hdstbn0# f1 exp_txp7 exp_txp7 sdvoc_clk+ f2 vss vss vss f3 exp_txn6 exp_txn6 sdvoc_blue- f4 vss vss vss f5 vss vss vss f6 vss vss vss f7 exp_rxp3 exp_rxp3 rsv f8 vss vss vss f9 exp_rxp2 exp_rxp2 sdvoc_stall+ f10 vss vss vss f11 exp_rxn0 exp_rxn0 sdvoc_tvclkin- f12 nc nc nc f13 rsv vssa_dac vssa_dac f14 rsv red red f15 rsv rsv rsv f16 vss vss vss f17 hd47 hd47 hd47 f18 vss vss vss f19 hdstbn2# hdstbn2# hdstbn2# f20 vtt vtt vtt f21 vtt vtt vtt f22 vtt vtt vtt f23 vss vss vss f24 nc nc nc f25 vss vss vss f26 hdstbn1# hdstbn1# hdstbn1# f27 hd23 hd23 hd23 f28 hd22 hd22 hd22 f29 vss vss vss f30 vss vss vss f31 hreq4# hreq4# hreq4# f32 vss vss vss f33 hreq0# hreq0# hreq0# f34 hd6 hd6 hd6 f35 vss vss vss g1 exp_txn7 exp_txn7 sdvoc_clk- g2 vss vss vss g3 exp_txp8 exp_txp8 rsv ballout and package information r 276 datasheet table 14-1. gmch/mch ballout for ddr2 systems (sorted by ball number) ball # intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 g4 vss vss vss g5 exp_rxn6 exp_rxn6 rsv g6 exp_rxp6 exp_rxp6 rsv g7 vss vss vss g8 vss vss vss g9 vss vss vss g10 vss vss vss g11 vss vss vss g12 nc nc nc g13 vss vss vss g14 rsv red# red# g15 vss vss vss g16 rsv rsv rsv g17 vss vss vss g18 hd45 hd45 hd45 g19 vss vss vss g20 vss vss vss g21 vtt vtt vtt g22 vtt vtt vtt g23 vss vss vss g24 hcpurst# hcpurst# hcpurst# g25 hd26 hd26 hd26 g26 vss vss vss g27 vss vss vss g28 vss vss vss g29 hd20 hd20 hd20 g30 ha6# ha6# ha6# g31 hreq3# hreq3# hreq3# g32 ha7# ha7# ha7# g33 hd7 hd7 hd7 g34 hd5 hd5 hd5 g35 hd3 hd3 hd3 h1 exp_txp9 exp_txp9 rsv h2 vss vss vss h3 exp_txn8 exp_txn8 rsv h4 vss vss vss h5 vss vss vss h6 vss vss vss h7 exp_rxn7 exp_rxn7 rsv h8 exp_rxp7 exp_rxp7 rsv h9 vss vss vss h10 vss vss vss h11 exp_rxn1 exp_rxn1 sdvob_int- ballout and package information r datasheet 277 table 14-1. gmch/mch ballout for ddr2 systems (sorted by ball number) ball # intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 h12 nc nc nc h13 vss vss vss h14 rsv blue blue h15 nc nc nc h16 bsel0 bsel0 bsel0 h17 nc nc nc h18 hd46 hd46 hd46 h19 hd41 hd41 hd41 h20 hd40 hd40 hd40 h21 vss vss vss h22 vtt vtt vtt h23 hd37 hd37 hd37 h24 vss vss vss h25 vss vss vss h26 hdstbp1# hdstbp1# hdstbp1# h27 vss vss vss h28 hd19 hd19 hd19 h29 ha3# ha3# ha3# h30 vss vss vss h31 hreq2# hreq2# hreq2# h32 vss vss vss h33 hd1 hd1 hd1 h34 vss vss vss h35 hd4 hd4 hd4 j1 exp_txn9 exp_txn9 rsv j2 vss vss vss j3 exp_txp10 exp_txp10 rsv j4 vss vss vss j5 exp_rxn8 exp_rxn8 rsv j6 exp_rxp8 exp_rxp8 rsv j7 vss vss vss j8 vss vss vss j9 vss vss vss j10 vss vss vss j11 exp_rxp1 exp_rxp1 sdvob_int+ j12 nc nc nc j13 rsv sdvo_ctrlclk sdvo_ctrlclk j14 rsv blue# blue# j15 vss vss vss j16 vss vss vss j17 vss vss vss j18 vss vss vss j19 hdstbp2# hdstbp2# hdstbp2# ballout and package information r 278 datasheet table 14-1. gmch/mch ballout for ddr2 systems (sorted by ball number) ball # intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 j20 vss vss vss j21 hd35 hd35 hd35 j22 hd32 hd32 hd32 j23 vss vss vss j24 hd33 hd33 hd33 j25 hd27 hd27 hd27 j26 hdinv1# hdinv1# hdinv1# j27 hd21 hd21 hd21 j28 ha13# ha13# ha13# j29 ha5# ha5# ha5# j30 vss vss vss j31 hadstb0# hadstb0# hadstb0# j32 hrs2# hrs2# hrs2# j33 hd0 hd0 hd0 j34 hd2 hd2 hd2 j35 hdefer# hdefer# hdefer# k1 exp_txp11 exp_txp11 rsv k2 vss vss vss k3 exp_txn10 exp_txn10 rsv k4 vss vss vss k5 vss vss vss k6 vss vss vss k7 exp_rxn9 exp_rxn9 rsv k8 exp_rxp9 exp_rxp9 rsv k9 vss vss vss k10 vss vss vss k11 vss vss vss k12 nc nc nc k13 rsv sdvo_ctrldata sdvo_ctrldata k14 vss vss vss k15 rsv rsv rsv k16 extts# extts# extts# k17 hd44 hd44 hd44 k18 hd43 hd43 hd43 k19 hdinv2# hdinv2# hdinv2# k20 vss vss vss k21 hd39 hd39 hd39 k22 hd34 hd34 hd34 k23 hd31 hd31 hd31 k24 vss vss vss k25 hd28 hd28 hd28 k26 vss vss vss k27 ha14# ha14# ha14# ballout and package information r datasheet 279 table 14-1. gmch/mch ballout for ddr2 systems (sorted by ball number) ball # intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 k28 vss vss vss k29 ha4# ha4# ha4# k30 ha8# ha8# ha8# k31 vss vss vss k32 vss vss vss k33 ha15# ha15# ha15# k34 hrs0# hrs0# hrs0# k35 vss vss vss l1 exp_txn11 exp_txn11 rsv l2 vss vss vss l3 exp_txp12 exp_txp12 rsv l4 vss vss vss l5 exp_rxn10 exp_rxn10 rsv l6 exp_rxp10 exp_rxp10 rsv l7 vss vss vss l8 vss vss vss l9 vss vss vss l10 vcc vcc vcc l11 vss vss vss l12 nc nc nc l13 vss vss vss l14 rsv ddc_data ddc_data l15 vss vss vss l16 vss vss vss l17 vss vss vss l18 vss vss vss l19 nc nc nc l20 vss vss vss l21 vss vss vss l22 vss vss vss l23 hd30 hd30 hd30 l24 vss vss vss l25 hd29 hd29 hd29 l26 ha18# ha18# ha18# l27 vss vss vss l28 ha12# ha12# ha12# l29 ha9# ha9# ha9# l30 vss vss vss l31 ha11# ha11# ha11# l32 vss vss vss l33 hlock# hlock# hlock# l34 hhit# hhit# hhit# l35 hdbsy# hdbsy# hdbsy# ballout and package information r 280 datasheet table 14-1. gmch/mch ballout for ddr2 systems (sorted by ball number) ball # intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 m1 exp_txp13 exp_txp13 rsv m2 vss vss vss m3 exp_txn12 exp_txn12 rsv m4 vss vss vss m5 vss vss vss m6 vss vss vss m7 exp_rxn12 exp_rxn12 rsv m8 exp_rxp12 exp_rxp12 rsv m9 vss vss vss m10 vss vss vss m11 vss vss vss m12 drefclkn drefclkn drefclkn m13 drefclkp drefclkp drefclkp m14 ich_sync# ich_sync# ich_sync# m15 rsv ddc_clk ddc_clk m16 rsv rsv rsv m17 vss vss vss m18 hd42 hd42 hd42 m19 hd38 hd38 hd38 m20 vss vss vss m21 hd36 hd36 hd36 m22 hclkn hclkn hclkn m23 hclkp hclkp hclkp m24 vss vss vss m25 vss vss vss m26 ha20# ha20# ha20# m27 vss vss vss m28 ha16# ha16# ha16# m29 vss vss vss m30 ha10# ha10# ha10# m31 hads# hads# hads# m32 hdrdy# hdrdy# hdrdy# m33 ? ? ? m34 vss vss vss m35 hbnr# hbnr# hbnr# n1 exp_txn13 exp_txn13 rsv n2 vss vss vss n3 exp_txp14 exp_txp14 rsv n4 vss vss vss n5 exp_rxn13 exp_rxn13 rsv n6 exp_rxp13 exp_rxp13 rsv n7 vss vss vss n8 vss vss vss ballout and package information r datasheet 281 table 14-1. gmch/mch ballout for ddr2 systems (sorted by ball number) ball # intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 n9 vss vss vss n10 vss vss vss n11 vss vss vss n12 nc nc nc n13 vcc vcc vcc n14 vcc vcc vcc n15 vcc vcc vcc n16 vcc vcc vcc n17 vss vss vss n18 vcc vcc vcc n19 vss vss vss n20 vcc vcc vcc n21 vcc vcc vcc n22 nc nc nc n23 nc nc nc n24 nc nc nc n25 vss vss vss n26 ha19# ha19# ha19# n27 hadstb1# hadstb1# hadstb1# n28 vss vss vss n29 ha23# ha23# ha23# n30 vss vss vss n31 ha21# ha21# ha21# n32 vss vss vss n33 ha26# ha26# ha26# n34 htrdy# htrdy# htrdy# n35 hhitm# hhitm# hhitm# p1 exp_txp15 exp_txp15 rsv p2 vss vss vss p3 exp_txn14 exp_txn14 rsv p4 vss vss vss p5 vss vss vss p6 vss vss vss p7 exp_rxp14 exp_rxp14 rsv p8 exp_rxn14 exp_rxn14 rsv p9 vss vss vss p10 exp_rxp11 exp_rxp11 rsv p11 vss vss vss p12 nc nc nc p13 vcc vcc vcc p14 vcc vcc vcc p15 vcc vcc vcc p16 vss vss vss ballout and package information r 282 datasheet table 14-1. gmch/mch ballout for ddr2 systems (sorted by ball number) ball # intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 p17 vcc vcc vcc p18 vss vss vss p19 vcc vcc vcc p20 vss vss vss p21 vcc vcc vcc p22 vcc vcc vcc p23 nc nc nc p24 nc nc nc p25 vss vss vss p26 ha22# ha22# ha22# p27 vss vss vss p28 ha24# ha24# ha24# p29 vss vss vss p30 nc nc nc p31 vss vss vss p32 vss vss vss p33 hedrdy# hedrdy# hedrdy# p34 hrs1# hrs1# hrs1# p35 vss vss vss r1 exp_txn15 exp_txn15 rsv r2 vss vss vss r3 dmi_txp0 dmi_txp0 dmi_txp0 r4 vss vss vss r5 exp_rxn15 exp_rxn15 rsv r6 exp_rxp15 exp_rxp15 rsv r7 vss vss vss r8 vss vss vss r9 vss vss vss r10 exp_rxn11 exp_rxn11 rsv r11 vss vss vss r12 nc nc nc r13 vcc vcc vcc r14 vcc vcc vcc r15 vcc vcc vcc r16 vcc vcc vcc r17 vss vss vss r18 vcc vcc vcc r19 vss vss vss r20 vcc vcc vcc r21 vss vss vss r22 vcc vcc vcc r23 vcc vcc vcc r24 nc nc nc ballout and package information r datasheet 283 table 14-1. gmch/mch ballout for ddr2 systems (sorted by ball number) ball # intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 r25 vss vss vss r26 vss vss vss r27 vss vss vss r28 ha25# ha25# ha25# r29 ha17# ha17# ha17# r30 rsv rsv rsv r31 rsv rsv rsv r32 sdq_a58 sdq_a58 sdq_a58 r33 hbreq0# hbreq0# hbreq0# r34 sdq_a59 sdq_a59 sdq_a59 r35 rsv rsv rsv t1 dmi_txp1 dmi_txp1 dmi_txp1 t2 vss vss vss t3 dmi_txn0 dmi_txn0 dmi_txn0 t4 vss vss vss t5 vss vss vss t6 vss vss vss t7 vss vss vss t8 dmi_rxn1 dmi_rxn1 dmi_rxn1 t9 dmi_rxp1 dmi_rxp1 dmi_rxp1 t10 vss vss vss t11 vss vss vss t12 nc nc nc t13 vcc vcc vcc t14 vcc vcc vcc t15 vcc vcc vcc t16 vcc vcc vcc t17 vcc vcc vcc t18 vss vss vss t19 vcc vcc vcc t20 vcc vcc vcc t21 vcc vcc vcc t22 vss vss vss t23 vcc vcc vcc t24 vcc vcc vcc t25 vss vss vss t26 ha30# ha30# ha30# t27 ha27# ha27# ha27# t28 vss vss vss t29 ha31# ha31# ha31# t30 vss vss vss t31 ha28# ha28# ha28# t32 vss vss vss ballout and package information r 284 datasheet table 14-1. gmch/mch ballout for ddr2 systems (sorted by ball number) ball # intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 t33 sdq_a62 sdq_a62 sdq_a62 t34 vss vss vss t35 sdq_a63 sdq_a63 sdq_a63 u1 dmi_txn1 dmi_txn1 dmi_txn1 u2 vss vss vss u3 dmi_txp2 dmi_txp2 dmi_txp2 u4 vss vss vss u5 dmi_rxp0 dmi_rxp0 dmi_rxp0 u6 dmi_rxn0 dmi_rxn0 dmi_rxn0 u7 vss vss vss u8 vss vss vss u9 vss vss vss u10 dmi_rxn3 dmi_rxn3 dmi_rxn3 u11 vss vss vss u12 nc nc nc u13 vcc vcc vcc u14 vcc vcc vcc u15 vss vss vss u16 vcc vcc vcc u17 vss vss vss u18 vcc vcc vcc u19 vss vss vss u20 vcc vcc vcc u21 vss vss vss u22 vcc vcc vcc u23 vss vss vss u24 vcc vcc vcc u25 vss vss vss u26 sdq_b63 sdq_b63 sdq_b63 u27 vss vss vss u28 ha29# ha29# ha29# u29 vss vss vss u30 rsv rsv rsv u31 vss vss vss u32 vss vss vss u33 sdm_a7 sdm_a7 sdm_a7 u34 sdqs_a7 sdqs_a7 sdqs_a7 u35 sdqs_a7# sdqs_a7# sdqs_a7# v1 vss vss vss v2 vss vss vss v3 dmi_txn2 dmi_txn2 dmi_txn2 v4 vss vss vss v5 dmi_txp3 dmi_txp3 dmi_txp3 ballout and package information r datasheet 285 table 14-1. gmch/mch ballout for ddr2 systems (sorted by ball number) ball # intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 v6 vss vss vss v7 dmi_rxp2 dmi_rxp2 dmi_rxp2 v8 dmi_rxn2 dmi_rxn2 dmi_rxn2 v9 vss vss vss v10 dmi_rxp3 dmi_rxp3 dmi_rxp3 v11 vss vss vss v12 nc nc nc v13 vcc vcc vcc v14 vcc vcc vcc v15 vcc vcc vcc v16 vss vss vss v17 vcc vcc vcc v18 vss vss vss v19 vcc vcc vcc v20 vss vss vss v21 vcc vcc vcc v22 vss vss vss v23 vcc vcc vcc v24 vcc vcc vcc v25 vss vss vss v26 vss vss vss v27 vss vss vss v28 sdq_b58 sdq_b58 sdq_b58 v29 sdq_b59 sdq_b59 sdq_b59 v30 rsv rsv rsv v31 rsv rsv rsv v32 rsv rsv rsv v33 sdq_a57 sdq_a57 sdq_a57 v34 sdq_a56 sdq_a56 sdq_a56 v35 vss vss vss w1 vcc_exp vcc_exp vcc_exp w2 vcc_exp vcc_exp vcc_exp w3 vcc_exp vcc_exp vcc_exp w4 vcc_exp vcc_exp vcc_exp w5 dmi_txn3 dmi_txn3 dmi_txn3 w6 vcc_exp vcc_exp vcc_exp w7 vcc_exp vcc_exp vcc_exp w8 vcc_exp vcc_exp vcc_exp w9 vcc_exp vcc_exp vcc_exp w10 exp_compi exp_compi rsv w11 vss vss vss w12 nc nc nc w13 vcc vcc vcc ballout and package information r 286 datasheet table 14-1. gmch/mch ballout for ddr2 systems (sorted by ball number) ball # intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 w14 vcc vcc vcc w15 vss vss vss w16 vcc vcc vcc w17 vss vss vss w18 vcc vcc vcc w19 vss vss vss w20 vcc vcc vcc w21 vss vss vss w22 vcc vcc vcc w23 vss vss vss w24 vcc vcc vcc w25 vss vss vss w26 sdq_b62 sdq_b62 sdq_b62 w27 sdqs_b7 sdqs_b7 sdqs_b7 w28 vss vss vss w29 sdq_b57 sdq_b57 sdq_b57 w30 vss vss vss w31 sdm_b7 sdm_b7 sdm_b7 w32 vss vss vss w33 sdq_a61 sdq_a61 sdq_a61 w34 sdq_a51 sdq_a51 sdq_a51 w35 sdq_a60 sdq_a60 sdq_a60 y1 vcc_exp vcc_exp vcc_exp y2 vcc_exp vcc_exp vcc_exp y3 vcc_exp vcc_exp vcc_exp y4 vcc_exp vcc_exp vcc_exp y5 vcc_exp vcc_exp vcc_exp y6 vcc_exp vcc_exp vcc_exp y7 vcc_exp vcc_exp vcc_exp y8 vcc_exp vcc_exp vcc_exp y9 vcc_exp vcc_exp vcc_exp y10 exp_compo exp_compo rsv y11 vss vss vss y12 nc nc nc y13 vcc vcc vcc y14 vcc vcc vcc y15 vcc vcc vcc y16 vcc vcc vcc y17 vcc vcc vcc y18 vss vss vss y19 vcc vcc vcc y20 vcc vcc vcc y21 vcc vcc vcc ballout and package information r datasheet 287 table 14-1. gmch/mch ballout for ddr2 systems (sorted by ball number) ball # intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 y22 vss vss vss y23 vcc vcc vcc y24 vcc vcc vcc y25 vss vss vss y26 sdq_b60 sdq_b60 sdq_b60 y27 vss vss vss y28 sdqs_b7# sdqs_b7# sdqs_b7# y29 vss vss vss y30 rsv rsv rsv y31 vss vss vss y32 vss vss vss y33 sdq_a50 sdq_a50 sdq_a50 y34 vss vss vss y35 sdq_a55 sdq_a55 sdq_a55 aa1 vss vss vss aa2 vss vss vss aa3 vss vss vss aa4 vss vss vss aa5 vss vss vss aa6 vss vss vss aa7 vss vss vss aa8 vss vss vss aa9 vss vss vss aa10 vss vss vss aa11 vss vss vss aa12 nc nc nc aa13 vcc vcc vcc aa14 vcc vcc vcc aa15 vss vss vss aa16 vcc vcc vcc aa17 vss vss vss aa18 vcc vcc vcc aa19 vss vss vss aa20 vcc vcc vcc aa21 vcc vcc vcc aa22 vcc vcc vcc aa23 vcc vcc vcc aa24 vcc vcc vcc aa25 vss vss vss aa26 vss vss vss aa27 vss vss vss aa28 sdq_b56 sdq_b56 sdq_b56 aa29 sdq_b61 sdq_b61 sdq_b61 ballout and package information r 288 datasheet table 14-1. gmch/mch ballout for ddr2 systems (sorted by ball number) ball # intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 aa30 rsv rsv rsv aa31 rsv rsv rsv aa32 sdq_a54 sdq_a54 sdq_a54 aa33 sdm_a6 sdm_a6 sdm_a6 aa34 sdqs_a6 sdqs_a6 sdqs_a6 aa35 sdqs_a6# sdqs_a6# sdqs_a6# ab1 vcc vcc vcc ab2 vcc vcc vcc ab3 vcc vcc vcc ab4 vcc vcc vcc ab5 vcc vcc vcc ab6 vcc vcc vcc ab7 vcc vcc vcc ab8 vcc vcc vcc ab9 vcc vcc vcc ab10 vcc vcc vcc ab11 vcc vcc vcc ab12 nc nc nc ab13 vcc vcc vcc ab14 vcc vcc vcc ab15 vcc vcc vcc ab16 vcc vcc vcc ab17 vcc vcc vcc ab18 vcc vcc vcc ab19 vcc vcc vcc ab20 vcc vcc vcc ab21 vcc vcc vcc ab22 vcc vcc vcc ab23 vcc vcc vcc ab24 vcc vcc vcc ab25 vss vss vss ab26 sdq_b51 sdq_b51 sdq_b51 ab27 sdq_b55 sdq_b55 sdq_b55 ab28 vss vss vss ab29 rsv rsv rsv ab30 vss vss vss ab31 sdqs_b6 sdqs_b6 sdqs_b6 ab32 vss vss vss ab33 rsv rsv rsv ab34 sclk_a5# sclk_a5# sclk_a5# ab35 vss vss vss ac1 vcc vcc vcc ac2 vcc vcc vcc ballout and package information r datasheet 289 table 14-1. gmch/mch ballout for ddr2 systems (sorted by ball number) ball # intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 ac3 vcc vcc vcc ac4 vcc vcc vcc ac5 vcc vcc vcc ac6 vcc vcc vcc ac7 vcc vcc vcc ac8 vcc vcc vcc ac9 vcc vcc vcc ac10 vcc vcc vcc ac11 vcc vcc vcc ac12 rsv rsv rsv ac13 rsv rsv rsv ac14 rsv rsv rsv ac15 rsv rsv rsv ac16 rsv rsv rsv ac17 rsv rsv rsv ac18 rsv rsv rsv ac19 rsv rsv rsv ac20 rsv rsv rsv ac21 rsv rsv rsv ac22 rsv rsv rsv ac23 nc nc nc ac24 nc nc nc ac25 vss vss vss ac26 sdq_b50 sdq_b50 sdq_b50 ac27 vss vss vss ac28 sdq_b54 sdq_b54 sdq_b54 ac29 vss vss vss ac30 sdqs_b6# sdqs_b6# sdqs_b6# ac31 vss vss vss ac32 vss vss vss ac33 sclk_a5 sclk_a5 sclk_a5 ac34 sclk_a2 sclk_a2 sclk_a2 ac35 sclk_a2# sclk_a2# sclk_a2# ad1 vcc vcc vcc ad2 vcc vcc vcc ad3 vcc vcc vcc ad4 vcc vcc vcc ad5 vcc vcc vcc ad6 vcc vcc vcc ad7 vcc vcc vcc ad8 vcc vcc vcc ad9 vcc vcc vcc ad10 vcc vcc vcc ballout and package information r 290 datasheet table 14-1. gmch/mch ballout for ddr2 systems (sorted by ball number) ball # intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 ad11 vss vss vss ad12 sdq_b20 sdq_b20 sdq_b20 ad13 vss vss vss ad14 sdq_b18 sdq_b18 sdq_b18 ad15 sdq_b19 sdq_b19 sdq_b19 ad16 vss vss vss ad17 sdq_a30 sdq_a30 sdq_a30 ad18 sdq_b28 sdq_b28 sdq_b28 ad19 vss vss vss ad20 sdqs_b3 sdqs_b3 sdqs_b3 ad21 sdq_b27 sdq_b27 sdq_b27 ad22 vss vss vss ad23 sdq_b37 sdq_b37 sdq_b37 ad24 sdm_b6 sdm_b6 sdm_b6 ad25 vss vss vss ad26 vss vss vss ad27 vss vss vss ad28 sclk_b5 sclk_b5 sclk_b5 ad29 sclk_b5# sclk_b5# sclk_b5# ad30 nc nc nc ad31 sdq_a48 sdq_a48 sdq_a48 ad32 rsv rsv rsv ad33 ? ? ? ad34 vss vss vss ad35 sdq_a49 sdq_a49 sdq_a49 ae1 sdq_a5 sdq_a5 sdq_a5 ae2 sdq_a4 sdq_a4 sdq_a4 ae3 sdq_a0 sdq_a0 sdq_a0 ae4 vss vss vss ae5 socomp1 socomp1 socomp1 ae6 vss vss vss ae7 svref0 svref0 svref0 ae8 svref1 svref1 svref1 ae9 vss vss vss ae10 sm_slewout1 sm_slewout1 sm_slewout1 ae11 sdq_b11 sdq_b11 sdq_b11 ae12 vss vss vss ae13 sdq_b21 sdq_b21 sdq_b21 ae14 vss vss vss ae15 vss vss vss ae16 rsv_tp0 rsv_tp0 rsv_tp0 ae17 vss vss vss ae18 vss vss vss ballout and package information r datasheet 291 table 14-1. gmch/mch ballout for ddr2 systems (sorted by ball number) ball # intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 ae19 sdq_a31 sdq_a31 sdq_a31 ae20 vss vss vss ae21 vss vss vss ae22 sdq_b30 sdq_b30 sdq_b30 ae23 vss vss vss ae24 vss vss vss ae25 sclk_b2# sclk_b2# sclk_b2# ae26 sclk_b2 sclk_b2 sclk_b2 ae27 sdq_b49 sdq_b49 sdq_b49 ae28 vss vss vss ae29 sdq_b53 sdq_b53 sdq_b53 ae30 vss vss vss ae31 sdq_b52 sdq_b52 sdq_b52 ae32 vss vss vss ae33 sdq_a43 sdq_a43 sdq_a43 ae34 sdq_a53 sdq_a53 sdq_a53 ae35 sdq_a52 sdq_a52 sdq_a52 af1 vss vss vss af2 sdm_a0 sdm_a0 sdm_a0 af3 sdq_a1 sdq_a1 sdq_a1 af4 vss vss vss af5 socomp0 socomp0 socomp0 af6 vss vss vss af7 rstin# rstin# rstin# af8 vss vss vss af9 sm_slewin1 sm_slewin1 sm_slewin1 af10 vss vss vss af11 sdq_b10 sdq_b10 sdq_b10 af12 vss vss vss af13 sdq_b16 sdq_b16 sdq_b16 af14 sdq_b23 sdq_b23 sdq_b23 af15 vss vss vss af16 sdq_a29 sdq_a29 sdq_a29 af17 sdqs_a3 sdqs_a3 sdqs_a3 af18 vss vss vss af19 sdq_a26 sdq_a26 sdq_a26 af20 sdqs_b3# sdqs_b3# sdqs_b3# af21 vss vss vss af22 sdq_b31 sdq_b31 sdq_b31 af23 sdq_b36 sdq_b36 sdq_b36 af24 sdq_b32 sdq_b32 sdq_b32 af25 sdq_b33 sdq_b33 sdq_b33 af26 vss vss vss ballout and package information r 292 datasheet table 14-1. gmch/mch ballout for ddr2 systems (sorted by ball number) ball # intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 af27 sdq_b48 sdq_b48 sdq_b48 af28 sdq_b43 sdq_b43 sdq_b43 af29 vss vss vss af30 vss vss vss af31 vss vss vss af32 vss vss vss af33 sdq_a42 sdq_a42 sdq_a42 af34 sdq_a47 sdq_a47 sdq_a47 af35 vss vss vss ag1 sdqs_a0 sdqs_a0 sdqs_a0 ag2 sdqs_a0# sdqs_a0# sdqs_a0# ag3 sdq_a6 sdq_a6 sdq_a6 ag4 srcomp0 srcomp0 srcomp0 ag5 vss vss vss ag6 nc nc nc ag7 pwrok pwrok pwrok ag8 srcomp1 srcomp1 srcomp1 ag9 sdq_b4 sdq_b4 sdq_b4 ag10 sdq_b14 sdq_b14 sdq_b14 ag11 sdq_b15 sdq_b15 sdq_b15 ag12 vss vss vss ag13 vss vss vss ag14 sdq_b22 sdq_b22 sdq_b22 ag15 vss vss vss ag16 vss vss vss ag17 sdqs_a3# sdqs_a3# sdqs_a3# ag18 vss vss vss ag19 vss vss vss ag20 sdm_b3 sdm_b3 sdm_b3 ag21 vss vss vss ag22 vss vss vss ag23 sclk_b0# sclk_b0# sclk_b0# ag24 sdm_b4 sdm_b4 sdm_b4 ag25 vss vss vss ag26 sdqs_b4# sdqs_b4# sdqs_b4# ag27 sdq_b47 sdq_b47 sdq_b47 ag28 vss vss vss ag29 vss vss vss ag30 sdq_b46 sdq_b46 sdq_b46 ag31 sdq_b42 sdq_b42 sdq_b42 ag32 sdq_a46 sdq_a46 sdq_a46 ag33 sdqs_a5# sdqs_a5# sdqs_a5# ag34 sdm_a5 sdm_a5 sdm_a5 ballout and package information r datasheet 293 table 14-1. gmch/mch ballout for ddr2 systems (sorted by ball number) ball # intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 ag35 sdqs_a5 sdqs_a5 sdqs_a5 ah1 vss vss vss ah2 sdq_a7 sdq_a7 sdq_a7 ah3 sdq_a2 sdq_a2 sdq_a2 ah4 sdq_b0 sdq_b0 sdq_b0 ah5 vss vss vss ah6 vss vss vss ah7 sdq_b5 sdq_b5 sdq_b5 ah8 vss vss vss ah9 sdm_b1 sdm_b1 sdm_b1 ah10 sdqs_b1# sdqs_b1# sdqs_b1# ah11 vss vss vss ah12 sdq_b17 sdq_b17 sdq_b17 ah13 sdm_b2 sdm_b2 sdm_b2 ah14 vss vss vss ah15 rsv_tp1 rsv_tp1 rsv_tp1 ah16 sdm_a3 sdm_a3 sdm_a3 ah17 vss vss vss ah18 sdq_a27 sdq_a27 sdq_a27 ah19 sdq_b25 sdq_b25 sdq_b25 ah20 vss vss vss ah21 sdq_b26 sdq_b26 sdq_b26 ah22 sclk_b0 sclk_b0 sclk_b0 ah23 vss vss vss ah24 nc nc nc ah25 sdqs_b4 sdqs_b4 sdqs_b4 ah26 vss vss vss ah27 sdq_a36 sdq_a36 sdq_a36 ah28 sdqs_b5 sdqs_b5 sdqs_b5 ah29 vss vss vss ah30 sdqs_b5# sdqs_b5# sdqs_b5# ah31 sdm_b5 sdm_b5 sdm_b5 ah32 vss vss vss ah33 sdq_a40 sdq_a40 sdq_a40 ah34 vss vss vss ah35 sdq_a41 sdq_a41 sdq_a41 aj1 sdq_a12 sdq_a12 sdq_a12 aj2 sdq_a3 sdq_a3 sdq_a3 aj3 sdq_a13 sdq_a13 sdq_a13 aj4 vss vss vss aj5 sdm_b0 sdm_b0 sdm_b0 aj6 sdq_b1 sdq_b1 sdq_b1 aj7 sdq_b12 sdq_b12 sdq_b12 ballout and package information r 294 datasheet table 14-1. gmch/mch ballout for ddr2 systems (sorted by ball number) ball # intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 aj8 sdq_b8 sdq_b8 sdq_b8 aj9 vss vss vss aj10 vss vss vss aj11 sclk_b4 sclk_b4 sclk_b4 aj12 sm_slewin0 sm_slewin0 sm_slewin0 aj13 vss vss vss aj14 nc nc nc aj15 vss vss vss aj16 vss vss vss aj17 sdq_a25 sdq_a25 sdq_a25 aj18 rsv rsv rsv aj19 vss vss vss aj20 rsv rsv rsv aj21 rsv rsv rsv aj22 vss vss vss aj23 rsv rsv rsv aj24 rsv rsv rsv aj25 sdq_b39 sdq_b39 sdq_b39 aj26 sdq_b35 sdq_b35 sdq_b35 aj27 vss vss vss aj28 sdq_a33 sdq_a33 sdq_a33 aj29 sdq_b44 sdq_b44 sdq_b44 aj30 vss vss vss aj31 sdq_b41 sdq_b41 sdq_b41 aj32 vss vss vss aj33 sdq_a44 sdq_a44 sdq_a44 aj34 sdq_a45 sdq_a45 sdq_a45 aj35 vss vss vss ak1 vss vss vss ak2 sdq_a8 sdq_a8 sdq_a8 ak3 sdq_a9 sdq_a9 sdq_a9 ak4 vss vss vss ak5 sdqs_b0 sdqs_b0 sdqs_b0 ak6 vss vss vss ak7 vss vss vss ak8 vss vss vss ak9 sclk_b1 sclk_b1 sclk_b1 ak10 sdqs_b1 sdqs_b1 sdqs_b1 ak11 vss vss vss ak12 sm_slewout0 sm_slewout0 sm_slewout0 ak13 sdqs_b2 sdqs_b2 sdqs_b2 ak14 vss vss vss ak15 rsv_tp3 rsv_tp3 rsv_tp3 ballout and package information r datasheet 295 table 14-1. gmch/mch ballout for ddr2 systems (sorted by ball number) ball # intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 ak16 sdq_a28 sdq_a28 sdq_a28 ak17 vss vss vss ak18 rsv rsv rsv ak19 sdq_b24 sdq_b24 sdq_b24 ak20 vss vss vss ak21 rsv rsv rsv ak22 sclk_b3# sclk_b3# sclk_b3# ak23 vss vss vss ak24 rsv rsv rsv ak25 vss vss vss ak26 vss vss vss ak27 sdq_a32 sdq_a32 sdq_a32 ak28 vss vss vss ak29 sdm_a4 sdm_a4 sdm_a4 ak30 vss vss vss ak31 sdq_a35 sdq_a35 sdq_a35 ak32 sdq_b40 sdq_b40 sdq_b40 ak33 sdq_b45 sdq_b45 sdq_b45 ak34 sodt_b3 sodt_b3 sodt_b3 ak35 vccsm vccsm vccsm al1 sdm_a1 sdm_a1 sdm_a1 al2 sdqs_a1# sdqs_a1# sdqs_a1# al3 sdqs_a1 sdqs_a1 sdqs_a1 al4 sdqs_b0# sdqs_b0# sdqs_b0# al5 sdq_b6 sdq_b6 sdq_b6 al6 sdq_b2 sdq_b2 sdq_b2 al7 sdq_b13 sdq_b13 sdq_b13 al8 sdq_b9 sdq_b9 sdq_b9 al9 sclk_b1# sclk_b1# sclk_b1# al10 vss vss vss al11 sclk_b4# sclk_b4# sclk_b4# al12 sma_b7 sma_b7 sma_b7 al13 vss vss vss al14 sdqs_b2# sdqs_b2# sdqs_b2# al15 sma_b3 sma_b3 sma_b3 al16 vss vss vss al17 sdq_a24 sdq_a24 sdq_a24 al18 sdq_b29 sdq_b29 sdq_b29 al19 vss vss vss al20 rsv rsv rsv al21 rsv rsv rsv al22 vss vss vss al23 sclk_b3 sclk_b3 sclk_b3 ballout and package information r 296 datasheet table 14-1. gmch/mch ballout for ddr2 systems (sorted by ball number) ball # intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 al24 sma_a2 sma_a2 sma_a2 al25 sdq_b38 sdq_b38 sdq_b38 al26 sdq_b34 sdq_b34 sdq_b34 al27 sdq_a37 sdq_a37 sdq_a37 al28 nc nc nc al29 sdqs_a4# sdqs_a4# sdqs_a4# al30 sdq_a39 sdq_a39 sdq_a39 al31 sdq_a34 sdq_a34 sdq_a34 al32 vss vss vss al33 sma_b13 sma_b13 sma_b13 al34 sodt_b1 sodt_b1 sodt_b1 al35 sodt_b2 sodt_b2 sodt_b2 am1 am2 sclk_a1 sclk_a1 sclk_a1 am3 sclk_a1# sclk_a1# sclk_a1# am4 vss vss vss am5 sdq_b7 sdq_b7 sdq_b7 am6 vss vss vss am7 vss vss vss am8 vss vss vss am9 scke_b3 scke_b3 scke_b3 am10 vccsm vccsm vccsm am11 vccsm vccsm vccsm am12 sma_b5 sma_b5 sma_b5 am13 vccsm vccsm vccsm am14 vccsm vccsm vccsm am15 sma_b0 sma_b0 sma_b0 am16 vccsm vccsm vccsm am17 vccsm vccsm vccsm am18 scke_a1 scke_a1 scke_a1 am19 vccsm vccsm vccsm am20 vccsm vccsm vccsm am21 sma_a11 sma_a11 sma_a11 am22 vccsm vccsm vccsm am23 vccsm vccsm vccsm am24 sclk_a3# sclk_a3# sclk_a3# am25 vccsm vccsm vccsm am26 vccsm vccsm vccsm am27 sma_a10 sma_a10 sma_a10 am28 vccsm vccsm vccsm am29 vss vss vss am30 sdqs_a4 sdqs_a4 sdqs_a4 am31 vss vss vss ballout and package information r datasheet 297 table 14-1. gmch/mch ballout for ddr2 systems (sorted by ball number) ball # intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 am32 vccsm vccsm vccsm am33 sodt_b0 sodt_b0 sodt_b0 am34 scs_b1# scs_b1# scs_b1# am35 ? ? ? an1 vss vss vss an2 sclk_a4# sclk_a4# sclk_a4# an3 sclk_a4 sclk_a4 sclk_a4 an4 sdq_a10 sdq_a10 sdq_a10 an5 sdq_a20 sdq_a20 sdq_a20 an6 sdq_b3 sdq_b3 sdq_b3 an7 sdm_a2 sdm_a2 sdm_a2 an8 sdq_a22 sdq_a22 sdq_a22 an9 sdq_a19 sdq_a19 sdq_a19 an10 scke_b1 scke_b1 scke_b1 an11 sbs_b2 sbs_b2 sbs_b2 an12 an13 sma_b8 sma_b8 sma_b8 an14 rsv_tp2 rsv_tp2 rsv_tp2 an15 sma_b2 sma_b2 sma_b2 an16 sbs_b1 sbs_b1 sbs_b1 an17 sras_b# sras_b# sras_b# an18 scke_a2 scke_a2 scke_a2 an19 nc nc nc an20 sbs_a2 sbs_a2 sbs_a2 an21 sma_a9 sma_a9 sma_a9 an22 sma_a8 sma_a8 sma_a8 an23 sma_a6 sma_a6 sma_a6 an24 ? ? ? an25 sclk_a3 sclk_a3 sclk_a3 an26 sclk_a0 sclk_a0 sclk_a0 an27 sbs_a1 sbs_a1 sbs_a1 an28 swe_a# swe_a# swe_a# an29 scas_a# scas_a# scas_a# an30 sdq_a38 sdq_a38 sdq_a38 an31 scs_a3# scs_a3# scs_a3# an32 sodt_a1 sodt_a1 sodt_a1 an33 scs_b0# scs_b0# scs_b0# an34 scs_b3# scs_b3# scs_b3# an35 vccsm vccsm vccsm ap1 nc nc nc ap2 sdq_a14 sdq_a14 sdq_a14 ap3 sdq_a15 sdq_a15 sdq_a15 ap4 sdq_a11 sdq_a11 sdq_a11 ballout and package information r 298 datasheet table 14-1. gmch/mch ballout for ddr2 systems (sorted by ball number) ball # intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 ap5 sdq_a21 sdq_a21 sdq_a21 ap6 sdq_a17 sdq_a17 sdq_a17 ap7 sdqs_a2 sdqs_a2 sdqs_a2 ap8 vss vss vss ap9 sdq_a18 sdq_a18 sdq_a18 ap10 scke_b0 scke_b0 scke_b0 ap11 sma_b11 sma_b11 sma_b11 ap12 vccsm vccsm vccsm ap13 sma_b6 sma_b6 sma_b6 ap14 sma_b4 sma_b4 sma_b4 ap15 sma_b10 sma_b10 sma_b10 ap16 vccsm vccsm vccsm ap17 swe_b# swe_b# swe_b# ap18 scas_b# scas_b# scas_b# ap19 scke_a0 scke_a0 scke_a0 ap20 vccsm vccsm vccsm ap21 sma_a7 sma_a7 sma_a7 ap22 sma_a5 sma_a5 sma_a5 ap23 sma_a3 sma_a3 sma_a3 ap24 vccsm vccsm vccsm ap25 sclk_a0# sclk_a0# sclk_a0# ap26 sma_a0 sma_a0 sma_a0 ap27 sras_a# sras_a# sras_a# ap28 vccsm vccsm vccsm ap29 sodt_a2 sodt_a2 sodt_a2 ap30 sodt_a0 sodt_a0 sodt_a0 ap31 sma_a13 sma_a13 sma_a13 ap32 scs_a1# scs_a1# scs_a1# ap33 sodt_a3 sodt_a3 sodt_a3 ap34 scs_b2# scs_b2# scs_b2# ap35 nc nc nc ar1 nc nc nc ar2 nc nc nc ar3 vss vss vss ar4 ar5 sdq_a16 sdq_a16 sdq_a16 ar6 vss vss vss ar7 sdqs_a2# sdqs_a2# sdqs_a2# ar8 sdq_a23 sdq_a23 sdq_a23 ar9 scke_b2 scke_b2 scke_b2 ar10 vccsm vccsm vccsm ar11 sma_b12 sma_b12 sma_b12 ar12 sma_b9 sma_b9 sma_b9 ballout and package information r datasheet 299 table 14-1. gmch/mch ballout for ddr2 systems (sorted by ball number) ball # intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 ar13 vss vss vss ar14 vccsm vccsm vccsm ar15 sma_b1 sma_b1 sma_b1 ar16 sbs_b0 sbs_b0 sbs_b0 ar17 vss vss vss ar18 vccsm vccsm vccsm ar19 scke_a3 scke_a3 scke_a3 ar20 sma_a12 sma_a12 sma_a12 ar21 vss vss vss ar22 vccsm vccsm vccsm ar23 sma_a4 sma_a4 sma_a4 ar24 sma_a1 sma_a1 sma_a1 ar25 vss vss vss ar26 vccsm vccsm vccsm ar27 sbs_a0 sbs_a0 sbs_a0 ar28 scs_a2# scs_a2# scs_a2# ar29 scs_a0# scs_a0# scs_a0# ar30 vss vss vss ar31 vccsm vccsm vccsm ar32 ? ? ? ar33 vccsm vccsm vccsm ar34 nc nc nc ar35 nc nc nc notes: 1. ddr2, pci express* x16 graphics interface, no dac, no intel ? sdvo 2. ddr2, pci express* x16 graphics interface, dac, intel ? sdvo 3. ddr2, no pci express* x16 graphics interface, dac, intel ? sdvo ballout and package information r 300 datasheet table 14-2. gmch/mch ballout for ddr2 systems (sorted by signal name) intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 ball # rsv blue blue h14 rsv blue# blue# j14 bsel0 bsel0 bsel0 h16 bsel1 bsel1 bsel1 e15 bsel2 bsel2 bsel2 d17 rsv ddc_clk ddc_clk m15 rsv ddc_data ddc_data l14 dmi_rxn0 dmi_rxn0 dmi_rxn0 u6 dmi_rxn1 dmi_rxn1 dmi_rxn1 t8 dmi_rxn2 dmi_rxn2 dmi_rxn2 v8 dmi_rxn3 dmi_rxn3 dmi_rxn3 u10 dmi_rxp0 dmi_rxp0 dmi_rxp0 u5 dmi_rxp1 dmi_rxp1 dmi_rxp1 t9 dmi_rxp2 dmi_rxp2 dmi_rxp2 v7 dmi_rxp3 dmi_rxp3 dmi_rxp3 v10 dmi_txn0 dmi_txn0 dmi_txn0 t3 dmi_txn1 dmi_txn1 dmi_txn1 u1 dmi_txn2 dmi_txn2 dmi_txn2 v3 dmi_txn3 dmi_txn3 dmi_txn3 w5 dmi_txp0 dmi_txp0 dmi_txp0 r3 dmi_txp1 dmi_txp1 dmi_txp1 t1 dmi_txp2 dmi_txp2 dmi_txp2 u3 dmi_txp3 dmi_txp3 dmi_txp3 v5 drefclkn drefclkn drefclkn m12 drefclkp drefclkp drefclkp m13 exp_compi exp_compi exp_compi w10 exp_compo exp_compo exp_compo y10 exp_rxn0 exp_rxn0 sdvoc_tvclkin- f11 exp_rxn1 exp_rxn1 sdvob_int- h11 exp_rxn10 exp_rxn10 rsv l5 exp_rxn11 exp_rxn11 rsv r10 exp_rxn12 exp_rxn12 rsv m7 exp_rxn13 exp_rxn13 rsv n5 exp_rxn14 exp_rxn14 rsv p8 exp_rxn15 exp_rxn15 rsv r5 exp_rxn2 exp_rxn2 sdvoc_stall- e9 exp_rxn3 exp_rxn3 rsv e7 exp_rxn4 exp_rxn4 rsv b4 exp_rxn5 exp_rxn5 sdvoc_int- e5 exp_rxn6 exp_rxn6 rsv g5 exp_rxn7 exp_rxn7 rsv h7 exp_rxn8 exp_rxn8 rsv j5 exp_rxn9 exp_rxn9 rsv k7 ballout and package information r datasheet 301 table 14-2. gmch/mch ballout for ddr2 systems (sorted by signal name) intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 ball # exp_rxp0 exp_rxp0 sdvoc_tvclkin+ e11 exp_rxp1 exp_rxp1 sdvob_int+ j11 exp_rxp10 exp_rxp10 rsv l6 exp_rxp11 exp_rxp11 rsv p10 exp_rxp12 exp_rxp12 rsv m8 exp_rxp13 exp_rxp13 rsv n6 exp_rxp14 exp_rxp14 rsv p7 exp_rxp15 exp_rxp15 rsv r6 exp_rxp2 exp_rxp2 sdvoc_stall+ f9 exp_rxp3 exp_rxp3 rsv f7 exp_rxp4 exp_rxp4 rsv b3 exp_rxp5 exp_rxp5 sdvoc_int+ d5 exp_rxp6 exp_rxp6 rsv g6 exp_rxp7 exp_rxp7 rsv h8 exp_rxp8 exp_rxp8 rsv j6 exp_rxp9 exp_rxp9 rsv k8 exp_slr exp_slr rsv a16 exp_txn0 exp_txn0 sdvob_red- c9 exp_txn1 exp_txn1 sdvob_green- a8 exp_txn10 exp_txn10 rsv k3 exp_txn11 exp_txn11 rsv l1 exp_txn12 exp_txn12 rsv m3 exp_txn13 exp_txn13 rsv n1 exp_txn14 exp_txn14 rsv p3 exp_txn15 exp_txn15 rsv r1 exp_txn2 exp_txn2 sdvob_blue- c7 exp_txn3 exp_txn3 sdvob_clk- a6 exp_txn4 exp_txn4 sdvoc_red-/ sdvob_alpha- c5 exp_txn5 exp_txn5 sdvoc_green- d2 exp_txn6 exp_txn6 sdvoc_blue- f3 exp_txn7 exp_txn7 sdvoc_clk- g1 exp_txn8 exp_txn8 rsv h3 exp_txn9 exp_txn9 rsv j1 exp_txp0 exp_txp0 sdvob_red+ c10 exp_txp1 exp_txp1 sdvob_green+ a9 exp_txp10 exp_txp10 rsv j3 exp_txp11 exp_txp11 rsv k1 exp_txp12 exp_txp12 rsv l3 exp_txp13 exp_txp13 rsv m1 exp_txp14 exp_txp14 rsv n3 exp_txp15 exp_txp15 rsv p1 exp_txp2 exp_txp2 sdvob_blue+ c8 ballout and package information r 302 datasheet table 14-2. gmch/mch ballout for ddr2 systems (sorted by signal name) intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 ball # exp_txp3 exp_txp3 sdvob_clk+ a7 exp_txp4 exp_txp4 sdvoc_red+/ sdvob_alpha+ c6 exp_txp5 exp_txp5 sdvoc_green+ c2 exp_txp6 exp_txp6 sdvoc_blue+ e3 exp_txp7 exp_txp7 sdvoc_clk+ f1 exp_txp8 exp_txp8 rsv g3 exp_txp9 exp_txp9 rsv h1 extts# extts# extts# k16 gclkn gclkn gclkn b11 gclkp gclkp gclkp a11 rsv green green d14 rsv green# green# e14 ha3# ha3# ha3# h29 ha4# ha4# ha4# k29 ha5# ha5# ha5# j29 ha6# ha6# ha6# g30 ha7# ha7# ha7# g32 ha8# ha8# ha8# k30 ha9# ha9# ha9# l29 ha10# ha10# ha10# m30 ha11# ha11# ha11# l31 ha12# ha12# ha12# l28 ha13# ha13# ha13# j28 ha14# ha14# ha14# k27 ha15# ha15# ha15# k33 ha16# ha16# ha16# m28 ha17# ha17# ha17# r29 ha18# ha18# ha18# l26 ha19# ha19# ha19# n26 ha20# ha20# ha20# m26 ha21# ha21# ha21# n31 ha22# ha22# ha22# p26 ha23# ha23# ha23# n29 ha24# ha24# ha24# p28 ha25# ha25# ha25# r28 ha26# ha26# ha26# n33 ha27# ha27# ha27# t27 ha28# ha28# ha28# t31 ha29# ha29# ha29# u28 ha30# ha30# ha30# t26 ha31# ha31# ha31# t29 hads# hads# hads# m31 ballout and package information r datasheet 303 table 14-2. gmch/mch ballout for ddr2 systems (sorted by signal name) intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 ball # hadstb0# hadstb0# hadstb0# j31 hadstb1# hadstb1# hadstb1# n27 hbnr# hbnr# hbnr# m35 hbpri# hbpri# hbpri# e30 hbreq0# hbreq0# hbreq0# r33 hclkn hclkn hclkn m22 hclkp hclkp hclkp m23 hcpurst# hcpurst# hcpurst# g24 hd0 hd0 hd0 j33 hd1 hd1 hd1 h33 hd2 hd2 hd2 j34 hd3 hd3 hd3 g35 hd4 hd4 hd4 h35 hd5 hd5 hd5 g34 hd6 hd6 hd6 f34 hd7 hd7 hd7 g33 hd8 hd8 hd8 d34 hd9 hd9 hd9 c33 hd10 hd10 hd10 d33 hd11 hd11 hd11 b34 hd12 hd12 hd12 c34 hd13 hd13 hd13 b33 hd14 hd14 hd14 c32 hd15 hd15 hd15 b32 hd16 hd16 hd16 e28 hd17 hd17 hd17 c30 hd18 hd18 hd18 d29 hd19 hd19 hd19 h28 hd20 hd20 hd20 g29 hd21 hd21 hd21 j27 hd22 hd22 hd22 f28 hd23 hd23 hd23 f27 hd24 hd24 hd24 e27 hd25 hd25 hd25 e25 hd26 hd26 hd26 g25 hd27 hd27 hd27 j25 hd28 hd28 hd28 k25 hd29 hd29 hd29 l25 hd30 hd30 hd30 l23 hd31 hd31 hd31 k23 hd32 hd32 hd32 j22 hd33 hd33 hd33 j24 hd34 hd34 hd34 k22 ballout and package information r 304 datasheet table 14-2. gmch/mch ballout for ddr2 systems (sorted by signal name) intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 ball # hd35 hd35 hd35 j21 hd36 hd36 hd36 m21 hd37 hd37 hd37 h23 hd38 hd38 hd38 m19 hd39 hd39 hd39 k21 hd40 hd40 hd40 h20 hd41 hd41 hd41 h19 hd42 hd42 hd42 m18 hd43 hd43 hd43 k18 hd44 hd44 hd44 k17 hd45 hd45 hd45 g18 hd46 hd46 hd46 h18 hd47 hd47 hd47 f17 hd48 hd48 hd48 a25 hd49 hd49 hd49 c27 hd50 hd50 hd50 c31 hd51 hd51 hd51 b30 hd52 hd52 hd52 b31 hd53 hd53 hd53 a31 hd54 hd54 hd54 b27 hd55 hd55 hd55 a29 hd56 hd56 hd56 c28 hd57 hd57 hd57 a28 hd58 hd58 hd58 c25 hd59 hd59 hd59 c26 hd60 hd60 hd60 d27 hd61 hd61 hd61 a27 hd62 hd62 hd62 e24 hd63 hd63 hd63 b25 hdbsy# hdbsy# hdbsy# l35 hdefer# hdefer# hdefer# j35 hdinv0# hdinv0# hdinv0# e34 hdinv1# hdinv1# hdinv1# j26 hdinv2# hdinv2# hdinv2# k19 hdinv3# hdinv3# hdinv3# b26 hdrdy# hdrdy# hdrdy# m32 hdstbn0# hdstbn0# hdstbn0# e35 hdstbn1# hdstbn1# hdstbn1# f26 hdstbn2# hdstbn2# hdstbn2# f19 hdstbn3# hdstbn3# hdstbn3# c29 hdstbp0# hdstbp0# hdstbp0# e33 hdstbp1# hdstbp1# hdstbp1# h26 hdstbp2# hdstbp2# hdstbp2# j19 ballout and package information r datasheet 305 table 14-2. gmch/mch ballout for ddr2 systems (sorted by signal name) intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 ball # hdstbp3# hdstbp3# hdstbp3# b29 hedrdy# hedrdy# hedrdy# p33 hhit# hhit# hhit# l34 hhitm# hhitm# hhitm# n35 hlock# hlock# hlock# l33 hpcreq# hpcreq# hpcreq# e31 hrcomp hrcomp hrcomp b23 hreq0# hreq0# hreq0# f33 hreq1# hreq1# hreq1# e32 hreq2# hreq2# hreq2# h31 hreq3# hreq3# hreq3# g31 hreq4# hreq4# hreq4# f31 hrs0# hrs0# hrs0# k34 hrs1# hrs1# hrs1# p34 hrs2# hrs2# hrs2# j32 hscomp hscomp hscomp d24 hswing hswing hswing a23 rsv hsync hsync e12 htrdy# htrdy# htrdy# n34 hvref hvref hvref a24 ich_sync# ich_sync# ich_sync# m14 mtype mtype mtype c15 nc nc nc a2 nc nc nc a34 nc nc nc a35 nc nc nc aa12 nc nc nc ab12 nc nc nc ac23 nc nc nc ac24 nc nc nc ad30 nc nc nc ag6 nc nc nc ah24 nc nc nc aj14 nc nc nc al28 nc nc nc an19 nc nc nc ap1 nc nc nc ap35 nc nc nc ar1 nc nc nc ar2 nc nc nc ar34 nc nc nc ar35 nc nc nc b1 nc nc nc b35 ballout and package information r 306 datasheet table 14-2. gmch/mch ballout for ddr2 systems (sorted by signal name) intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 ball # nc nc nc c16 nc nc nc e16 nc nc nc f12 nc nc nc f24 nc nc nc g12 nc nc nc h12 nc nc nc h15 nc nc nc h17 nc nc nc j12 nc nc nc k12 nc nc nc l12 nc nc nc l19 nc nc nc n12 nc nc nc n22 nc nc nc n23 nc nc nc n24 nc nc nc p12 nc nc nc p23 nc nc nc p24 nc nc nc p30 nc nc nc r12 nc nc nc r24 nc nc nc t12 nc nc nc u12 nc nc nc v12 nc nc nc w12 nc nc nc y12 pwrok pwrok pwrok ag7 rsv red red f14 rsv red# red# g14 rsv refset refset a15 rstin# rstin# rstin# af7 rsv rsv rsv aa30 rsv rsv rsv aa31 rsv rsv rsv ab29 rsv rsv rsv ab33 rsv rsv rsv ac12 rsv rsv rsv ac13 rsv rsv rsv ac14 rsv rsv rsv ac15 rsv rsv rsv ac16 rsv rsv rsv ac17 rsv rsv rsv ac18 ballout and package information r datasheet 307 table 14-2. gmch/mch ballout for ddr2 systems (sorted by signal name) intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 ball # rsv rsv rsv ac19 rsv rsv rsv ac20 rsv rsv rsv ac21 rsv rsv rsv ac22 rsv rsv rsv ad32 rsv rsv rsv aj18 rsv rsv rsv aj20 rsv rsv rsv aj21 rsv rsv rsv aj23 rsv rsv rsv aj24 rsv rsv rsv ak18 rsv rsv rsv ak21 rsv rsv rsv ak24 rsv rsv rsv al20 rsv rsv rsv al21 rsv rsv rsv b15 rsv rsv rsv c14 rsv rsv rsv f15 rsv rsv rsv g16 rsv rsv rsv k15 rsv rsv rsv m16 rsv rsv rsv r30 rsv rsv rsv r31 rsv rsv rsv r35 rsv rsv rsv u30 rsv rsv rsv v30 rsv rsv rsv v31 rsv rsv rsv v32 rsv rsv rsv y30 rsv_tp0 rsv_tp0 rsv_tp0 ae16 rsv_tp1 rsv_tp1 rsv_tp1 ah15 rsv_tp2 rsv_tp2 rsv_tp2 an14 rsv_tp3 rsv_tp3 rsv_tp3 ak15 sbs_a0 sbs_a0 sbs_a0 ar27 sbs_a1 sbs_a1 sbs_a1 an27 sbs_a2 sbs_a2 sbs_a2 an20 sbs_b0 sbs_b0 sbs_b0 ar16 sbs_b1 sbs_b1 sbs_b1 an16 sbs_b2 sbs_b2 sbs_b2 an11 scas_a# scas_a# scas_a# an29 scas_b# scas_b# scas_b# ap18 scke_a0 scke_a0 scke_a0 ap19 scke_a1 scke_a1 scke_a1 am18 ballout and package information r 308 datasheet table 14-2. gmch/mch ballout for ddr2 systems (sorted by signal name) intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 ball # scke_a2 scke_a2 scke_a2 an18 scke_a3 scke_a3 scke_a3 ar19 scke_b0 scke_b0 scke_b0 ap10 scke_b1 scke_b1 scke_b1 an10 scke_b2 scke_b2 scke_b2 ar9 scke_b3 scke_b3 scke_b3 am9 sclk_a0 sclk_a0 sclk_a0 an26 sclk_a0# sclk_a0# sclk_a0# ap25 sclk_a1 sclk_a1 sclk_a1 am2 sclk_a1# sclk_a1# sclk_a1# am3 sclk_a2 sclk_a2 sclk_a2 ac34 sclk_a2# sclk_a2# sclk_a2# ac35 sclk_a3 sclk_a3 sclk_a3 an25 sclk_a3# sclk_a3# sclk_a3# am24 sclk_a4 sclk_a4 sclk_a4 an3 sclk_a4# sclk_a4# sclk_a4# an2 sclk_a5 sclk_a5 sclk_a5 ac33 sclk_a5# sclk_a5# sclk_a5# ab34 sclk_b0 sclk_b0 sclk_b0 ah22 sclk_b0# sclk_b0# sclk_b0# ag23 sclk_b1 sclk_b1 sclk_b1 ak9 sclk_b1# sclk_b1# sclk_b1# al9 sclk_b2 sclk_b2 sclk_b2 ae26 sclk_b2# sclk_b2# sclk_b2# ae25 sclk_b3 sclk_b3 sclk_b3 al23 sclk_b3# sclk_b3# sclk_b3# ak22 sclk_b4 sclk_b4 sclk_b4 aj11 sclk_b4# sclk_b4# sclk_b4# al11 sclk_b5 sclk_b5 sclk_b5 ad28 sclk_b5# sclk_b5# sclk_b5# ad29 scs_a0# scs_a0# scs_a0# ar29 scs_a1# scs_a1# scs_a1# ap32 scs_a2# scs_a2# scs_a2# ar28 scs_a3# scs_a3# scs_a3# an31 scs_b0# scs_b0# scs_b0# an33 scs_b1# scs_b1# scs_b1# am34 scs_b2# scs_b2# scs_b2# ap34 scs_b3# scs_b3# scs_b3# an34 sdm_a0 sdm_a0 sdm_a0 af2 sdm_a1 sdm_a1 sdm_a1 al1 sdm_a2 sdm_a2 sdm_a2 an7 sdm_a3 sdm_a3 sdm_a3 ah16 sdm_a4 sdm_a4 sdm_a4 ak29 ballout and package information r datasheet 309 table 14-2. gmch/mch ballout for ddr2 systems (sorted by signal name) intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 ball # sdm_a5 sdm_a5 sdm_a5 ag34 sdm_a6 sdm_a6 sdm_a6 aa33 sdm_a7 sdm_a7 sdm_a7 u33 sdm_b0 sdm_b0 sdm_b0 aj5 sdm_b1 sdm_b1 sdm_b1 ah9 sdm_b2 sdm_b2 sdm_b2 ah13 sdm_b3 sdm_b3 sdm_b3 ag20 sdm_b4 sdm_b4 sdm_b4 ag24 sdm_b5 sdm_b5 sdm_b5 ah31 sdm_b6 sdm_b6 sdm_b6 ad24 sdm_b7 sdm_b7 sdm_b7 w31 sdq_a0 sdq_a0 sdq_a0 ae3 sdq_a1 sdq_a1 sdq_a1 af3 sdq_a2 sdq_a2 sdq_a2 ah3 sdq_a3 sdq_a3 sdq_a3 aj2 sdq_a4 sdq_a4 sdq_a4 ae2 sdq_a5 sdq_a5 sdq_a5 ae1 sdq_a6 sdq_a6 sdq_a6 ag3 sdq_a7 sdq_a7 sdq_a7 ah2 sdq_a8 sdq_a8 sdq_a8 ak2 sdq_a9 sdq_a9 sdq_a9 ak3 sdq_a10 sdq_a10 sdq_a10 an4 sdq_a11 sdq_a11 sdq_a11 ap4 sdq_a12 sdq_a12 sdq_a12 aj1 sdq_a13 sdq_a13 sdq_a13 aj3 sdq_a14 sdq_a14 sdq_a14 ap2 sdq_a15 sdq_a15 sdq_a15 ap3 sdq_a16 sdq_a16 sdq_a16 ar5 sdq_a17 sdq_a17 sdq_a17 ap6 sdq_a18 sdq_a18 sdq_a18 ap9 sdq_a19 sdq_a19 sdq_a19 an9 sdq_a20 sdq_a20 sdq_a20 an5 sdq_a21 sdq_a21 sdq_a21 ap5 sdq_a22 sdq_a22 sdq_a22 an8 sdq_a23 sdq_a23 sdq_a23 ar8 sdq_a24 sdq_a24 sdq_a24 al17 sdq_a25 sdq_a25 sdq_a25 aj17 sdq_a26 sdq_a26 sdq_a26 af19 sdq_a27 sdq_a27 sdq_a27 ah18 sdq_a28 sdq_a28 sdq_a28 ak16 sdq_a29 sdq_a29 sdq_a29 af16 sdq_a30 sdq_a30 sdq_a30 ad17 sdq_a31 sdq_a31 sdq_a31 ae19 ballout and package information r 310 datasheet table 14-2. gmch/mch ballout for ddr2 systems (sorted by signal name) intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 ball # sdq_a32 sdq_a32 sdq_a32 ak27 sdq_a33 sdq_a33 sdq_a33 aj28 sdq_a34 sdq_a34 sdq_a34 al31 sdq_a35 sdq_a35 sdq_a35 ak31 sdq_a36 sdq_a36 sdq_a36 ah27 sdq_a37 sdq_a37 sdq_a37 al27 sdq_a38 sdq_a38 sdq_a38 an30 sdq_a39 sdq_a39 sdq_a39 al30 sdq_a40 sdq_a40 sdq_a40 ah33 sdq_a41 sdq_a41 sdq_a41 ah35 sdq_a42 sdq_a42 sdq_a42 af33 sdq_a43 sdq_a43 sdq_a43 ae33 sdq_a44 sdq_a44 sdq_a44 aj33 sdq_a45 sdq_a45 sdq_a45 aj34 sdq_a46 sdq_a46 sdq_a46 ag32 sdq_a47 sdq_a47 sdq_a47 af34 sdq_a48 sdq_a48 sdq_a48 ad31 sdq_a49 sdq_a49 sdq_a49 ad35 sdq_a50 sdq_a50 sdq_a50 y33 sdq_a51 sdq_a51 sdq_a51 w34 sdq_a52 sdq_a52 sdq_a52 ae35 sdq_a53 sdq_a53 sdq_a53 ae34 sdq_a54 sdq_a54 sdq_a54 aa32 sdq_a55 sdq_a55 sdq_a55 y35 sdq_a56 sdq_a56 sdq_a56 v34 sdq_a57 sdq_a57 sdq_a57 v33 sdq_a58 sdq_a58 sdq_a58 r32 sdq_a59 sdq_a59 sdq_a59 r34 sdq_a60 sdq_a60 sdq_a60 w35 sdq_a61 sdq_a61 sdq_a61 w33 sdq_a62 sdq_a62 sdq_a62 t33 sdq_a63 sdq_a63 sdq_a63 t35 sdq_b0 sdq_b0 sdq_b0 ah4 sdq_b1 sdq_b1 sdq_b1 aj6 sdq_b2 sdq_b2 sdq_b2 al6 sdq_b3 sdq_b3 sdq_b3 an6 sdq_b4 sdq_b4 sdq_b4 ag9 sdq_b5 sdq_b5 sdq_b5 ah7 sdq_b6 sdq_b6 sdq_b6 al5 sdq_b7 sdq_b7 sdq_b7 am5 sdq_b8 sdq_b8 sdq_b8 aj8 sdq_b9 sdq_b9 sdq_b9 al8 sdq_b10 sdq_b10 sdq_b10 af11 ballout and package information r datasheet 311 table 14-2. gmch/mch ballout for ddr2 systems (sorted by signal name) intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 ball # sdq_b11 sdq_b11 sdq_b11 ae11 sdq_b12 sdq_b12 sdq_b12 aj7 sdq_b13 sdq_b13 sdq_b13 al7 sdq_b14 sdq_b14 sdq_b14 ag10 sdq_b15 sdq_b15 sdq_b15 ag11 sdq_b16 sdq_b16 sdq_b16 af13 sdq_b17 sdq_b17 sdq_b17 ah12 sdq_b18 sdq_b18 sdq_b18 ad14 sdq_b19 sdq_b19 sdq_b19 ad15 sdq_b20 sdq_b20 sdq_b20 ad12 sdq_b21 sdq_b21 sdq_b21 ae13 sdq_b22 sdq_b22 sdq_b22 ag14 sdq_b23 sdq_b23 sdq_b23 af14 sdq_b24 sdq_b24 sdq_b24 ak19 sdq_b25 sdq_b25 sdq_b25 ah19 sdq_b26 sdq_b26 sdq_b26 ah21 sdq_b27 sdq_b27 sdq_b27 ad21 sdq_b28 sdq_b28 sdq_b28 ad18 sdq_b29 sdq_b29 sdq_b29 al18 sdq_b30 sdq_b30 sdq_b30 ae22 sdq_b31 sdq_b31 sdq_b31 af22 sdq_b32 sdq_b32 sdq_b32 af24 sdq_b33 sdq_b33 sdq_b33 af25 sdq_b34 sdq_b34 sdq_b34 al26 sdq_b35 sdq_b35 sdq_b35 aj26 sdq_b36 sdq_b36 sdq_b36 af23 sdq_b37 sdq_b37 sdq_b37 ad23 sdq_b38 sdq_b38 sdq_b38 al25 sdq_b39 sdq_b39 sdq_b39 aj25 sdq_b40 sdq_b40 sdq_b40 ak32 sdq_b41 sdq_b41 sdq_b41 aj31 sdq_b42 sdq_b42 sdq_b42 ag31 sdq_b43 sdq_b43 sdq_b43 af28 sdq_b44 sdq_b44 sdq_b44 aj29 sdq_b45 sdq_b45 sdq_b45 ak33 sdq_b46 sdq_b46 sdq_b46 ag30 sdq_b47 sdq_b47 sdq_b47 ag27 sdq_b48 sdq_b48 sdq_b48 af27 sdq_b49 sdq_b49 sdq_b49 ae27 sdq_b50 sdq_b50 sdq_b50 ac26 sdq_b51 sdq_b51 sdq_b51 ab26 sdq_b52 sdq_b52 sdq_b52 ae31 sdq_b53 sdq_b53 sdq_b53 ae29 ballout and package information r 312 datasheet table 14-2. gmch/mch ballout for ddr2 systems (sorted by signal name) intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 ball # sdq_b54 sdq_b54 sdq_b54 ac28 sdq_b55 sdq_b55 sdq_b55 ab27 sdq_b56 sdq_b56 sdq_b56 aa28 sdq_b57 sdq_b57 sdq_b57 w29 sdq_b58 sdq_b58 sdq_b58 v28 sdq_b59 sdq_b59 sdq_b59 v29 sdq_b60 sdq_b60 sdq_b60 y26 sdq_b61 sdq_b61 sdq_b61 aa29 sdq_b62 sdq_b62 sdq_b62 w26 sdq_b63 sdq_b63 sdq_b63 u26 sdqs_a0 sdqs_a0 sdqs_a0 ag1 sdqs_a0# sdqs_a0# sdqs_a0# ag2 sdqs_a1 sdqs_a1 sdqs_a1 al3 sdqs_a1# sdqs_a1# sdqs_a1# al2 sdqs_a2 sdqs_a2 sdqs_a2 ap7 sdqs_a2# sdqs_a2# sdqs_a2# ar7 sdqs_a3 sdqs_a3 sdqs_a3 af17 sdqs_a3# sdqs_a3# sdqs_a3# ag17 sdqs_a4 sdqs_a4 sdqs_a4 am30 sdqs_a4# sdqs_a4# sdqs_a4# al29 sdqs_a5 sdqs_a5 sdqs_a5 ag35 sdqs_a5# sdqs_a5# sdqs_a5# ag33 sdqs_a6 sdqs_a6 sdqs_a6 aa34 sdqs_a6# sdqs_a6# sdqs_a6# aa35 sdqs_a7 sdqs_a7 sdqs_a7 u34 sdqs_a7# sdqs_a7# sdqs_a7# u35 sdqs_b0 sdqs_b0 sdqs_b0 ak5 sdqs_b0# sdqs_b0# sdqs_b0# al4 sdqs_b1 sdqs_b1 sdqs_b1 ak10 sdqs_b1# sdqs_b1# sdqs_b1# ah10 sdqs_b2 sdqs_b2 sdqs_b2 ak13 sdqs_b2# sdqs_b2# sdqs_b2# al14 sdqs_b3 sdqs_b3 sdqs_b3 ad20 sdqs_b3# sdqs_b3# sdqs_b3# af20 sdqs_b4 sdqs_b4 sdqs_b4 ah25 sdqs_b4# sdqs_b4# sdqs_b4# ag26 sdqs_b5 sdqs_b5 sdqs_b5 ah28 sdqs_b5# sdqs_b5# sdqs_b5# ah30 sdqs_b6 sdqs_b6 sdqs_b6 ab31 sdqs_b6# sdqs_b6# sdqs_b6# ac30 sdqs_b7 sdqs_b7 sdqs_b7 w27 sdqs_b7# sdqs_b7# sdqs_b7# y28 rsv sdvo_ctrlclk sdvo_ctrlclk j13 ballout and package information r datasheet 313 table 14-2. gmch/mch ballout for ddr2 systems (sorted by signal name) intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 ball # rsv sdvo_ctrldata sdvo_ctrldata k13 sm_slewin0 sm_slewin0 sm_slewin0 aj12 sm_slewin1 sm_slewin1 sm_slewin1 af9 sm_slewout0 sm_slewout0 sm_slewout0 ak12 sm_slewout1 sm_slewout1 sm_slewout1 ae10 sma_a0 sma_a0 sma_a0 ap26 sma_a1 sma_a1 sma_a1 ar24 sma_a2 sma_a2 sma_a2 al24 sma_a3 sma_a3 sma_a3 ap23 sma_a4 sma_a4 sma_a4 ar23 sma_a5 sma_a5 sma_a5 ap22 sma_a6 sma_a6 sma_a6 an23 sma_a7 sma_a7 sma_a7 ap21 sma_a8 sma_a8 sma_a8 an22 sma_a9 sma_a9 sma_a9 an21 sma_a10 sma_a10 sma_a10 am27 sma_a11 sma_a11 sma_a11 am21 sma_a12 sma_a12 sma_a12 ar20 sma_a13 sma_a13 sma_a13 ap31 sma_b0 sma_b0 sma_b0 am15 sma_b1 sma_b1 sma_b1 ar15 sma_b2 sma_b2 sma_b2 an15 sma_b3 sma_b3 sma_b3 al15 sma_b4 sma_b4 sma_b4 ap14 sma_b5 sma_b5 sma_b5 am12 sma_b6 sma_b6 sma_b6 ap13 sma_b7 sma_b7 sma_b7 al12 sma_b8 sma_b8 sma_b8 an13 sma_b9 sma_b9 sma_b9 ar12 sma_b10 sma_b10 sma_b10 ap15 sma_b11 sma_b11 sma_b11 ap11 sma_b12 sma_b12 sma_b12 ar11 sma_b13 sma_b13 sma_b13 al33 socomp0 socomp0 socomp0 af5 socomp1 socomp1 socomp1 ae5 sodt_a0 sodt_a0 sodt_a0 ap30 sodt_a1 sodt_a1 sodt_a1 an32 sodt_a2 sodt_a2 sodt_a2 ap29 sodt_a3 sodt_a3 sodt_a3 ap33 sodt_b0 sodt_b0 sodt_b0 am33 sodt_b1 sodt_b1 sodt_b1 al34 sodt_b2 sodt_b2 sodt_b2 al35 sodt_b3 sodt_b3 sodt_b3 ak34 ballout and package information r 314 datasheet table 14-2. gmch/mch ballout for ddr2 systems (sorted by signal name) intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 ball # sras_a# sras_a# sras_a# ap27 sras_b# sras_b# sras_b# an17 srcomp0 srcomp0 srcomp0 ag4 srcomp1 srcomp1 srcomp1 ag8 svref0 svref0 svref0 ae7 svref1 svref1 svref1 ae8 swe_a# swe_a# swe_a# an28 swe_b# swe_b# swe_b# ap17 vcc vcc vcc aa13 vcc vcc vcc aa14 vcc vcc vcc aa16 vcc vcc vcc aa18 vcc vcc vcc aa20 vcc vcc vcc aa21 vcc vcc vcc aa22 vcc vcc vcc aa23 vcc vcc vcc aa24 vcc vcc vcc ab1 vcc vcc vcc ab10 vcc vcc vcc ab11 vcc vcc vcc ab13 vcc vcc vcc ab14 vcc vcc vcc ab15 vcc vcc vcc ab16 vcc vcc vcc ab17 vcc vcc vcc ab18 vcc vcc vcc ab19 vcc vcc vcc ab2 vcc vcc vcc ab20 vcc vcc vcc ab21 vcc vcc vcc ab22 vcc vcc vcc ab23 vcc vcc vcc ab24 vcc vcc vcc ab3 vcc vcc vcc ab4 vcc vcc vcc ab5 vcc vcc vcc ab6 vcc vcc vcc ab7 vcc vcc vcc ab8 vcc vcc vcc ab9 vcc vcc vcc ac1 vcc vcc vcc ac10 vcc vcc vcc ac11 ballout and package information r datasheet 315 table 14-2. gmch/mch ballout for ddr2 systems (sorted by signal name) intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 ball # vcc vcc vcc ac2 vcc vcc vcc ac3 vcc vcc vcc ac4 vcc vcc vcc ac5 vcc vcc vcc ac6 vcc vcc vcc ac7 vcc vcc vcc ac8 vcc vcc vcc ac9 vcc vcc vcc ad1 vcc vcc vcc ad10 vcc vcc vcc ad2 vcc vcc vcc ad3 vcc vcc vcc ad4 vcc vcc vcc ad5 vcc vcc vcc ad6 vcc vcc vcc ad7 vcc vcc vcc ad8 vcc vcc vcc ad9 vcc vcc vcc l10 vcc vcc vcc n13 vcc vcc vcc n14 vcc vcc vcc n15 vcc vcc vcc n16 vcc vcc vcc n18 vcc vcc vcc n20 vcc vcc vcc n21 vcc vcc vcc p13 vcc vcc vcc p14 vcc vcc vcc p15 vcc vcc vcc p17 vcc vcc vcc p19 vcc vcc vcc p21 vcc vcc vcc p22 vcc vcc vcc r13 vcc vcc vcc r14 vcc vcc vcc r15 vcc vcc vcc r16 vcc vcc vcc r18 vcc vcc vcc r20 vcc vcc vcc r22 vcc vcc vcc r23 vcc vcc vcc t13 vcc vcc vcc t14 ballout and package information r 316 datasheet table 14-2. gmch/mch ballout for ddr2 systems (sorted by signal name) intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 ball # vcc vcc vcc t15 vcc vcc vcc t16 vcc vcc vcc t17 vcc vcc vcc t19 vcc vcc vcc t20 vcc vcc vcc t21 vcc vcc vcc t23 vcc vcc vcc t24 vcc vcc vcc u13 vcc vcc vcc u14 vcc vcc vcc u16 vcc vcc vcc u18 vcc vcc vcc u20 vcc vcc vcc u22 vcc vcc vcc u24 vcc vcc vcc v13 vcc vcc vcc v14 vcc vcc vcc v15 vcc vcc vcc v17 vcc vcc vcc v19 vcc vcc vcc v21 vcc vcc vcc v23 vcc vcc vcc v24 vcc vcc vcc w13 vcc vcc vcc w14 vcc vcc vcc w16 vcc vcc vcc w18 vcc vcc vcc w20 vcc vcc vcc w22 vcc vcc vcc w24 vcc vcc vcc y13 vcc vcc vcc y14 vcc vcc vcc y15 vcc vcc vcc y16 vcc vcc vcc y17 vcc vcc vcc y19 vcc vcc vcc y20 vcc vcc vcc y21 vcc vcc vcc y23 vcc vcc vcc y24 vcc_exp vcc_exp vcc_exp w1 vcc_exp vcc_exp vcc_exp w2 vcc_exp vcc_exp vcc_exp w3 ballout and package information r datasheet 317 table 14-2. gmch/mch ballout for ddr2 systems (sorted by signal name) intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 ball # vcc_exp vcc_exp vcc_exp w4 vcc_exp vcc_exp vcc_exp w6 vcc_exp vcc_exp vcc_exp w7 vcc_exp vcc_exp vcc_exp w8 vcc_exp vcc_exp vcc_exp w9 vcc_exp vcc_exp vcc_exp y1 vcc_exp vcc_exp vcc_exp y2 vcc_exp vcc_exp vcc_exp y3 vcc_exp vcc_exp vcc_exp y4 vcc_exp vcc_exp vcc_exp y5 vcc_exp vcc_exp vcc_exp y6 vcc_exp vcc_exp vcc_exp y7 vcc_exp vcc_exp vcc_exp y8 vcc_exp vcc_exp vcc_exp y9 vcc2 vcc2 vcc2 a13 rsv vcca_dac vcca_dac d13 rsv vcca_dac vcca_dac e13 vcca_dplla vcca_dplla vcca_dplla a12 vcca_dpllb vcca_dpllb vcca_dpllb b13 vcca_exppll vcca_exppll vcca_exppll a14 vcca_hpll vcca_hpll vcca_hpll a17 vcca_smpll vcca_smpll vcca_smpll b17 vccsm vccsm vccsm ak35 vccsm vccsm vccsm am10 vccsm vccsm vccsm am11 vccsm vccsm vccsm am13 vccsm vccsm vccsm am14 vccsm vccsm vccsm am16 vccsm vccsm vccsm am17 vccsm vccsm vccsm am19 vccsm vccsm vccsm am20 vccsm vccsm vccsm am22 vccsm vccsm vccsm am23 vccsm vccsm vccsm am25 vccsm vccsm vccsm am26 vccsm vccsm vccsm am28 vccsm vccsm vccsm am32 vccsm vccsm vccsm an35 vccsm vccsm vccsm ap12 vccsm vccsm vccsm ap16 vccsm vccsm vccsm ap20 vccsm vccsm vccsm ap24 vccsm vccsm vccsm ap28 ballout and package information r 318 datasheet table 14-2. gmch/mch ballout for ddr2 systems (sorted by signal name) intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 ball # vccsm vccsm vccsm ar10 vccsm vccsm vccsm ar14 vccsm vccsm vccsm ar18 vccsm vccsm vccsm ar22 vccsm vccsm vccsm ar26 vccsm vccsm vccsm ar31 vccsm vccsm vccsm ar33 vss vss vss a10 vss vss vss a18 vss vss vss a26 vss vss vss a3 vss vss vss a30 vss vss vss a33 vss vss vss a5 vss vss vss aa1 vss vss vss aa10 vss vss vss aa11 vss vss vss aa15 vss vss vss aa17 vss vss vss aa19 vss vss vss aa2 vss vss vss aa25 vss vss vss aa26 vss vss vss aa27 vss vss vss aa3 vss vss vss aa4 vss vss vss aa5 vss vss vss aa6 vss vss vss aa7 vss vss vss aa8 vss vss vss aa9 vss vss vss ab25 vss vss vss ab28 vss vss vss ab30 vss vss vss ab32 vss vss vss ab35 vss vss vss ac25 vss vss vss ac27 vss vss vss ac29 vss vss vss ac31 vss vss vss ac32 vss vss vss ad11 vss vss vss ad13 ballout and package information r datasheet 319 table 14-2. gmch/mch ballout for ddr2 systems (sorted by signal name) intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 ball # vss vss vss ad16 vss vss vss ad19 vss vss vss ad22 vss vss vss ad25 vss vss vss ad26 vss vss vss ad27 vss vss vss ad34 vss vss vss ae12 vss vss vss ae14 vss vss vss ae15 vss vss vss ae17 vss vss vss ae18 vss vss vss ae20 vss vss vss ae21 vss vss vss ae23 vss vss vss ae24 vss vss vss ae28 vss vss vss ae30 vss vss vss ae32 vss vss vss ae4 vss vss vss ae6 vss vss vss ae9 vss vss vss af1 vss vss vss af10 vss vss vss af12 vss vss vss af15 vss vss vss af18 vss vss vss af21 vss vss vss af26 vss vss vss af29 vss vss vss af30 vss vss vss af31 vss vss vss af32 vss vss vss af35 vss vss vss af4 vss vss vss af6 vss vss vss af8 vss vss vss ag12 vss vss vss ag13 vss vss vss ag15 vss vss vss ag16 vss vss vss ag18 vss vss vss ag19 ballout and package information r 320 datasheet table 14-2. gmch/mch ballout for ddr2 systems (sorted by signal name) intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 ball # vss vss vss ag21 vss vss vss ag22 vss vss vss ag25 vss vss vss ag28 vss vss vss ag29 vss vss vss ag5 vss vss vss ah1 vss vss vss ah11 vss vss vss ah14 vss vss vss ah17 vss vss vss ah20 vss vss vss ah23 vss vss vss ah26 vss vss vss ah29 vss vss vss ah32 vss vss vss ah34 vss vss vss ah5 vss vss vss ah6 vss vss vss ah8 vss vss vss aj10 vss vss vss aj13 vss vss vss aj15 vss vss vss aj16 vss vss vss aj19 vss vss vss aj22 vss vss vss aj27 vss vss vss aj30 vss vss vss aj32 vss vss vss aj35 vss vss vss aj4 vss vss vss aj9 vss vss vss ak1 vss vss vss ak11 vss vss vss ak14 vss vss vss ak17 vss vss vss ak20 vss vss vss ak23 vss vss vss ak25 vss vss vss ak26 vss vss vss ak28 vss vss vss ak30 vss vss vss ak4 vss vss vss ak6 ballout and package information r datasheet 321 table 14-2. gmch/mch ballout for ddr2 systems (sorted by signal name) intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 ball # vss vss vss ak7 vss vss vss ak8 vss vss vss al10 vss vss vss al13 vss vss vss al16 vss vss vss al19 vss vss vss al22 vss vss vss al32 vss vss vss am29 vss vss vss am31 vss vss vss am4 vss vss vss am6 vss vss vss am7 vss vss vss am8 vss vss vss an1 vss vss vss ap8 vss vss vss ar13 vss vss vss ar17 vss vss vss ar21 vss vss vss ar25 vss vss vss ar3 vss vss vss ar30 vss vss vss ar6 vss vss vss b10 vss vss vss b12 vss vss vss b14 vss vss vss b16 vss vss vss b18 vss vss vss b2 vss vss vss b24 vss vss vss b28 vss vss vss b5 vss vss vss b6 vss vss vss b7 vss vss vss b8 vss vss vss b9 vss vss vss c1 vss vss vss c11 vss vss vss c13 vss vss vss c17 vss vss vss c18 vss vss vss c23 vss vss vss c3 ballout and package information r 322 datasheet table 14-2. gmch/mch ballout for ddr2 systems (sorted by signal name) intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 ball # vss vss vss c35 vss vss vss c4 vss vss vss d10 vss vss vss d11 vss vss vss d15 vss vss vss d16 vss vss vss d18 vss vss vss d23 vss vss vss d25 vss vss vss d26 vss vss vss d28 vss vss vss d3 vss vss vss d30 vss vss vss d31 vss vss vss d32 vss vss vss d4 vss vss vss d6 vss vss vss d7 vss vss vss d8 vss vss vss d9 vss vss vss e1 vss vss vss e10 vss vss vss e17 vss vss vss e18 vss vss vss e2 vss vss vss e23 vss vss vss e26 vss vss vss e29 vss vss vss e4 vss vss vss e6 vss vss vss e8 vss vss vss f10 vss vss vss f16 vss vss vss f18 vss vss vss f2 vss vss vss f23 vss vss vss f25 vss vss vss f29 vss vss vss f30 vss vss vss f32 vss vss vss f35 vss vss vss f4 vss vss vss f5 ballout and package information r datasheet 323 table 14-2. gmch/mch ballout for ddr2 systems (sorted by signal name) intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 ball # vss vss vss f6 vss vss vss f8 vss vss vss g10 vss vss vss g11 vss vss vss g13 vss vss vss g15 vss vss vss g17 vss vss vss g19 vss vss vss g2 vss vss vss g20 vss vss vss g23 vss vss vss g26 vss vss vss g27 vss vss vss g28 vss vss vss g4 vss vss vss g7 vss vss vss g8 vss vss vss g9 vss vss vss h10 vss vss vss h13 vss vss vss h2 vss vss vss h21 vss vss vss h24 vss vss vss h25 vss vss vss h27 vss vss vss h30 vss vss vss h32 vss vss vss h34 vss vss vss h4 vss vss vss h5 vss vss vss h6 vss vss vss h9 vss vss vss j10 vss vss vss j15 vss vss vss j16 vss vss vss j17 vss vss vss j18 vss vss vss j2 vss vss vss j20 vss vss vss j23 vss vss vss j30 vss vss vss j4 vss vss vss j7 ballout and package information r 324 datasheet table 14-2. gmch/mch ballout for ddr2 systems (sorted by signal name) intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 ball # vss vss vss j8 vss vss vss j9 vss vss vss k10 vss vss vss k11 vss vss vss k14 vss vss vss k2 vss vss vss k20 vss vss vss k24 vss vss vss k26 vss vss vss k28 vss vss vss k31 vss vss vss k32 vss vss vss k35 vss vss vss k4 vss vss vss k5 vss vss vss k6 vss vss vss k9 vss vss vss l11 vss vss vss l13 vss vss vss l15 vss vss vss l16 vss vss vss l17 vss vss vss l18 vss vss vss l2 vss vss vss l20 vss vss vss l21 vss vss vss l22 vss vss vss l24 vss vss vss l27 vss vss vss l30 vss vss vss l32 vss vss vss l4 vss vss vss l7 vss vss vss l8 vss vss vss l9 vss vss vss m10 vss vss vss m11 vss vss vss m17 vss vss vss m2 vss vss vss m20 vss vss vss m24 vss vss vss m25 vss vss vss m27 ballout and package information r datasheet 325 table 14-2. gmch/mch ballout for ddr2 systems (sorted by signal name) intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 ball # vss vss vss m29 vss vss vss m34 vss vss vss m4 vss vss vss m5 vss vss vss m6 vss vss vss m9 vss vss vss n10 vss vss vss n11 vss vss vss n17 vss vss vss n19 vss vss vss n2 vss vss vss n25 vss vss vss n28 vss vss vss n30 vss vss vss n32 vss vss vss n4 vss vss vss n7 vss vss vss n8 vss vss vss n9 vss vss vss p11 vss vss vss p16 vss vss vss p18 vss vss vss p2 vss vss vss p20 vss vss vss p25 vss vss vss p27 vss vss vss p29 vss vss vss p31 vss vss vss p32 vss vss vss p35 vss vss vss p4 vss vss vss p5 vss vss vss p6 vss vss vss p9 vss vss vss r11 vss vss vss r17 vss vss vss r19 vss vss vss r2 vss vss vss r21 vss vss vss r25 vss vss vss r26 vss vss vss r27 vss vss vss r4 ballout and package information r 326 datasheet table 14-2. gmch/mch ballout for ddr2 systems (sorted by signal name) intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 ball # vss vss vss r7 vss vss vss r8 vss vss vss r9 vss vss vss t10 vss vss vss t11 vss vss vss t18 vss vss vss t2 vss vss vss t22 vss vss vss t25 vss vss vss t28 vss vss vss t30 vss vss vss t32 vss vss vss t34 vss vss vss t4 vss vss vss t5 vss vss vss t6 vss vss vss t7 vss vss vss u11 vss vss vss u15 vss vss vss u17 vss vss vss u19 vss vss vss u2 vss vss vss u21 vss vss vss u23 vss vss vss u25 vss vss vss u27 vss vss vss u29 vss vss vss u31 vss vss vss u32 vss vss vss u4 vss vss vss u7 vss vss vss u8 vss vss vss u9 vss vss vss v1 vss vss vss v11 vss vss vss v16 vss vss vss v18 vss vss vss v2 vss vss vss v20 vss vss vss v22 vss vss vss v25 vss vss vss v26 vss vss vss v27 ballout and package information r datasheet 327 table 14-2. gmch/mch ballout for ddr2 systems (sorted by signal name) intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 ball # vss vss vss v35 vss vss vss v4 vss vss vss v6 vss vss vss v9 vss vss vss w11 vss vss vss w15 vss vss vss w17 vss vss vss w19 vss vss vss w21 vss vss vss w23 vss vss vss w25 vss vss vss w28 vss vss vss w30 vss vss vss w32 vss vss vss y11 vss vss vss y18 vss vss vss y22 vss vss vss y25 vss vss vss y27 vss vss vss y29 vss vss vss y31 vss vss vss y32 vss vss vss y34 rsv vssa_dac vssa_dac f13 rsv vsync vsync d12 vtt vtt vtt a19 vtt vtt vtt a20 vtt vtt vtt a21 vtt vtt vtt a22 vtt vtt vtt b19 vtt vtt vtt b20 vtt vtt vtt b21 vtt vtt vtt b22 vtt vtt vtt c19 vtt vtt vtt c20 vtt vtt vtt c21 vtt vtt vtt c22 vtt vtt vtt d19 vtt vtt vtt d20 vtt vtt vtt d21 vtt vtt vtt d22 vtt vtt vtt e19 vtt vtt vtt e20 ballout and package information r 328 datasheet table 14-2. gmch/mch ballout for ddr2 systems (sorted by signal name) intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 ball # vtt vtt vtt e21 vtt vtt vtt e22 vtt vtt vtt f20 vtt vtt vtt f21 vtt vtt vtt f22 vtt vtt vtt g21 vtt vtt vtt g22 vtt vtt vtt h22 notes: 1. ddr2, pci express* x16 graphics interface, no dac, no intel ? sdvo 2. ddr2, pci express* x16 graphics interface, dac, intel ? sdvo 3. ddr2, no pci express* x16 graphics interface, dac, intel ? sdvo ballout and package information r datasheet 329 14.2 ddr ballout figure 14-4, figure 14-5, and figure 14-6 show the 82915g gmch ballout for platforms using ddr system memory, as viewed from the top side of the package. figure 14-4 shows columns 1?12; figure 14-5 shows columns 13?24; figure 14-6 shows columns 25?35. the complete ddr ballout for both the 82915g/82915gv/82915GL gmch and 82915p/82915pl mch are listed in table 2-1and table 14-4 is sorted by ball number. table 14-4 is sorted alphabetically by signal name based on the signal names of the 82915g gmch. note that the first table has more entries than the second table. the second table does not include unpopulated balls whereas the first table does. note: balls that are listed as rsv are reserved. board traces should not be routed to these balls. note: balls that are listed as nc are no connects. boar d traces to these balls are permitted as specified. ballout and package information r 330 datasheet figure 14-4. intel ? 82915g gmch ballout for ddr (top view: columns 1?12 ) 1 2 3 4 5 6 7 8 9 10 11 12 a nc vss vss exp_txn3 exp_txp3 exp_txn1 exp_txp1 vss gclkp vcca_ dplla b nc vss exp_rxp4 exp_rxn4 vss vss vss vss vss vss gclkn vss c vss exp_txp5 vss vss exp_txn4 exp_txp4 exp_ txn2 exp_txp2 exp_txn0 exp_txp0 vss d exp_txn5 vss vss exp_rxp5 vss vss vss vss vss vss vsync e vss vss exp_txp6 vss exp_rxn5 vss exp_rxn3 vss exp_rxn2 vss exp_rxp0 hsync f exp_txp7 vss exp_txn6 vss vss vss exp_rxp3 vss exp_rxp2 vss exp_rxn0 nc g exp_txn7 vss exp_txp8 vss exp_rxn6 exp_rxp6 vss vss vss vss vss nc h exp_txp9 vss exp_txn8 vss vss vss exp_rxn7 exp_rxp7 vss vss exp_rxn1 nc j exp_ txn9 vss exp_ txp10 vss exp_rxn8 exp_rxp8 vss vss vss vss exp_rxp1 nc k exp_ txp11 vss exp_ txn10 vss vss vss exp_rxn9 exp_rxp9 vss vss vss nc l exp_ txn11 vss exp_ txp12 vss exp_ rxn10 exp_ rxp10 vss vss vss vcc vss nc m exp_ txp13 vss exp_ txn12 vss vss vss exp_ rxn12 exp_ rxp12 vss vss vss dref clkn n exp_ txn13 vss exp_ txp14 vss exp_ rxn13 exp_ rxp13 vss vss vss vss vss nc p exp_ txp15 vss exp_ txn14 vss vss vss exp_ rxp14 exp_ rxn14 vss exp_ rxp11 vss nc r exp_ txn15 vss dmi_txp0 vss exp_rxn1 5 exp_ rxp15 vss vss vss exp_ rxn11 vss nc t dmi_txp1 vss dmi_txn0 vss vss vss vss dmi_rxn1 dmi_rxp1 vss vss nc u dmi_txn1 vss dmi_txp2 vss dmi_rxp0 dmi_rxn0 vss vss vss dmi_rxn3 vss nc v vss vss dmi_txn2 vss dmi_txp3 vss dmi_rxp2 dmi_rxn2 vss dmi_rxp3 vss nc w vcc_exp vcc_exp vcc_exp vcc_exp dmi_txn3 vcc_exp vcc_exp vcc_exp vcc_exp exp_ compi vss nc y vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp exp_ compo vss nc aa vss vss vss vss vss vss vss vss vss vss vss nc ab vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc nc ac vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc rsv ad vcc vcc vcc vcc v cc vcc vcc vcc vcc vcc vss sdq_b20 ae sdq_a5 sdq_a4 sdq_a0 vss rsv vss smvref0 smvref1 vss sm_slew out1 sdq_b11 vss af vss sdm_a0 sdq_a1 vss rsv vss rstin# vss sm_slewi n1 vss sdq_b10 vss ag sdqs_a0 rsv sdq_a6 srcomp0 vss nc pwrok srcomp1 sdq_b4 sdq_b14 sdq_b15 vss ah vss sdq_a2 sdq_a7 sdq_b5 vss vss sd q_b0 vss sdm_b1 rsv vss sdq_b21 aj sdq_a8 sdq_a3 sdq_a12 vss sdm_b0 sd q_b1 sdq_b8 sdq_b12 vss vss sclk_b1# sm_ slewin0 ak vss sdq_a9 sdq_a13 vss sdqs_b 0 vss vss vss sclk_b4 sdqs_b1 vss sm_sle wout0 al sdm_a1 rsv sdqs_a1 rsv sdq_ b2 sdq_b7 sdq_b9 sdq_b13 sclk_b4# vss sclk_b1 scke_a0 am sclk_a4 sclk_a4# vss sdq_b6 vss vss vss scke_b1 vccsm vccsm sma_b12 an vss sclk_a1 sclk_a1# sdq_a10 sdq_a20 sdq_b3 sdm_a2 sdq_a18 sdq_a23 scke_b0 scke_a1 ap nc sdq_a14 sdq_a15 sdq_a11 sdq_a16 sdq_a21 sdqs_a2 vss sdq_a19 scke_b2 scke_a2 vccsm ar nc nc vss sdq_a17 vss rsv sdq_a22 sc ke_b3 vccsm scke_a3 sma_b11 1 2 3 4 5 6 7 8 9 10 11 12 ballout and package information r datasheet 331 figure 14-5. intel ? 82915g gmch ballout for ddr (top view: columns 13?24 ) 13 14 15 16 17 18 19 20 21 22 23 24 a vcc2 vcca_ exppll refset exp_slr vcca_ hpll vss vtt vtt vtt vtt hswing hvref b vcca_ dpllb vss rsv vss vcca_ smpll vss vtt vtt vtt vtt hrcomp vss c vss rsv mtype nc vss vss vtt vtt vtt vtt vss d vcca_ dac green vss vss bsel2 vss vtt vtt vtt vtt vss hscomp e vcca_dac green# bsel1 nc vss vss vtt vtt vtt vtt vss hd62 f vssa_dac red rsv vss hd47 vss hdstbn2# vtt vtt vtt vss nc g vss red# vss rsv vss hd45 vss vss vtt vtt vss hcpurst # h vss blue nc bsel0 nc hd46 hd41 hd40 vss vtt hd37 vss j sdvo_ctr lclk blue# vss vss vss vss hdstbp2# vss hd35 hd32 vss hd33 k sdvo_ ctrldata vss rsv extts# hd44 hd43 hdinv2# vss hd39 hd34 hd31 vss l vss ddc_data vss vss vss vss nc vss vss vss hd30 vss m drefclkp ich_sync# ddc_clk rsv vss hd42 hd38 vss hd36 hclkn hclkp vss n vcc vcc vcc vcc vss v cc vss vcc vcc nc nc nc p vcc vcc vcc vss vcc vss vcc vss vcc vcc nc nc r vcc vcc vcc vcc vss v cc vss vcc vss vcc vcc nc t vcc vcc vcc vcc vcc vss vcc vcc vcc vss vcc vcc u vcc vcc vss vcc vss vcc vss vcc vss vcc vss vcc v vcc vcc vcc vss vcc vss vcc vss vcc vss vcc vcc w vcc vcc vss vcc vss vcc vss vcc vss vcc vss vcc y vcc vcc vcc vcc vcc vss vcc vcc vcc vss vcc vcc aa vcc vcc vss vcc vss vcc vss vcc vcc vcc vcc vcc ab vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc ac rsv rsv rsv rsv rsv r sv rsv rsv rsv rsv nc nc ad vss sdq_b19 sdq_b23 vss sdq_a26 sdq_b24 vss sdqs_b3 sdq_b31 vss sdq_b36 sdm_b6 ae sdq_b16 vss vss rsv_tp0 vss vss sdq_a30 vss vss sdq_b26 vss vss af sdq_b17 sdq_b22 vss sdq_a28 sdqs_a3 vss sd q_a27 rsv vss sdq_b30 sdq_b32 sdq_b37 ag vss sdq_b18 vss vss rsv vss vss sdm_ b3 vss vss sclk_b0# sdm_b4 ah sdm_b2 vss rsv_tp1 sdm_a3 vss sdq_a 31 sdq_b29 vss sdq_b27 sclk_b0 vss nc aj vss nc vss vss sdq_a29 rsv vss rsv rsv vss rsv rsv ak sdqs_b2 vss rsv_tp3 sdq_a24 vss r sv sdq_b25 vss rsv sclk_b3# vss rsv al vss rsv sma_b7 vss sdq_a25 sdq_ b28 vss rsv rsv vss sclk_b3 rsv am vccsm vccsm sma_a9 vccsm vccsm sma_b0 vccsm vccsm sma_a4 vccsm vccsm sclk_a0 an sma_b9 rsv_tp2 sma_b5 sma_a7 sma_b2 sm a_a8 nc sma_b10 sma_a2 sma_a0 sma_a10 ap sma_a12 sma_b8 sma_a11 vccsm sma_b6 sma_b1 sma_a5 vccsm sma_a3 sma_a1 rsv vccsm ar vss vccsm sma_b4 sma_b3 vss vccsm sbs_b1 sma_a6 vss vccsm rsv rsv 13 14 15 16 17 18 19 20 21 22 23 24 ballout and package information r 332 datasheet figure 14-6. intel ? 82915g gmch ballout for ddr (top view: columns 25?35 ) 25 26 27 28 29 30 31 32 33 34 35 hd48 vss hd61 hd57 hd55 vss hd53 vss nc nc a hd63 hdinv3# hd54 vss hdstbp3# hd51 hd52 hd15 hd13 hd11 nc b hd58 hd59 hd49 hd56 hdstbn3# hd17 hd50 hd14 hd9 hd12 vss c vss vss hd60 vss hd18 vss vss vss hd10 hd8 d hd25 vss hd24 hd16 vss hbpri# hpcreq# hreq1# hdstbp0# hdinv0# hdstbn0# e vss hdstbn1# hd23 hd22 vss vss hreq4# vss hreq0# hd6 vss f hd26 vss vss vss hd20 ha6# hreq3# ha7# hd7 hd5 hd3 g vss hdstbp1# vss hd19 ha3# vss hreq2# vss hd1 vss hd4 h hd27 hdinv1# hd21 ha13# ha5# vss ha dstb0# hrs2# hd0 hd2 hdefer# j hd28 vss ha14# vss ha4# ha8# vss vss ha15# hrs0# vss k hd29 ha18# vss ha12# ha9# vss ha11# vss hlock# hhit# hdbsy# l vss ha20# vss ha16# vss ha10# hads# hdrdy# vss hbnr# m vss ha19# hadstb1# vss ha23# vss ha21# vss ha26# htrdy# hhitm# n vss ha22# vss ha24# vss nc vss vss hedrdy# hrs1# vss p vss vss vss ha25# ha17# rsv rsv sdq_a58 hbreq0# sdq_a59 rsv r vss ha30# ha27# vss ha31# vss ha28# vss sdq_a62 vss sdq_a63 t vss sdq_b58 vss ha29# vss rsv vss vss sdm_a7 sdqs_a7 rsv u vss vss vss sdq_b63 sdq_b59 rsv rsv rsv sdq_a57 sdq_a56 vss v vss sdq_b62 sdqs_b7 vss sdq_b57 vss sd m_b7 vss sdq_a61 sdq_a51 sdq_a60 w vss sdq_b60 vss rsv vss rsv vss vss sdq_a50 vss sdq_a55 y vss vss vss sdq_b61 sdq_b56 rsv rsv sdq_a54 sdm_a6 sdqs_a6 rsv aa vss sdq_b51 sdq_b50 vss rsv vss sd qs_b6 vss sma_a13 sclk_a2 vss ab vss sdq_b55 vss sdq_b54 vss rsv vss vss sclk_a2# sclk_a5# sclk_a5 ac vss vss vss sclk_b5# sclk_b5 nc sdq_a52 sma_b13 vss sdq_a53 ad sclk_b2# sclk_b2 sdq_b53 vss sdq_b52 vss sdq_b48 vss sdq_a47 sdq_a49 sdq_a48 ae sdq_b33 vss sdq_b49 sdq_b47 vss vss vss vss sdq_a46 sdq_a43 vss af vss rsv sdq_b46 vss vss sdq_b42 sdq_b 43 sdq_a42 rsv sdm_a5 sdqs_a5 ag sdqs_b4 vss sdq_a32 sdqs_b5 vss r sv sdm_b5 vss sdq_a45 vss sdq_a41 ah sdq_b38 sdq_b35 vss sdq_a37 sdq_b 40 vss sdq_b41 vss sdq_a44 sdq_a40 vss aj vss vss sdq_a33 vss sdm_a4 vss sdq_a35 sdq_b45 sdq_b44 scs_a2# vccsm ak sdq_b34 sdq_b39 sdq_a36 nc rsv sdq_a 38 sdq_a39 vss scs_a3# scas_a# scs_a1# al vccsm vccsm sbs_b0 vccsm vss sdqs_a4 vss vccsm scs_b3# scs_a0# am sclk_a0# sclk_a3# scas_b# sbs_a0 sras_a# sdq_a34 rsv rsv scs_b2# scs_b1# vccsm an sclk_a3 sbs_a1 sras_b# vccsm rsv rsv swe_a# rsv rsv scs_b0# nc ap vss vccsm swe_b# rsv rsv vss vccsm vccsm nc nc ar 25 26 27 28 29 30 31 32 33 34 35 ballout and package information r datasheet 333 table 14-3. gmch/mch ballout for ddr systems (sorted by ball number) ball # intel ? 82915GL gmch 6 intel ? 82915pl mch 5 intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 intel ? 82910gl gmch 4 a1 ? ? ? ? ? ? a2 nc nc nc nc nc nc a3 vss vss vss vss vss vss a4 ? ? ? ? ? ? a5 vss vss vss vss vss vss a6 sdvob_clk - exp_txn3 exp_txn3 exp_txn3 sdvob_clk- sdvob_clk- a7 sdvob_clk + exp_txp3 exp_txp3 exp_txp3 sdvob_clk+ sdvob_clk+ a8 sdvob_gre en- exp_txn1 exp_txn1 exp_txn1 sdvob_gree n- sdvob_green- a9 sdvob_gre en+ exp_txp1 exp_txp1 exp_txp1 sdvob_gree n+ sdvob_green+ a10 vss vss vss vss vss vss a11 gclkp gclkp gclkp gclkp gclkp gclkp a12 vcca_dpll a vcca_dplla vcca_dplla vcca_d plla vcca_dplla vcca_dplla a13 vcc2 vcc2 vcc2 vcc2 vcc2 vcc2 a14 vcca_expp ll vcca_exppl l vcca_exppll vcca_exppll vcca_exppll vcca_exppll a15 refset rsv rsv ref set refset refset a16 rsv exp_slr exp_slr exp_slr rsv rsv a17 vcca_hpll vcca_hpll vcca_hpll vcca_hpll vcca_hpll vcca_hpll a18 vss vss vss vss vss vss a19 vtt vtt vtt vtt vtt vtt a20 vtt vtt vtt vtt vtt vtt a21 vtt vtt vtt vtt vtt vtt a22 vtt vtt vtt vtt vtt vtt a23 hswing hswing hswing hswing hswing hswing a24 hvref hvref hvref hvref hvref hvref a25 hd48 hd48 hd48 hd48 hd48 hd48 a26 vss vss vss vss vss vss a27 hd61 hd61 hd61 hd61 hd61 hd61 a28 hd57 hd57 hd57 hd57 hd57 hd57 a29 hd55 hd55 hd55 hd55 hd55 hd55 a30 vss vss vss vss vss vss a31 hd53 hd53 hd53 hd53 hd53 hd53 a32 ? ? ? ? ? ? a33 vss vss vss vss vss vss a34 nc nc nc nc nc nc ballout and package information r 334 datasheet ball # intel ? 82915GL gmch 6 intel ? 82915pl mch 5 intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 intel ? 82910gl gmch 4 a35 nc nc nc nc nc nc b1 nc nc nc nc nc nc b2 vss vss vss vss vss vss b3 rsv exp_rxp4 exp_rxp4 exp_rxp4 rsv rsv b4 rsv exp_rxn4 exp_rxn4 exp_rxn4 rsv rsv b5 vss vss vss vss vss vss b6 vss vss vss vss vss vss b7 vss vss vss vss vss vss b8 vss vss vss vss vss vss b9 vss vss vss vss vss vss b10 vss vss vss vss vss vss b11 gclkn gclkn gclkn gclkn gclkn gclkn b12 vss vss vss vss vss vss b13 vcca_dpll b vcca_dpllb vcca_dpllb vcca_d pllb vcca_dpllb vcca_dpllb b14 vss vss vss vss vss vss b15 rsv rsv rsv rsv rsv rsv b16 vss vss vss vss vss vss b17 vcca_smpl l vcca_smpll vcca_smpll vcca_s mpll vcca_smpll vcca_smpll b18 vss vss vss vss vss vss b19 vtt vtt vtt vtt vtt vtt b20 vtt vtt vtt vtt vtt vtt b21 vtt vtt vtt vtt vtt vtt b22 vtt vtt vtt vtt vtt vtt b23 hrcomp hrcomp hrcomp hrcomp hrcomp hrcomp b24 vss vss vss vss vss vss b25 hd63 hd63 hd63 hd63 hd63 hd63 b26 hdinv3# hdinv3# hdinv3# hdinv3# hdinv3# hdinv3# b27 hd54 hd54 hd54 hd54 hd54 hd54 b28 vss vss vss vss vss vss b29 hdstbp3# hdstbp3# hdstbp3# hdstbp3# hdstbp3# hdstbp3# b30 hd51 hd51 hd51 hd51 hd51 hd51 b31 hd52 hd52 hd52 hd52 hd52 hd52 b32 hd15 hd15 hd15 hd15 hd15 hd15 b33 hd13 hd13 hd13 hd13 hd13 hd13 b34 hd11 hd11 hd11 hd11 hd11 hd11 b35 nc nc nc nc nc nc c1 vss vss vss vss vss vss ballout and package information r datasheet 335 ball # intel ? 82915GL gmch 6 intel ? 82915pl mch 5 intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 intel ? 82910gl gmch 4 c2 sdvoc_gre en+ exp_txp5 exp_txp5 exp_txp5 sdvoc_gree n+ sdvoc_green+ c3 vss vss vss vss vss vss c4 vss vss vss vss vss vss c5 sdvoc_red -/ sdvob_alp ha- exp_txn4 exp_txn4 exp_txn4 sdvoc_red-/ sdvob_alpha - sdvoc_red-/ sdvob_alpha- c6 sdvoc_red +/ sdvob_alp ha+ exp_txp4 exp_txp4 exp_txp4 sdvoc_red+/ sdvob_alpha + sdvoc_red+/ sdvob_alpha+ c7 sdvob_blu e- exp_txn2 exp_txn2 exp_txn2 sdvob_blue- sdvob_blue- c8 sdvob_blu e+ exp_txp2 exp_txp2 exp_txp2 sdvob_blue+ sdvob_blue+ c9 sdvob_red - exp_txn0 exp_txn0 exp_txn0 sdvob_red- sdvob_red- c10 sdvob_red + exp_txp0 exp_txp0 exp_txp0 sdvob_red+ sdvob_red+ c11 vss vss vss vss vss vss c12 ? ? ? ? ? ? c13 vss vss vss vss vss vss c14 rsv rsv rsv rsv rsv rsv c15 mtype mtype mtype mtype mtype mtype c16 nc nc nc nc nc nc c17 vss vss vss vss vss vss c18 vss vss vss vss vss vss c19 vtt vtt vtt vtt vtt vtt c20 vtt vtt vtt vtt vtt vtt c21 vtt vtt vtt vtt vtt vtt c22 vtt vtt vtt vtt vtt vtt c23 vss vss vss vss vss vss c24 ? ? ? ? ? ? c25 hd58 hd58 hd58 hd58 hd58 hd58 c26 hd59 hd59 hd59 hd59 hd59 hd59 c27 hd49 hd49 hd49 hd49 hd49 hd49 c28 hd56 hd56 hd56 hd56 hd56 hd56 c29 hdstbn3# hdstbn3# hdstbn3# hdstbn3# hdstbn3# hdstbn3# c30 hd17 hd17 hd17 hd17 hd17 hd17 c31 hd50 hd50 hd50 hd50 hd50 hd50 c32 hd14 hd14 hd14 hd14 hd14 hd14 c33 hd9 hd9 hd9 hd9 hd9 hd9 ballout and package information r 336 datasheet ball # intel ? 82915GL gmch 6 intel ? 82915pl mch 5 intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 intel ? 82910gl gmch 4 c34 hd12 hd12 hd12 hd12 hd12 hd12 c35 vss vss vss vss vss vss d1 ? ? ? ? ? ? d2 sdvoc_gre en- exp_txn5 exp_txn5 exp_txn5 sdvoc_gree n- sdvoc_green- d3 vss vss vss vss vss vss d4 vss vss vss vss vss vss d5 sdvoc_int + exp_rxp5 exp_rxp5 exp_rxp5 sdvoc_int+ sdvoc_int+ d6 vss vss vss vss vss vss d7 vss vss vss vss vss vss d8 vss vss vss vss vss vss d9 vss vss vss vss vss vss d10 vss vss vss vss vss vss d11 vss vss vss vss vss vss d12 vsync rsv rsv vsync vsync vsync d13 vcca_dac rsv rsv vcca_dac vcca_dac vcca_dac d14 green rsv rsv green green green d15 vss vss vss vss vss vss d16 vss vss vss vss vss vss d17 bsel2 bsel2 bsel2 bsel2 bsel2 bsel2 d18 vss vss vss vss vss vss d19 vtt vtt vtt vtt vtt vtt d20 vtt vtt vtt vtt vtt vtt d21 vtt vtt vtt vtt vtt vtt d22 vtt vtt vtt vtt vtt vtt d23 vss vss vss vss vss vss d24 hscomp hscomp hscomp hscomp hscomp hscomp d25 vss vss vss vss vss vss d26 vss vss vss vss vss vss d27 hd60 hd60 hd60 hd60 hd60 hd60 d28 vss vss vss vss vss vss d29 hd18 hd18 hd18 hd18 hd18 hd18 d30 vss vss vss vss vss vss d31 vss vss vss vss vss vss d32 vss vss vss vss vss vss d33 hd10 hd10 hd10 hd10 hd10 hd10 d34 hd8 hd8 hd8 hd8 hd8 hd8 d35 ? ? ? ? ? ? e1 vss vss vss vss vss vss ballout and package information r datasheet 337 ball # intel ? 82915GL gmch 6 intel ? 82915pl mch 5 intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 intel ? 82910gl gmch 4 e2 vss vss vss vss vss vss e3 sdvoc_blu e+ exp_txp6 exp_txp6 exp_txp6 sdvoc_blue+ sdvoc_blue+ e4 vss vss vss vss vss vss e5 sdvoc_int- exp_rxn5 exp_rxn5 exp_rxn5 sdvoc_int- sdvoc_int- e6 vss vss vss vss vss vss e7 rsv exp_rxn3 exp_rxn3 exp_rxn3 rsv rsv e8 vss vss vss vss vss vss e9 sdvoc_sta ll- exp_rxn2 exp_rxn2 exp_rxn2 sdvoc_stall - sdvoc_stall- e10 vss vss vss vss vss vss e11 sdvoc_tvc lkin+ exp_rxp0 exp_rxp0 exp_rxp0 sdvoc_tvclk in+ sdvoc_tvclkin+ e12 hsync rsv rsv hsync hsync hsync e13 vcca_dac rsv rsv vcca_dac vcca_dac vcca_dac e14 green# rsv rsv green# green# green# e15 bsel1 bsel1 bsel1 bsel1 bsel1 bsel1 e16 nc nc nc nc nc nc e17 vss vss vss vss vss vss e18 vss vss vss vss vss vss e19 vtt vtt vtt vtt vtt vtt e20 vtt vtt vtt vtt vtt vtt e21 vtt vtt vtt vtt vtt vtt e22 vtt vtt vtt vtt vtt vtt e23 vss vss vss vss vss vss e24 hd62 hd62 hd62 hd62 hd62 hd62 e25 hd25 hd25 hd25 hd25 hd25 hd25 e26 vss vss vss vss vss vss e27 hd24 hd24 hd24 hd24 hd24 hd24 e28 hd16 hd16 hd16 hd16 hd16 hd16 e29 vss vss vss vss vss vss e30 hbpri# hbpri# hbpri# hbpri# hbpri# hbpri# e31 hpcreq# hpcreq# hpcreq# hpcreq# hpcreq# hpcreq# e32 hreq1# hreq1# hreq1# hreq1# hreq1# hreq1# e33 hdstbp0# hdstbp0# hdstbp0# hdstbp0# hdstbp0# hdstbp0# e34 hdinv0# hdinv0# hdinv0# hdinv0# hdinv0# hdinv0# e35 hdstbn0# hdstbn0# hdstbn0# hdstbn0# hdstbn0# hdstbn0# f1 exp_txp7 exp_txp7 exp_txp7 exp_txp7 exp_txp7 exp_txp7 f2 vss vss vss vss vss vss f3 sdvoc_blu e- exp_txn6 exp_txn6 exp_txn6 sdvoc_blue- sdvoc_blue- ballout and package information r 338 datasheet ball # intel ? 82915GL gmch 6 intel ? 82915pl mch 5 intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 intel ? 82910gl gmch 4 f4 vss vss vss vss vss vss f5 vss vss vss vss vss vss f6 vss vss vss vss vss vss f7 rsv exp_rxp3 exp_rxp3 exp_rxp3 rsv rsv f8 vss vss vss vss vss vss f9 sdvoc_sta ll+ exp_rxp2 exp_rxp2 exp_rxp2 sdvoc_stall + sdvoc_stall+ f10 vss vss vss vss vss vss f11 sdvoc_tvc lkin- exp_rxn0 exp_rxn0 exp_rxn0 sdvoc_tvclk in- sdvoc_tvclkin- f12 nc nc nc nc nc nc f13 vssa_dac rsv rsv vssa_dac vssa_dac vssa_dac f14 red rsv rsv red red red f15 rsv rsv rsv rsv rsv rsv f16 vss vss vss vss vss vss f17 hd47 hd47 hd47 hd47 hd47 hd47 f18 vss vss vss vss vss vss f19 hdstbn2# hdstbn2# hdstbn2# hdstbn2# hdstbn2# hdstbn2# f20 vtt vtt vtt vtt vtt vtt f21 vtt vtt vtt vtt vtt vtt f22 vtt vtt vtt vtt vtt vtt f23 vss vss vss vss vss vss f24 nc nc nc nc nc nc f25 vss vss vss vss vss vss f26 hdstbn1# hdstbn1# hdstbn1# hdstbn1# hdstbn1# hdstbn1# f27 hd23 hd23 hd23 hd23 hd23 hd23 f28 hd22 hd22 hd22 hd22 hd22 hd22 f29 vss vss vss vss vss vss f30 vss vss vss vss vss vss f31 hreq4# hreq4# hreq4# hreq4# hreq4# hreq4# f32 vss vss vss vss vss vss f33 hreq0# hreq0# hreq0# hreq0# hreq0# hreq0# f34 hd6 hd6 hd6 hd6 hd6 hd6 f35 vss vss vss vss vss vss g1 sdvoc_clk - exp_txn7 exp_txn7 exp_txn7 sdvoc_clk- sdvoc_clk- g2 vss vss vss vss vss vss g3 rsv exp_txp8 exp_txp8 exp_txp8 rsv rsv g4 vss vss vss vss vss vss g5 rsv exp_rxn6 exp_rxn6 exp_rxn6 rsv rsv ballout and package information r datasheet 339 ball # intel ? 82915GL gmch 6 intel ? 82915pl mch 5 intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 intel ? 82910gl gmch 4 g6 rsv exp_rxp6 exp_rxp6 exp_rxp6 rsv rsv g7 vss vss vss vss vss vss g8 vss vss vss vss vss vss g9 vss vss vss vss vss vss g10 vss vss vss vss vss vss g11 vss vss vss vss vss vss g12 nc nc nc nc nc nc g13 vss vss vss vss vss vss g14 red# rsv rsv red# red# red# g15 vss vss vss vss vss vss g16 rsv rsv rsv rsv rsv rsv g17 vss vss vss vss vss vss g18 hd45 hd45 hd45 hd45 hd45 hd45 g19 vss vss vss vss vss vss g20 vss vss vss vss vss vss g21 vtt vtt vtt vtt vtt vtt g22 vtt vtt vtt vtt vtt vtt g23 vss vss vss vss vss vss g24 hcpurst# hcpurst# hcpurst# hcpurst# hcpurst# hcpurst# g25 hd26 hd26 hd26 hd26 hd26 hd26 g26 vss vss vss vss vss vss g27 vss vss vss vss vss vss g28 vss vss vss vss vss vss g29 hd20 hd20 hd20 hd20 hd20 hd20 g30 ha6# ha6# ha6# ha6# ha6# ha6# g31 hreq3# hreq3# hreq3# hreq3# hreq3# hreq3# g32 ha7# ha7# ha7# ha7# ha7# ha7# g33 hd7 hd7 hd7 hd7 hd7 hd7 g34 hd5 hd5 hd5 hd5 hd5 hd5 g35 hd3 hd3 hd3 hd3 hd3 hd3 h1 rsv exp_txp9 exp_txp9 exp_txp9 rsv rsv h2 vss vss vss vss vss vss h3 rsv exp_txn8 exp_txn8 exp_txn8 rsv rsv h4 vss vss vss vss vss vss h5 vss vss vss vss vss vss h6 vss vss vss vss vss vss h7 rsv exp_rxn7 exp_rxn7 exp_rxn7 rsv rsv h8 rsv exp_rxp7 exp_rxp7 exp_rxp7 rsv rsv h9 vss vss vss vss vss vss h10 vss vss vss vss vss vss ballout and package information r 340 datasheet ball # intel ? 82915GL gmch 6 intel ? 82915pl mch 5 intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 intel ? 82910gl gmch 4 h11 sdvob_int- exp_rxn1 exp_rxn1 exp_rxn1 sdvob_int- sdvob_int- h12 nc nc nc nc nc nc h13 vss vss vss vss vss vss h14 blue rsv rsv blue blue blue h15 nc nc nc nc nc nc h16 bsel0 bsel0 bsel0 bsel0 bsel0 bsel0 h17 nc nc nc nc nc nc h18 hd46 hd46 hd46 hd46 hd46 hd46 h19 hd41 hd41 hd41 hd41 hd41 hd41 h20 hd40 hd40 hd40 hd40 hd40 hd40 h21 vss vss vss vss vss vss h22 vtt vtt vtt vtt vtt vtt h23 hd37 hd37 hd37 hd37 hd37 hd37 h24 vss vss vss vss vss vss h25 vss vss vss vss vss vss h26 hdstbp1# hdstbp1# hdstbp1# hdstbp1# hdstbp1# hdstbp1# h27 vss vss vss vss vss vss h28 hd19 hd19 hd19 hd19 hd19 hd19 h29 ha3# ha3# ha3# ha3# ha3# ha3# h30 vss vss vss vss vss vss h31 hreq2# hreq2# hreq2# hreq2# hreq2# hreq2# h32 vss vss vss vss vss vss h33 hd1 hd1 hd1 hd1 hd1 hd1 h34 vss vss vss vss vss vss h35 hd4 hd4 hd4 hd4 hd4 hd4 j1 rsv exp_txn9 exp_txn9 exp_txn9 rsv rsv j2 vss vss vss vss vss vss j3 rsv exp_txp10 exp_txp10 exp_txp10 rsv rsv j4 vss vss vss vss vss vss j5 rsv exp_rxn8 exp_rxn8 exp_rxn8 rsv rsv j6 rsv exp_rxp8 exp_rxp8 exp_rxp8 rsv rsv j7 vss vss vss vss vss vss j8 vss vss vss vss vss vss j9 vss vss vss vss vss vss j10 vss vss vss vss vss vss j11 sdvob_int+ exp_rxp1 exp_rxp1 exp_ rxp1 sdvob_int+ sdvob_int+ j12 nc nc nc nc nc nc j13 sdvo_ctrl clk rsv rsv sdvo_ctrlclk sdvo_ctrlcl k sdvo_ctrlclk j14 blue# rsv rsv blue# blue# blue# ballout and package information r datasheet 341 ball # intel ? 82915GL gmch 6 intel ? 82915pl mch 5 intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 intel ? 82910gl gmch 4 j15 vss vss vss vss vss vss j16 vss vss vss vss vss vss j17 vss vss vss vss vss vss j18 vss vss vss vss vss vss j19 hdstbp2# hdstbp2# hdstbp2# hdstbp2# hdstbp2# hdstbp2# j20 vss vss vss vss vss vss j21 hd35 hd35 hd35 hd35 hd35 hd35 j22 hd32 hd32 hd32 hd32 hd32 hd32 j23 vss vss vss vss vss vss j24 hd33 hd33 hd33 hd33 hd33 hd33 j25 hd27 hd27 hd27 hd27 hd27 hd27 j26 hdinv1# hdinv1# hdinv1# hdinv1# hdinv1# hdinv1# j27 hd21 hd21 hd21 hd21 hd21 hd21 j28 ha13# ha13# ha13# ha13# ha13# ha13# j29 ha5# ha5# ha5# ha5# ha5# ha5# j30 vss vss vss vss vss vss j31 hadstb0# hadstb0# hadstb0# hadstb0# hadstb0# hadstb0# j32 hrs2# hrs2# hrs2# hrs2# hrs2# hrs2# j33 hd0 hd0 hd0 hd0 hd0 hd0 j34 hd2 hd2 hd2 hd2 hd2 hd2 j35 hdefer# hdefer# hdefer# hdefer# hdefer# hdefer# k1 rsv exp_txp11 exp_txp11 exp_txp11 rsv rsv k2 vss vss vss vss vss vss k3 rsv exp_txn10 exp_txn10 exp_txn10 rsv rsv k4 vss vss vss vss vss vss k5 vss vss vss vss vss vss k6 vss vss vss vss vss vss k7 rsv exp_rxn9 exp_rxn9 exp_rxn9 rsv rsv k8 rsv exp_rxp9 exp_rxp9 exp_rxp9 rsv rsv k9 vss vss vss vss vss vss k10 vss vss vss vss vss vss k11 vss vss vss vss vss vss k12 nc nc nc nc nc nc k13 sdvo_ctrl data rsv rsv sdvo_ctrldata sdvo_ctrlda ta sdvo_ctrldata k14 vss vss vss vss vss vss k15 rsv rsv rsv rsv rsv rsv k16 extts# extts# extts# extts# extts# extts# k17 hd44 hd44 hd44 hd44 hd44 hd44 k18 hd43 hd43 hd43 hd43 hd43 hd43 ballout and package information r 342 datasheet ball # intel ? 82915GL gmch 6 intel ? 82915pl mch 5 intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 intel ? 82910gl gmch 4 k19 hdinv2# hdinv2# hdinv2# hdinv2# hdinv2# hdinv2# k20 vss vss vss vss vss vss k21 hd39 hd39 hd39 hd39 hd39 hd39 k22 hd34 hd34 hd34 hd34 hd34 hd34 k23 hd31 hd31 hd31 hd31 hd31 hd31 k24 vss vss vss vss vss vss k25 hd28 hd28 hd28 hd28 hd28 hd28 k26 vss vss vss vss vss vss k27 ha14# ha14# ha14# ha14# ha14# ha14# k28 vss vss vss vss vss vss k29 ha4# ha4# ha4# ha4# ha4# ha4# k30 ha8# ha8# ha8# ha8# ha8# ha8# k31 vss vss vss vss vss vss k32 vss vss vss vss vss vss k33 ha15# ha15# ha15# ha15# ha15# ha15# k34 hrs0# hrs0# hrs0# hrs0# hrs0# hrs0# k35 vss vss vss vss vss vss l1 rsv exp_txn11 exp_txn11 exp_txn11 rsv rsv l2 vss vss vss vss vss vss l3 rsv exp_txp12 exp_txp12 exp_txp12 rsv rsv l4 vss vss vss vss vss vss l5 rsv exp_rxn10 exp_rxn10 exp_rxn10 rsv rsv l6 rsv exp_rxp10 exp_rxp10 exp_rxp10 rsv rsv l7 vss vss vss vss vss vss l8 vss vss vss vss vss vss l9 vss vss vss vss vss vss l10 vcc vcc vcc vcc vcc vcc l11 vss vss vss vss vss vss l12 nc nc nc nc nc nc l13 vss vss vss vss vss vss l14 ddc_data rsv rsv ddc_data ddc_data ddc_data l15 vss vss vss vss vss vss l16 vss vss vss vss vss vss l17 vss vss vss vss vss vss l18 vss vss vss vss vss vss l19 nc nc nc nc nc nc l20 vss vss vss vss vss vss l21 vss vss vss vss vss vss l22 vss vss vss vss vss vss l23 hd30 hd30 hd30 hd30 hd30 hd30 ballout and package information r datasheet 343 ball # intel ? 82915GL gmch 6 intel ? 82915pl mch 5 intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 intel ? 82910gl gmch 4 l24 vss vss vss vss vss vss l25 hd29 hd29 hd29 hd29 hd29 hd29 l26 ha18# ha18# ha18# ha18# ha18# ha18# l27 vss vss vss vss vss vss l28 ha12# ha12# ha12# ha12# ha12# ha12# l29 ha9# ha9# ha9# ha9# ha9# ha9# l30 vss vss vss vss vss vss l31 ha11# ha11# ha11# ha11# ha11# ha11# l32 vss vss vss vss vss vss l33 hlock# hlock# hlock# hlock# hlock# hlock# l34 hhit# hhit# hhit# hhit# hhit# hhit# l35 hdbsy# hdbsy# hdbsy# hdbsy# hdbsy# hdbsy# m1 rsv exp_txp13 exp_txp13 exp_txp13 rsv rsv m2 vss vss vss vss vss vss m3 rsv exp_txn12 exp_txn12 exp_txn12 rsv rsv m4 vss vss vss vss vss vss m5 vss vss vss vss vss vss m6 vss vss vss vss vss vss m7 rsv exp_rxn12 exp_rxn12 exp_rxn12 rsv rsv m8 rsv exp_rxp12 exp_rxp12 exp_rxp12 rsv rsv m9 vss vss vss vss vss vss m10 vss vss vss vss vss vss m11 vss vss vss vss vss vss m12 drefclkn drefclkn drefclkn drefclkn drefclkn drefclkn m13 drefclkp drefclkp drefclkp drefclkp drefclkp drefclkp m14 ich_sync# ich_sync# ich_sync# ich_sync# ich_sync# ich_sync# m15 ddc_clk rsv rsv ddc_clk ddc_clk ddc_clk m16 rsv rsv rsv rsv rsv rsv m17 vss vss vss vss vss vss m18 hd42 hd42 hd42 hd42 hd42 hd42 m19 hd38 hd38 hd38 hd38 hd38 hd38 m20 vss vss vss vss vss vss m21 hd36 hd36 hd36 hd36 hd36 hd36 m22 hclkn hclkn hclkn hclkn hclkn hclkn m23 hclkp hclkp hclkp hclkp hclkp hclkp m24 vss vss vss vss vss vss m25 vss vss vss vss vss vss m26 ha20# ha20# ha20# ha20# ha20# ha20# m27 vss vss vss vss vss vss m28 ha16# ha16# ha16# ha16# ha16# ha16# ballout and package information r 344 datasheet ball # intel ? 82915GL gmch 6 intel ? 82915pl mch 5 intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 intel ? 82910gl gmch 4 m29 vss vss vss vss vss vss m30 ha10# ha10# ha10# ha10# ha10# ha10# m31 hads# hads# hads# hads# hads# hads# m32 hdrdy# hdrdy# hdrdy# hdrdy# hdrdy# hdrdy# m33 ? ? ? ? ? ? m34 vss vss vss vss vss vss m35 hbnr# hbnr# hbnr# hbnr# hbnr# hbnr# n1 rsv exp_txn13 exp_txn13 exp_txn13 rsv rsv n2 vss vss vss vss vss vss n3 rsv exp_txp14 exp_txp14 exp_txp14 rsv rsv n4 vss vss vss vss vss vss n5 rsv exp_rxn13 exp_rxn13 exp_rxn13 rsv rsv n6 rsv exp_rxp13 exp_rxp13 exp_rxp13 rsv rsv n7 vss vss vss vss vss vss n8 vss vss vss vss vss vss n9 vss vss vss vss vss vss n10 vss vss vss vss vss vss n11 vss vss vss vss vss vss n12 nc nc nc nc nc nc n13 vcc vcc vcc vcc vcc vcc n14 vcc vcc vcc vcc vcc vcc n15 vcc vcc vcc vcc vcc vcc n16 vcc vcc vcc vcc vcc vcc n17 vss vss vss vss vss vss n18 vcc vcc vcc vcc vcc vcc n19 vss vss vss vss vss vss n20 vcc vcc vcc vcc vcc vcc n21 vcc vcc vcc vcc vcc vcc n22 nc nc nc nc nc nc n23 nc nc nc nc nc nc n24 nc nc nc nc nc nc n25 vss vss vss vss vss vss n26 ha19# ha19# ha19# ha19# ha19# ha19# n27 hadstb1# hadstb1# hadstb1# hadstb1# hadstb1# hadstb1# n28 vss vss vss vss vss vss n29 ha23# ha23# ha23# ha23# ha23# ha23# n30 vss vss vss vss vss vss n31 ha21# ha21# ha21# ha21# ha21# ha21# n32 vss vss vss vss vss vss n33 ha26# ha26# ha26# ha26# ha26# ha26# ballout and package information r datasheet 345 ball # intel ? 82915GL gmch 6 intel ? 82915pl mch 5 intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 intel ? 82910gl gmch 4 n34 htrdy# htrdy# htrdy# htrdy# htrdy# htrdy# n35 hhitm# hhitm# hhitm# hhitm# hhitm# hhitm# p1 rsv exp_txp15 exp_txp15 exp_txp15 rsv rsv p2 vss vss vss vss vss vss p3 rsv exp_txn14 exp_txn14 exp_txn14 rsv rsv p4 vss vss vss vss vss vss p5 vss vss vss vss vss vss p6 vss vss vss vss vss vss p7 rsv exp_rxp14 exp_rxp14 exp_rxp14 rsv rsv p8 rsv exp_rxn14 exp_rxn14 exp_rxn14 rsv rsv p9 vss vss vss vss vss vss p10 rsv exp_rxp11 exp_rxp11 exp_rxp11 rsv rsv p11 vss vss vss vss vss vss p12 nc nc nc nc nc nc p13 vcc vcc vcc vcc vcc vcc p14 vcc vcc vcc vcc vcc vcc p15 vcc vcc vcc vcc vcc vcc p16 vss vss vss vss vss vss p17 vcc vcc vcc vcc vcc vcc p18 vss vss vss vss vss vss p19 vcc vcc vcc vcc vcc vcc p20 vss vss vss vss vss vss p21 vcc vcc vcc vcc vcc vcc p22 vcc vcc vcc vcc vcc vcc p23 nc nc nc nc nc nc p24 nc nc nc nc nc nc p25 vss vss vss vss vss vss p26 ha22# ha22# ha22# ha22# ha22# ha22# p27 vss vss vss vss vss vss p28 ha24# ha24# ha24# ha24# ha24# ha24# p29 vss vss vss vss vss vss p30 nc nc nc nc nc nc p31 vss vss vss vss vss vss p32 vss vss vss vss vss vss p33 hedrdy# hedrdy# hedrdy# hedrdy# hedrdy# hedrdy# p34 hrs1# hrs1# hrs1# hrs1# hrs1# hrs1# p35 vss vss vss vss vss vss r1 rsv exp_txn15 exp_txn15 exp_txn15 rsv rsv r2 vss vss vss vss vss vss r3 dmi_txp0 dmi_txp0 dmi_txp0 dmi_txp0 dmi_txp0 dmi_txp0 ballout and package information r 346 datasheet ball # intel ? 82915GL gmch 6 intel ? 82915pl mch 5 intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 intel ? 82910gl gmch 4 r4 vss vss vss vss vss vss r5 rsv exp_rxn15 exp_rxn15 exp_rxn15 rsv rsv r6 rsv exp_rxp15 exp_rxp15 exp_rxp15 rsv rsv r7 vss vss vss vss vss vss r8 vss vss vss vss vss vss r9 vss vss vss vss vss vss r10 rsv exp_rxn11 exp_rxn11 exp_rxn11 rsv rsv r11 vss vss vss vss vss vss r12 nc nc nc nc nc nc r13 vcc vcc vcc vcc vcc vcc r14 vcc vcc vcc vcc vcc vcc r15 vcc vcc vcc vcc vcc vcc r16 vcc vcc vcc vcc vcc vcc r17 vss vss vss vss vss vss r18 vcc vcc vcc vcc vcc vcc r19 vss vss vss vss vss vss r20 vcc vcc vcc vcc vcc vcc r21 vss vss vss vss vss vss r22 vcc vcc vcc vcc vcc vcc r23 vcc vcc vcc vcc vcc vcc r24 nc nc nc nc nc nc r25 vss vss vss vss vss vss r26 vss vss vss vss vss vss r27 vss vss vss vss vss vss r28 ha25# ha25# ha25# ha25# ha25# ha25# r29 ha17# ha17# ha17# ha17# ha17# ha17# r30 rsv rsv rsv rsv rsv rsv r31 rsv rsv rsv rsv rsv rsv r32 sdq_a58 sdq_a58 sdq_a58 sdq_a58 sdq_a58 sdq_a58 r33 hbreq0# hbreq0# hbreq0# hbreq0# hbreq0# hbreq0# r34 sdq_a59 sdq_a59 sdq_a59 sdq_a59 sdq_a59 sdq_a59 r35 rsv rsv rsv rsv rsv rsv t1 dmi_txp1 dmi_txp1 dmi_txp1 dmi_txp1 dmi_txp1 dmi_txp1 t2 vss vss vss vss vss vss t3 dmi_txn0 dmi_txn0 dmi_txn0 dmi_txn0 dmi_txn0 dmi_txn0 t4 vss vss vss vss vss vss t5 vss vss vss vss vss vss t6 vss vss vss vss vss vss t7 vss vss vss vss vss vss t8 dmi_rxn1 dmi_rxn1 dmi_rxn1 dmi_rxn1 dmi_rxn1 dmi_rxn1 ballout and package information r datasheet 347 ball # intel ? 82915GL gmch 6 intel ? 82915pl mch 5 intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 intel ? 82910gl gmch 4 t9 dmi_rxp1 dmi_rxp1 dmi_rxp1 dmi_rxp1 dmi_rxp1 dmi_rxp1 t10 vss vss vss vss vss vss t11 vss vss vss vss vss vss t12 nc nc nc nc nc nc t13 vcc vcc vcc vcc vcc vcc t14 vcc vcc vcc vcc vcc vcc t15 vcc vcc vcc vcc vcc vcc t16 vcc vcc vcc vcc vcc vcc t17 vcc vcc vcc vcc vcc vcc t18 vss vss vss vss vss vss t19 vcc vcc vcc vcc vcc vcc t20 vcc vcc vcc vcc vcc vcc t21 vcc vcc vcc vcc vcc vcc t22 vss vss vss vss vss vss t23 vcc vcc vcc vcc vcc vcc t24 vcc vcc vcc vcc vcc vcc t25 vss vss vss vss vss vss t26 ha30# ha30# ha30# ha30# ha30# ha30# t27 ha27# ha27# ha27# ha27# ha27# ha27# t28 vss vss vss vss vss vss t29 ha31# ha31# ha31# ha31# ha31# ha31# t30 vss vss vss vss vss vss t31 ha28# ha28# ha28# ha28# ha28# ha28# t32 vss vss vss vss vss vss t33 sdq_a62 sdq_a62 sdq_a62 sdq_a62 sdq_a62 sdq_a62 t34 vss vss vss vss vss vss t35 sdq_a63 sdq_a63 sdq_a63 sdq_a63 sdq_a63 sdq_a63 u1 dmi_txn1 dmi_txn1 dmi_txn1 dmi_txn1 dmi_txn1 dmi_txn1 u2 vss vss vss vss vss vss u3 dmi_txp2 dmi_txp2 dmi_txp2 dmi_txp2 dmi_txp2 dmi_txp2 u4 vss vss vss vss vss vss u5 dmi_rxp0 dmi_rxp0 dmi_rxp0 dmi_rxp0 dmi_rxp0 dmi_rxp0 u6 dmi_rxn0 dmi_rxn0 dmi_rxn0 dmi_rxn0 dmi_rxn0 dmi_rxn0 u7 vss vss vss vss vss vss u8 vss vss vss vss vss vss u9 vss vss vss vss vss vss u10 dmi_rxn3 dmi_rxn3 dmi_rxn3 dmi_rxn3 dmi_rxn3 dmi_rxn3 u11 vss vss vss vss vss vss u12 nc nc nc nc nc nc u13 vcc vcc vcc vcc vcc vcc ballout and package information r 348 datasheet ball # intel ? 82915GL gmch 6 intel ? 82915pl mch 5 intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 intel ? 82910gl gmch 4 u14 vcc vcc vcc vcc vcc vcc u15 vss vss vss vss vss vss u16 vcc vcc vcc vcc vcc vcc u17 vss vss vss vss vss vss u18 vcc vcc vcc vcc vcc vcc u19 vss vss vss vss vss vss u20 vcc vcc vcc vcc vcc vcc u21 vss vss vss vss vss vss u22 vcc vcc vcc vcc vcc vcc u23 vss vss vss vss vss vss u24 vcc vcc vcc vcc vcc vcc u25 vss vss vss vss vss vss u26 sdq_b58 sdq_b58 sdq_b58 sdq_b58 sdq_b58 sdq_b58 u27 vss vss vss vss vss vss u28 ha29# ha29# ha29# ha29# ha29# ha29# u29 vss vss vss vss vss vss u30 rsv rsv rsv rsv rsv rsv u31 vss vss vss vss vss vss u32 vss vss vss vss vss vss u33 sdm_a7 sdm_a7 sdm_a7 sdm_a7 sdm_a7 sdm_a7 u34 sdqs_a7 sdqs_a7 sdqs_a7 sdqs_a7 sdqs_a7 sdqs_a7 u35 rsv rsv rsv rsv rsv rsv v1 vss vss vss vss vss vss v2 vss vss vss vss vss vss v3 dmi_txn2 dmi_txn2 dmi_txn2 dmi_txn2 dmi_txn2 dmi_txn2 v4 vss vss vss vss vss vss v5 dmi_txp3 dmi_txp3 dmi_txp3 dmi_txp3 dmi_txp3 dmi_txp3 v6 vss vss vss vss vss vss v7 dmi_rxp2 dmi_rxp2 dmi_rxp2 dmi_rxp2 dmi_rxp2 dmi_rxp2 v8 dmi_rxn2 dmi_rxn2 dmi_rxn2 dmi_rxn2 dmi_rxn2 dmi_rxn2 v9 vss vss vss vss vss vss v10 dmi_rxp3 dmi_rxp3 dmi_rxp3 dmi_rxp3 dmi_rxp3 dmi_rxp3 v11 vss vss vss vss vss vss v12 nc nc nc nc nc nc v13 vcc vcc vcc vcc vcc vcc v14 vcc vcc vcc vcc vcc vcc v15 vcc vcc vcc vcc vcc vcc v16 vss vss vss vss vss vss v17 vcc vcc vcc vcc vcc vcc v18 vss vss vss vss vss vss ballout and package information r datasheet 349 ball # intel ? 82915GL gmch 6 intel ? 82915pl mch 5 intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 intel ? 82910gl gmch 4 v19 vcc vcc vcc vcc vcc vcc v20 vss vss vss vss vss vss v21 vcc vcc vcc vcc vcc vcc v22 vss vss vss vss vss vss v23 vcc vcc vcc vcc vcc vcc v24 vcc vcc vcc vcc vcc vcc v25 vss vss vss vss vss vss v26 vss vss vss vss vss vss v27 vss vss vss vss vss vss v28 sdq_b63 sdq_b63 sdq_b63 sdq_b63 sdq_b63 sdq_b63 v29 sdq_b59 sdq_b59 sdq_b59 sdq_b59 sdq_b59 sdq_b59 v30 rsv rsv rsv rsv rsv rsv v31 rsv rsv rsv rsv rsv rsv v32 rsv rsv rsv rsv rsv rsv v33 sdq_a57 sdq_a57 sdq_a57 sdq_a57 sdq_a57 sdq_a57 v34 sdq_a56 sdq_a56 sdq_a56 sdq_a56 sdq_a56 sdq_a56 v35 vss vss vss vss vss vss w1 vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp w2 vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp w3 vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp w4 vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp w5 dmi_txn3 dmi_txn3 dmi_txn3 dmi_txn3 dmi_txn3 dmi_txn3 w6 vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp w7 vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp w8 vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp w9 vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp w10 exp_compi exp_compi exp_compi exp_compi exp_compi exp_compi w11 vss vss vss vss vss vss w12 nc nc nc nc nc nc w13 vcc vcc vcc vcc vcc vcc w14 vcc vcc vcc vcc vcc vcc w15 vss vss vss vss vss vss w16 vcc vcc vcc vcc vcc vcc w17 vss vss vss vss vss vss w18 vcc vcc vcc vcc vcc vcc w19 vss vss vss vss vss vss w20 vcc vcc vcc vcc vcc vcc w21 vss vss vss vss vss vss w22 vcc vcc vcc vcc vcc vcc w23 vss vss vss vss vss vss ballout and package information r 350 datasheet ball # intel ? 82915GL gmch 6 intel ? 82915pl mch 5 intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 intel ? 82910gl gmch 4 w24 vcc vcc vcc vcc vcc vcc w25 vss vss vss vss vss vss w26 sdq_b62 sdq_b62 sdq_b62 sdq_b62 sdq_b62 sdq_b62 w27 sdqs_b7 sdqs_b7 sdqs_b7 sdqs_b7 sdqs_b7 sdqs_b7 w28 vss vss vss vss vss vss w29 sdq_b57 sdq_b57 sdq_b57 sdq_b57 sdq_b57 sdq_b57 w30 vss vss vss vss vss vss w31 sdm_b7 sdm_b7 sdm_b7 sdm_b7 sdm_b7 sdm_b7 w32 vss vss vss vss vss vss w33 sdq_a61 sdq_a61 sdq_a61 sdq_a61 sdq_a61 sdq_a61 w34 sdq_a51 sdq_a51 sdq_a51 sdq_a51 sdq_a51 sdq_a51 w35 sdq_a60 sdq_a60 sdq_a60 sdq_a60 sdq_a60 sdq_a60 y1 vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp y2 vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp y3 vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp y4 vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp y5 vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp y6 vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp y7 vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp y8 vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp y9 vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp y10 exp_comp o exp_compo exp_compo exp_compo exp_compo exp_compo y11 vss vss vss vss vss vss y12 nc nc nc nc nc nc y13 vcc vcc vcc vcc vcc vcc y14 vcc vcc vcc vcc vcc vcc y15 vcc vcc vcc vcc vcc vcc y16 vcc vcc vcc vcc vcc vcc y17 vcc vcc vcc vcc vcc vcc y18 vss vss vss vss vss vss y19 vcc vcc vcc vcc vcc vcc y20 vcc vcc vcc vcc vcc vcc y21 vcc vcc vcc vcc vcc vcc y22 vss vss vss vss vss vss y23 vcc vcc vcc vcc vcc vcc y24 vcc vcc vcc vcc vcc vcc y25 vss vss vss vss vss vss y26 sdq_b60 sdq_b60 sdq_b60 sdq_b60 sdq_b60 sdq_b60 y27 vss vss vss vss vss vss ballout and package information r datasheet 351 ball # intel ? 82915GL gmch 6 intel ? 82915pl mch 5 intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 intel ? 82910gl gmch 4 y28 rsv rsv rsv rsv rsv rsv y29 vss vss vss vss vss vss y30 rsv rsv rsv rsv rsv rsv y31 vss vss vss vss vss vss y32 vss vss vss vss vss vss y33 sdq_a50 sdq_a50 sdq_a50 sdq_a50 sdq_a50 sdq_a50 y34 vss vss vss vss vss vss y35 sdq_a55 sdq_a55 sdq_a55 sdq_a55 sdq_a55 sdq_a55 aa1 vss vss vss vss vss vss aa2 vss vss vss vss vss vss aa3 vss vss vss vss vss vss aa4 vss vss vss vss vss vss aa5 vss vss vss vss vss vss aa6 vss vss vss vss vss vss aa7 vss vss vss vss vss vss aa8 vss vss vss vss vss vss aa9 vss vss vss vss vss vss aa10 vss vss vss vss vss vss aa11 vss vss vss vss vss vss aa12 nc nc nc nc nc nc aa13 vcc vcc vcc vcc vcc vcc aa14 vcc vcc vcc vcc vcc vcc aa15 vss vss vss vss vss vss aa16 vcc vcc vcc vcc vcc vcc aa17 vss vss vss vss vss vss aa18 vcc vcc vcc vcc vcc vcc aa19 vss vss vss vss vss vss aa20 vcc vcc vcc vcc vcc vcc aa21 vcc vcc vcc vcc vcc vcc aa22 vcc vcc vcc vcc vcc vcc aa23 vcc vcc vcc vcc vcc vcc aa24 vcc vcc vcc vcc vcc vcc aa25 vss vss vss vss vss vss aa26 vss vss vss vss vss vss aa27 vss vss vss vss vss vss aa28 sdq_b61 sdq_b61 sdq_b61 sdq_b61 sdq_b61 sdq_b61 aa29 sdq_b56 sdq_b56 sdq_b56 sdq_b56 sdq_b56 sdq_b56 aa30 rsv rsv rsv rsv rsv rsv aa31 rsv rsv rsv rsv rsv rsv aa32 sdq_a54 sdq_a54 sdq_a54 sdq_a54 sdq_a54 sdq_a54 ballout and package information r 352 datasheet ball # intel ? 82915GL gmch 6 intel ? 82915pl mch 5 intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 intel ? 82910gl gmch 4 aa33 sdm_a6 sdm_a6 sdm_a6 sdm_a6 sdm_a6 sdm_a6 aa34 sdqs_a6 sdqs_a6 sdqs_a6 sdqs_a6 sdqs_a6 sdqs_a6 aa35 rsv rsv rsv rsv rsv rsv ab1 vcc vcc vcc vcc vcc vcc ab2 vcc vcc vcc vcc vcc vcc ab3 vcc vcc vcc vcc vcc vcc ab4 vcc vcc vcc vcc vcc vcc ab5 vcc vcc vcc vcc vcc vcc ab6 vcc vcc vcc vcc vcc vcc ab7 vcc vcc vcc vcc vcc vcc ab8 vcc vcc vcc vcc vcc vcc ab9 vcc vcc vcc vcc vcc vcc ab10 vcc vcc vcc vcc vcc vcc ab11 vcc vcc vcc vcc vcc vcc ab12 nc nc nc nc nc nc ab13 vcc vcc vcc vcc vcc vcc ab14 vcc vcc vcc vcc vcc vcc ab15 vcc vcc vcc vcc vcc vcc ab16 vcc vcc vcc vcc vcc vcc ab17 vcc vcc vcc vcc vcc vcc ab18 vcc vcc vcc vcc vcc vcc ab19 vcc vcc vcc vcc vcc vcc ab20 vcc vcc vcc vcc vcc vcc ab21 vcc vcc vcc vcc vcc vcc ab22 vcc vcc vcc vcc vcc vcc ab23 vcc vcc vcc vcc vcc vcc ab24 vcc vcc vcc vcc vcc vcc ab25 vss vss vss vss vss vss ab26 sdq_b51 sdq_b51 sdq_b51 sdq_b51 sdq_b51 sdq_b51 ab27 sdq_b50 sdq_b50 sdq_b50 sdq_b50 sdq_b50 sdq_b50 ab28 vss vss vss vss vss vss ab29 rsv rsv rsv rsv rsv rsv ab30 vss vss vss vss vss vss ab31 sdqs_b6 sdqs_b6 sdqs_b6 sdqs_b6 sdqs_b6 sdqs_b6 ab32 vss vss vss vss vss vss ab33 sma_a13 sma_a13 sma_a13 sma_a13 sma_a13 sma_a13 ab34 sclk_a2 sclk_a2 sclk_a2 sclk_a2 sclk_a2 sclk_a2 ab35 vss vss vss vss vss vss ac1 vcc vcc vcc vcc vcc vcc ac2 vcc vcc vcc vcc vcc vcc ballout and package information r datasheet 353 ball # intel ? 82915GL gmch 6 intel ? 82915pl mch 5 intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 intel ? 82910gl gmch 4 ac3 vcc vcc vcc vcc vcc vcc ac4 vcc vcc vcc vcc vcc vcc ac5 vcc vcc vcc vcc vcc vcc ac6 vcc vcc vcc vcc vcc vcc ac7 vcc vcc vcc vcc vcc vcc ac8 vcc vcc vcc vcc vcc vcc ac9 vcc vcc vcc vcc vcc vcc ac10 vcc vcc vcc vcc vcc vcc ac11 vcc vcc vcc vcc vcc vcc ac12 rsv rsv rsv rsv rsv rsv ac13 rsv rsv rsv rsv rsv rsv ac14 rsv rsv rsv rsv rsv rsv ac15 rsv rsv rsv rsv rsv rsv ac16 rsv rsv rsv rsv rsv rsv ac17 rsv rsv rsv rsv rsv rsv ac18 rsv rsv rsv rsv rsv rsv ac19 rsv rsv rsv rsv rsv rsv ac20 rsv rsv rsv rsv rsv rsv ac21 rsv rsv rsv rsv rsv rsv ac22 rsv rsv rsv rsv rsv rsv ac23 nc nc nc nc nc nc ac24 nc nc nc nc nc nc ac25 vss vss vss vss vss vss ac26 sdq_b55 sdq_b55 sdq_b55 sdq_b55 sdq_b55 sdq_b55 ac27 vss vss vss vss vss vss ac28 sdq_b54 sdq_b54 sdq_b54 sdq_b54 sdq_b54 sdq_b54 ac29 vss vss vss vss vss vss ac30 rsv rsv rsv rsv rsv rsv ac31 vss vss vss vss vss vss ac32 vss vss vss vss vss vss ac33 sclk_a2# sclk_a2# sclk_a2# sclk_a2# sclk_a2# sclk_a2# ac34 sclk_a5# rsv sclk_a5# sclk_a5# sclk_a5# rsv ac35 sclk_a5 rsv sclk_a5 sclk_a5 sclk_a5 rsv ad1 vcc vcc vcc vcc vcc vcc ad2 vcc vcc vcc vcc vcc vcc ad3 vcc vcc vcc vcc vcc vcc ad4 vcc vcc vcc vcc vcc vcc ad5 vcc vcc vcc vcc vcc vcc ad6 vcc vcc vcc vcc vcc vcc ad7 vcc vcc vcc vcc vcc vcc ballout and package information r 354 datasheet ball # intel ? 82915GL gmch 6 intel ? 82915pl mch 5 intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 intel ? 82910gl gmch 4 ad8 vcc vcc vcc vcc vcc vcc ad9 vcc vcc vcc vcc vcc vcc ad10 vcc vcc vcc vcc vcc vcc ad11 vss vss vss vss vss vss ad12 sdq_b20 sdq_b20 sdq_b20 sdq_b20 sdq_b20 sdq_b20 ad13 vss vss vss vss vss vss ad14 sdq_b19 sdq_b19 sdq_b19 sdq_b19 sdq_b19 sdq_b19 ad15 sdq_b23 sdq_b23 sdq_b23 sdq_b23 sdq_b23 sdq_b23 ad16 vss vss vss vss vss vss ad17 sdq_a26 sdq_a26 sdq_a26 sdq_a26 sdq_a26 sdq_a26 ad18 sdq_b24 sdq_b24 sdq_b24 sdq_b24 sdq_b24 sdq_b24 ad19 vss vss vss vss vss vss ad20 sdqs_b3 sdqs_b3 sdqs_b3 sdqs_b3 sdqs_b3 sdqs_b3 ad21 sdq_b31 sdq_b31 sdq_b31 sdq_b31 sdq_b31 sdq_b31 ad22 vss vss vss vss vss vss ad23 sdq_b36 sdq_b36 sdq_b36 sdq_b36 sdq_b36 sdq_b36 ad24 sdm_b6 sdm_b6 sdm_b6 sdm_b6 sdm_b6 sdm_b6 ad25 vss vss vss vss vss vss ad26 vss vss vss vss vss vss ad27 vss vss vss vss vss vss ad28 sclk_b5# rsv sclk_b5# sclk_b5# sclk_b5# rsv ad29 sclk_b5 rsv sclk_b5 sclk_b5 sclk_b5 rsv ad30 nc nc nc nc nc nc ad31 sdq_a52 sdq_a52 sdq_a52 sdq_a52 sdq_a52 sdq_a52 ad32 sma_b13 sma_b13 sma_b13 sma_b13 sma_b13 sma_b13 ad33 ? ? ? ? ? ? ad34 vss vss vss vss vss vss ad35 sdq_a53 sdq_a53 sdq_a53 sdq_a53 sdq_a53 sdq_a53 ae1 sdq_a5 sdq_a5 sdq_a5 sdq_a5 sdq_a5 sdq_a5 ae2 sdq_a4 sdq_a4 sdq_a4 sdq_a4 sdq_a4 sdq_a4 ae3 sdq_a0 sdq_a0 sdq_a0 sdq_a0 sdq_a0 sdq_a0 ae4 vss vss vss vss vss vss ae5 rsv rsv rsv rsv rsv rsv ae6 vss vss vss vss vss vss ae7 svref0 svref0 svref0 svref0 svref0 svref0 ae8 svref1 svref1 svref1 svref1 svref1 svref1 ae9 vss vss vss vss vss vss ae10 sm_slewo ut1 sm_slewou t1 sm_slewout1 sm_slewout1 sm_slewout 1 sm_slewout1 ae11 sdq_b11 sdq_b11 sdq_b11 sdq_b11 sdq_b11 sdq_b11 ballout and package information r datasheet 355 ball # intel ? 82915GL gmch 6 intel ? 82915pl mch 5 intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 intel ? 82910gl gmch 4 ae12 vss vss vss vss vss vss ae13 sdq_b16 sdq_b16 sdq_b16 sdq_b16 sdq_b16 sdq_b16 ae14 vss vss vss vss vss vss ae15 vss vss vss vss vss vss ae16 rsv_tp0 rsv_tp0 rsv_tp0 rsv_tp0 rsv_tp0 rsv_tp0 ae17 vss vss vss vss vss vss ae18 vss vss vss vss vss vss ae19 sdq_a30 sdq_a30 sdq_a30 sdq_a30 sdq_a30 sdq_a30 ae20 vss vss vss vss vss vss ae21 vss vss vss vss vss vss ae22 sdq_b26 sdq_b26 sdq_b26 sdq_b26 sdq_b26 sdq_b26 ae23 vss vss vss vss vss vss ae24 vss vss vss vss vss vss ae25 sclk_b2# sclk_b2# sclk_b2# sclk_b2# sclk_b2# sclk_b2# ae26 sclk_b2 sclk_b2 sclk_b2 sclk_b2 sclk_b2 sclk_b2 ae27 sdq_b53 sdq_b53 sdq_b53 sdq_b53 sdq_b53 sdq_b53 ae28 vss vss vss vss vss vss ae29 sdq_b52 sdq_b52 sdq_b52 sdq_b52 sdq_b52 sdq_b52 ae30 vss vss vss vss vss vss ae31 sdq_b48 sdq_b48 sdq_b48 sdq_b48 sdq_b48 sdq_b48 ae32 vss vss vss vss vss vss ae33 sdq_a47 sdq_a47 sdq_a47 sdq_a47 sdq_a47 sdq_a47 ae34 sdq_a49 sdq_a49 sdq_a49 sdq_a49 sdq_a49 sdq_a49 ae35 sdq_a48 sdq_a48 sdq_a48 sdq_a48 sdq_a48 sdq_a48 af1 vss vss vss vss vss vss af2 sdm_a0 sdm_a0 sdm_a0 sdm_a0 sdm_a0 sdm_a0 af3 sdq_a1 sdq_a1 sdq_a1 sdq_a1 sdq_a1 sdq_a1 af4 vss vss vss vss vss vss af5 rsv rsv rsv rsv rsv rsv af6 vss vss vss vss vss vss af7 rstin# rstin# rstin# rstin# rstin# rstin# af8 vss vss vss vss vss vss af9 sm_slewin 1 sm_slewin1 sm_slewin1 sm_slewin1 sm_slewin1 sm_slewin1 af10 vss vss vss vss vss vss af11 sdq_b10 sdq_b10 sdq_b10 sdq_b10 sdq_b10 sdq_b10 af12 vss vss vss vss vss vss af13 sdq_b17 sdq_b17 sdq_b17 sdq_b17 sdq_b17 sdq_b17 af14 sdq_b22 sdq_b22 sdq_b22 sdq_b22 sdq_b22 sdq_b22 af15 vss vss vss vss vss vss ballout and package information r 356 datasheet ball # intel ? 82915GL gmch 6 intel ? 82915pl mch 5 intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 intel ? 82910gl gmch 4 af16 sdq_a28 sdq_a28 sdq_a28 sdq_a28 sdq_a28 sdq_a28 af17 sdqs_a3 sdqs_a3 sdqs_a3 sdqs_a3 sdqs_a3 sdqs_a3 af18 vss vss vss vss vss vss af19 sdq_a27 sdq_a27 sdq_a27 sdq_a27 sdq_a27 sdq_a27 af20 rsv rsv rsv rsv rsv rsv af21 vss vss vss vss vss vss af22 sdq_b30 sdq_b30 sdq_b30 sdq_b30 sdq_b30 sdq_b30 af23 sdq_b32 sdq_b32 sdq_b32 sdq_b32 sdq_b32 sdq_b32 af24 sdq_b37 sdq_b37 sdq_b37 sdq_b37 sdq_b37 sdq_b37 af25 sdq_b33 sdq_b33 sdq_b33 sdq_b33 sdq_b33 sdq_b33 af26 vss vss vss vss vss vss af27 sdq_b49 sdq_b49 sdq_b49 sdq_b49 sdq_b49 sdq_b49 af28 sdq_b47 sdq_b47 sdq_b47 sdq_b47 sdq_b47 sdq_b47 af29 vss vss vss vss vss vss af30 vss vss vss vss vss vss af31 vss vss vss vss vss vss af32 vss vss vss vss vss vss af33 sdq_a46 sdq_a46 sdq_a46 sdq_a46 sdq_a46 sdq_a46 af34 sdq_a43 sdq_a43 sdq_a43 sdq_a43 sdq_a43 sdq_a43 af35 vss vss vss vss vss vss ag1 sdqs_a0 sdqs_a0 sdqs_a0 sdqs_a0 sdqs_a0 sdqs_a0 ag2 rsv rsv rsv rsv rsv rsv ag3 sdq_a6 sdq_a6 sdq_a6 sdq_a6 sdq_a6 sdq_a6 ag4 srcomp0 srcomp0 srcomp0 srcomp0 srcomp0 srcomp0 ag5 vss vss vss vss vss vss ag6 nc nc nc nc nc nc ag7 pwrok pwrok pwrok pwrok pwrok pwrok ag8 srcomp1 srcomp1 srcomp1 srcomp1 srcomp1 srcomp1 ag9 sdq_b4 sdq_b4 sdq_b4 sdq_b4 sdq_b4 sdq_b4 ag10 sdq_b14 sdq_b14 sdq_b14 sdq_b14 sdq_b14 sdq_b14 ag11 sdq_b15 sdq_b15 sdq_b15 sdq_b15 sdq_b15 sdq_b15 ag12 vss vss vss vss vss vss ag13 vss vss vss vss vss vss ag14 sdq_b18 sdq_b18 sdq_b18 sdq_b18 sdq_b18 sdq_b18 ag15 vss vss vss vss vss vss ag16 vss vss vss vss vss vss ag17 rsv rsv rsv rsv rsv rsv ag18 vss vss vss vss vss vss ag19 vss vss vss vss vss vss ag20 sdm_b3 sdm_b3 sdm_b3 sdm_b3 sdm_b3 sdm_b3 ballout and package information r datasheet 357 ball # intel ? 82915GL gmch 6 intel ? 82915pl mch 5 intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 intel ? 82910gl gmch 4 ag21 vss vss vss vss vss vss ag22 vss vss vss vss vss vss ag23 sclk_b0# sclk_b0# sclk_b0# sclk_b0# sclk_b0# sclk_b0# ag24 sdm_b4 sdm_b4 sdm_b4 sdm_b4 sdm_b4 sdm_b4 ag25 vss vss vss vss vss vss ag26 rsv rsv rsv rsv rsv rsv ag27 sdq_b46 sdq_b46 sdq_b46 sdq_b46 sdq_b46 sdq_b46 ag28 vss vss vss vss vss vss ag29 vss vss vss vss vss vss ag30 sdq_b42 sdq_b42 sdq_b42 sdq_b42 sdq_b42 sdq_b42 ag31 sdq_b43 sdq_b43 sdq_b43 sdq_b43 sdq_b43 sdq_b43 ag32 sdq_a42 sdq_a42 sdq_a42 sdq_a42 sdq_a42 sdq_a42 ag33 rsv rsv rsv rsv rsv rsv ag34 sdm_a5 sdm_a5 sdm_a5 sdm_a5 sdm_a5 sdm_a5 ag35 sdqs_a5 sdqs_a5 sdqs_a5 sdqs_a5 sdqs_a5 sdqs_a5 ah1 vss vss vss vss vss vss ah2 sdq_a2 sdq_a2 sdq_a2 sdq_a2 sdq_a2 sdq_a2 ah3 sdq_a7 sdq_a7 sdq_a7 sdq_a7 sdq_a7 sdq_a7 ah4 sdq_b5 sdq_b5 sdq_b5 sdq_b5 sdq_b5 sdq_b5 ah5 vss vss vss vss vss vss ah6 vss vss vss vss vss vss ah7 sdq_b0 sdq_b0 sdq_b0 sdq_b0 sdq_b0 sdq_b0 ah8 vss vss vss vss vss vss ah9 sdm_b1 sdm_b1 sdm_b1 sdm_b1 sdm_b1 sdm_b1 ah10 rsv rsv rsv rsv rsv rsv ah11 vss vss vss vss vss vss ah12 sdq_b21 sdq_b21 sdq_b21 sdq_b21 sdq_b21 sdq_b21 ah13 sdm_b2 sdm_b2 sdm_b2 sdm_b2 sdm_b2 sdm_b2 ah14 vss vss vss vss vss vss ah15 rsv_tp1 rsv_tp1 rsv_tp1 rsv_tp1 rsv_tp1 rsv_tp1 ah16 sdm_a3 sdm_a3 sdm_a3 sdm_a3 sdm_a3 sdm_a3 ah17 vss vss vss vss vss vss ah18 sdq_a31 sdq_a31 sdq_a31 sdq_a31 sdq_a31 sdq_a31 ah19 sdq_b29 sdq_b29 sdq_b29 sdq_b29 sdq_b29 sdq_b29 ah20 vss vss vss vss vss vss ah21 sdq_b27 sdq_b27 sdq_b27 sdq_b27 sdq_b27 sdq_b27 ah22 sclk_b0 sclk_b0 sclk_b0 sclk_b0 sclk_b0 sclk_b0 ah23 vss vss vss vss vss vss ah24 nc nc nc nc nc nc ah25 sdqs_b4 sdqs_b4 sdqs_b4 sdqs_b4 sdqs_b4 sdqs_b4 ballout and package information r 358 datasheet ball # intel ? 82915GL gmch 6 intel ? 82915pl mch 5 intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 intel ? 82910gl gmch 4 ah26 vss vss vss vss vss vss ah27 sdq_a32 sdq_a32 sdq_a32 sdq_a32 sdq_a32 sdq_a32 ah28 sdqs_b5 sdqs_b5 sdqs_b5 sdqs_b5 sdqs_b5 sdqs_b5 ah29 vss vss vss vss vss vss ah30 rsv rsv rsv rsv rsv rsv ah31 sdm_b5 sdm_b5 sdm_b5 sdm_b5 sdm_b5 sdm_b5 ah32 vss vss vss vss vss vss ah33 sdq_a45 sdq_a45 sdq_a45 sdq_a45 sdq_a45 sdq_a45 ah34 vss vss vss vss vss vss ah35 sdq_a41 sdq_a41 sdq_a41 sdq_a41 sdq_a41 sdq_a41 aj1 sdq_a8 sdq_a8 sdq_a8 sdq_a8 sdq_a8 sdq_a8 aj2 sdq_a3 sdq_a3 sdq_a3 sdq_a3 sdq_a3 sdq_a3 aj3 sdq_a12 sdq_a12 sdq_a12 sdq_a12 sdq_a12 sdq_a12 aj4 vss vss vss vss vss vss aj5 sdm_b0 sdm_b0 sdm_b0 sdm_b0 sdm_b0 sdm_b0 aj6 sdq_b1 sdq_b1 sdq_b1 sdq_b1 sdq_b1 sdq_b1 aj7 sdq_b8 sdq_b8 sdq_b8 sdq_b8 sdq_b8 sdq_b8 aj8 sdq_b12 sdq_b12 sdq_b12 sdq_b12 sdq_b12 sdq_b12 aj9 vss vss vss vss vss vss aj10 vss vss vss vss vss vss aj11 sclk_b1# sclk_b1# sclk_b1# sclk_b1# sclk_b1# sclk_b1# aj12 sm_slewin 0 sm_slewin0 sm_slewin0 sm_slewin0 sm_slewin0 sm_slewin0 aj13 vss vss vss vss vss vss aj14 nc nc nc nc nc nc aj15 vss vss vss vss vss vss aj16 vss vss vss vss vss vss aj17 sdq_a29 sdq_a29 sdq_a29 sdq_a29 sdq_a29 sdq_a29 aj18 rsv rsv rsv rsv rsv rsv aj19 vss vss vss vss vss vss aj20 rsv rsv rsv rsv rsv rsv aj21 rsv rsv rsv rsv rsv rsv aj22 vss vss vss vss vss vss aj23 rsv rsv rsv rsv rsv rsv aj24 rsv rsv rsv rsv rsv rsv aj25 sdq_b38 sdq_b38 sdq_b38 sdq_b38 sdq_b38 sdq_b38 aj26 sdq_b35 sdq_b35 sdq_b35 sdq_b35 sdq_b35 sdq_b35 aj27 vss vss vss vss vss vss aj28 sdq_a37 sdq_a37 sdq_a37 sdq_a37 sdq_a37 sdq_a37 aj29 sdq_b40 sdq_b40 sdq_b40 sdq_b40 sdq_b40 sdq_b40 ballout and package information r datasheet 359 ball # intel ? 82915GL gmch 6 intel ? 82915pl mch 5 intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 intel ? 82910gl gmch 4 aj30 vss vss vss vss vss vss aj31 sdq_b41 sdq_b41 sdq_b41 sdq_b41 sdq_b41 sdq_b41 aj32 vss vss vss vss vss vss aj33 sdq_a44 sdq_a44 sdq_a44 sdq_a44 sdq_a44 sdq_a44 aj34 sdq_a40 sdq_a40 sdq_a40 sdq_a40 sdq_a40 sdq_a40 aj35 vss vss vss vss vss vss ak1 vss vss vss vss vss vss ak2 sdq_a9 sdq_a9 sdq_a9 sdq_a9 sdq_a9 sdq_a9 ak3 sdq_a13 sdq_a13 sdq_a13 sdq_a13 sdq_a13 sdq_a13 ak4 vss vss vss vss vss vss ak5 sdqs_b0 sdqs_b0 sdqs_b0 sdqs_b0 sdqs_b0 sdqs_b0 ak6 vss vss vss vss vss vss ak7 vss vss vss vss vss vss ak8 vss vss vss vss vss vss ak9 sclk_b4 sclk_b4 sclk_b4 sclk_b4 sclk_b4 rsv ak10 sdqs_b1 sdqs_b1 sdqs_b1 sdqs_b1 sdqs_b1 sdqs_b1 ak11 vss vss vss vss vss vss ak12 sm_slewo ut0 sm_slewou t0 sm_slewout0 sm_slewout0 sm_slewout 0 sm_slewout0 ak13 sdqs_b2 sdqs_b2 sdqs_b2 sdqs_b2 sdqs_b2 sdqs_b2 ak14 vss vss vss vss vss vss ak15 rsv_tp3 rsv_tp3 rsv_tp3 rsv_tp3 rsv_tp3 rsv_tp3 ak16 sdq_a24 sdq_a24 sdq_a24 sdq_a24 sdq_a24 sdq_a24 ak17 vss vss vss vss vss vss ak18 rsv rsv rsv rsv rsv rsv ak19 sdq_b25 sdq_b25 sdq_b25 sdq_b25 sdq_b25 sdq_b25 ak20 vss vss vss vss vss vss ak21 rsv rsv rsv rsv rsv rsv ak22 sclk_b3# rsv sclk_b3# sclk_b3# sclk_b3# rsv ak23 vss rsv vss vss vss vss ak24 rsv rsv rsv rsv rsv rsv ak25 vss vss vss vss vss vss ak26 vss vss vss vss vss vss ak27 sdq_a33 sdq_a33 sdq_a33 sdq_a33 sdq_a33 sdq_a33 ak28 vss vss vss vss vss vss ak29 sdm_a4 sdm_a4 sdm_a4 sdm_a4 sdm_a4 sdm_a4 ak30 vss vss vss vss vss vss ak31 sdq_a35 sdq_a35 sdq_a35 sdq_a35 sdq_a35 sdq_a35 ak32 sdq_b45 sdq_b45 sdq_b45 sdq_b45 sdq_b45 sdq_b45 ak33 sdq_b44 sdq_b44 sdq_b44 sdq_b44 sdq_b44 sdq_b44 ballout and package information r 360 datasheet ball # intel ? 82915GL gmch 6 intel ? 82915pl mch 5 intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 intel ? 82910gl gmch 4 ak34 scs_a2# scs_a2# scs_a2# scs_a2# scs_a2# rsv ak35 vccsm vccsm vccsm vccsm vccsm vccsm al1 sdm_a1 sdm_a1 sdm_a1 sdm_a1 sdm_a1 sdm_a1 al2 rsv rsv rsv rsv rsv rsv al3 sdqs_a1 sdqs_a1 sdqs_a1 sdqs_a1 sdqs_a1 sdqs_a1 al4 rsv rsv rsv rsv rsv rsv al5 sdq_b2 sdq_b2 sdq_b2 sdq_b2 sdq_b2 sdq_b2 al6 sdq_b7 sdq_b7 sdq_b7 sdq_b7 sdq_b7 sdq_b7 al7 sdq_b9 sdq_b9 sdq_b9 sdq_b9 sdq_b9 sdq_b9 al8 sdq_b13 sdq_b13 sdq_b13 sdq_b13 sdq_b13 sdq_b13 al9 sclk_b4# rsv sclk_b4# sclk_b4# sclk_b4# rsv al10 vss vss vss vss vss vss al11 sclk_b1 sclk_b1 sclk_b1 sclk_b1 sclk_b1 sclk_b1 al12 scke_a0 scke_a0 scke_a0 scke_a0 scke_a0 scke_a0 al13 vss vss vss vss vss vss al14 rsv rsv rsv rsv rsv rsv al15 sma_b7 sma_b7 sma_b7 sma_b7 sma_b7 sma_b7 al16 vss vss vss vss vss vss al17 sdq_a25 sdq_a25 sdq_a25 sdq_a25 sdq_a25 sdq_a25 al18 sdq_b28 sdq_b28 sdq_b28 sdq_b28 sdq_b28 sdq_b28 al19 vss vss vss vss vss vss al20 rsv rsv rsv rsv rsv rsv al21 rsv rsv rsv rsv rsv rsv al22 vss vss vss vss vss vss al23 sclk_b3 rsv sclk_b3 sclk_b3 sclk_b3 rsv al24 rsv rsv rsv rsv rsv rsv al25 sdq_b34 sdq_b34 sdq_b34 sdq_b34 sdq_b34 sdq_b34 al26 sdq_b39 sdq_b39 sdq_b39 sdq_b39 sdq_b39 sdq_b39 al27 sdq_a36 sdq_a36 sdq_a36 sdq_a36 sdq_a36 sdq_a36 al28 nc nc nc nc nc nc al29 rsv rsv rsv rsv rsv rsv al30 sdq_a38 sdq_a38 sdq_a38 sdq_a38 sdq_a38 sdq_a38 al31 sdq_a39 sdq_a39 sdq_a39 sdq_a39 sdq_a39 sdq_a39 al32 vss vss vss vss vss vss al33 scs_a3# rsv scs_a3# scs_a3# scs_a3# rsv al34 scas_a# scas_a# scas_a# scas_a# scas_a# scas_a# al35 scs_a1# scs_a1# scs_a1# scs_a1# scs_a1# scs_a1# am1 ? ? ? ? ? ? am2 sclk_a4 rsv sclk_a4 sclk_a4 sclk_a4 rsv am3 sclk_a4# rsv sclk_a4# sclk_a4# sclk_a4# rsv ballout and package information r datasheet 361 ball # intel ? 82915GL gmch 6 intel ? 82915pl mch 5 intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 intel ? 82910gl gmch 4 am4 vss vss vss vss vss vss am5 sdq_b6 sdq_b6 sdq_b6 sdq_b6 sdq_b6 sdq_b6 am6 vss vss vss vss vss vss am7 vss vss vss vss vss vss am8 vss vss vss vss vss vss am9 scke_b1 scke_b1 scke_b1 scke_b1 scke_b1 scke_b1 am10 vccsm vccsm vccsm vccsm vccsm vccsm am11 vccsm vccsm vccsm vccsm vccsm vccsm am12 sma_b12 sma_b12 sma_b12 sma_b12 sma_b12 sma_b12 am13 vccsm vccsm vccsm vccsm vccsm vccsm am14 vccsm vccsm vccsm vccsm vccsm vccsm am15 sma_a9 sma_a9 sma_a9 sma_a9 sma_a9 sma_a9 am16 vccsm vccsm vccsm vccsm vccsm vccsm am17 vccsm vccsm vccsm vccsm vccsm vccsm am18 sma_b0 sma_b0 sma_b0 sma_b0 sma_b0 sma_b0 am19 vccsm vccsm vccsm vccsm vccsm vccsm am20 vccsm vccsm vccsm vccsm vccsm vccsm am21 sma_a4 sma_a4 sma_a4 sma_a4 sma_a4 sma_a4 am22 vccsm vccsm vccsm vccsm vccsm vccsm am23 vccsm vccsm vccsm vccsm vccsm vccsm am24 sclk_a0 sclk_a0 sclk_a0 sclk_a0 sclk_a0 sclk_a0 am25 vccsm vccsm vccsm vccsm vccsm vccsm am26 vccsm vccsm vccsm vccsm vccsm vccsm am27 sbs_b0 sbs_b0 sbs_b0 sbs_b0 sbs_b0 sbs_b0 am28 vccsm vccsm vccsm vccsm vccsm vccsm am29 vss vss vss vss vss vss am30 sdqs_a4 sdqs_a4 sdqs_a4 sdqs_a4 sdqs_a4 sdqs_a4 am31 vss vss vss vss vss vss am32 vccsm vccsm vccsm vccsm vccsm vccsm am33 scs_b3# rsv scs_b3# scs_b3# scs_b3# rsv am34 scs_a0# scs_a0# scs_a0# scs_a0# scs_a0# scs_a0# am35 ? ? ? ? ? ? an1 vss vss vss vss vss vss an2 sclk_a1 sclk_a1 sclk_a1 sclk_a1 sclk_a1 sclk_a1 an3 sclk_a1# sclk_a1# sclk_a1# sclk_a1# sclk_a1# sclk_a1# an4 sdq_a10 sdq_a10 sdq_a10 sdq_a10 sdq_a10 sdq_a10 an5 sdq_a20 sdq_a20 sdq_a20 sdq_a20 sdq_a20 sdq_a20 an6 sdq_b3 sdq_b3 sdq_b3 sdq_b3 sdq_b3 sdq_b3 an7 sdm_a2 sdm_a2 sdm_a2 sdm_a2 sdm_a2 sdm_a2 an8 sdq_a18 sdq_a18 sdq_a18 sdq_a18 sdq_a18 sdq_a18 ballout and package information r 362 datasheet ball # intel ? 82915GL gmch 6 intel ? 82915pl mch 5 intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 intel ? 82910gl gmch 4 an9 sdq_a23 sdq_a23 sdq_a23 sdq_a23 sdq_a23 sdq_a23 an10 scke_b0 scke_b0 scke_b0 scke_b0 scke_b0 scke_b0 an11 scke_a1 scke_a1 scke_a1 scke_a1 scke_a1 scke_a1 an12 ? ? ? ? ? ? an13 sma_b9 sma_b9 sma_b9 sma_b9 sma_b9 sma_b9 an14 rsv_tp2 rsv_tp2 rsv_tp2 rsv_tp2 rsv_tp2 rsv_tp2 an15 sma_b5 sma_b5 sma_b5 sma_b5 sma_b5 sma_b5 an16 sma_a7 sma_a7 sma_a7 sma_a7 sma_a7 sma_a7 an17 sma_b2 sma_b2 sma_b2 sma_b2 sma_b2 sma_b2 an18 sma_a8 sma_a8 sma_a8 sma_a8 sma_a8 sma_a8 an19 nc nc nc nc nc nc an20 sma_b10 sma_b10 sma_b10 sma_b10 sma_b10 sma_b10 an21 sma_a2 sma_a2 sma_a2 sma_a2 sma_a2 sma_a2 an22 sma_a0 sma_a0 sma_a0 sma_a0 sma_a0 sma_a0 an23 sma_a10 sma_a10 sma_a10 sma_a10 sma_a10 sma_a10 an24 ? ? ? ? ? ? an25 sclk_a0# sclk_a0# sclk_a0# sclk_a0# sclk_a0# sclk_a0# an26 sclk_a3# sclk_a3# sclk_a3# sclk_a3# sclk_a3# rsv an27 scas_b# scas_b# scas_b# scas_b# scas_b# scas_b# an28 sbs_a0 sbs_a0 sbs_a0 sbs_a0 sbs_a0 sbs_a0 an29 sras_a# sras_a# sras_a# sras_a# sras_a# sras_a# an30 sdq_a34 sdq_a34 sdq_a34 sdq_a34 sdq_a34 sdq_a34 an31 rsv rsv rsv rsv rsv rsv an32 rsv rsv rsv rsv rsv rsv an33 scs_b2# rsv scs_b2# scs_b2# scs_b2# rsv an34 scs_b1# scs_b1# scs_b1# scs_b1# scs_b1# scs_b1# an35 vccsm vccsm vccsm vccsm vccsm vccsm ap1 nc nc nc nc nc nc ap2 sdq_a14 sdq_a14 sdq_a14 sdq_a14 sdq_a14 sdq_a14 ap3 sdq_a15 sdq_a15 sdq_a15 sdq_a15 sdq_a15 sdq_a15 ap4 sdq_a11 sdq_a11 sdq_a11 sdq_a11 sdq_a11 sdq_a11 ap5 sdq_a16 sdq_a16 sdq_a16 sdq_a16 sdq_a16 sdq_a16 ap6 sdq_a21 sdq_a21 sdq_a21 sdq_a21 sdq_a21 sdq_a21 ap7 sdqs_a2 sdqs_a2 sdqs_a2 sdqs_a2 sdqs_a2 sdqs_a2 ap8 vss vss vss vss vss vss ap9 sdq_a19 sdq_a19 sdq_a19 sdq_a19 sdq_a19 sdq_a19 ap10 scke_b2 rsv scke_b2 scke_b2 scke_b2 rsv ap11 scke_a2 rsv scke_a2 scke_a2 scke_a2 rsv ap12 vccsm vccsm vccsm vccsm vccsm vccsm ap13 sma_a12 sma_a12 sma_a12 sma_a12 sma_a12 sma_a12 ballout and package information r datasheet 363 ball # intel ? 82915GL gmch 6 intel ? 82915pl mch 5 intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 intel ? 82910gl gmch 4 ap14 sma_b8 sma_b8 sma_b8 sma_b8 sma_b8 sma_b8 ap15 sma_a11 sma_a11 sma_a11 sma_a11 sma_a11 sma_a11 ap16 vccsm vccsm vccsm vccsm vccsm vccsm ap17 sma_b6 sma_b6 sma_b6 sma_b6 sma_b6 sma_b6 ap18 sma_b1 sma_b1 sma_b1 sma_b1 sma_b1 sma_b1 ap19 sma_a5 sma_a5 sma_a5 sma_a5 sma_a5 sma_a5 ap20 vccsm vccsm vccsm vccsm vccsm vccsm ap21 sma_a3 sma_a3 sma_a3 sma_a3 sma_a3 sma_a3 ap22 sma_a1 sma_a1 sma_a1 sma_a1 sma_a1 sma_a1 ap23 rsv rsv rsv rsv rsv rsv ap24 vccsm vccsm vccsm vccsm vccsm vccsm ap25 sclk_a3 rsv sclk_a3 sclk_a3 sclk_a3 rsv ap26 sbs_a1 sbs_a1 sbs_a1 sbs_a1 sbs_a1 sbs_a1 ap27 sras_b# sras_b# sras_b# sras_b# sras_b# sras_b# ap28 vccsm vccsm vccsm vccsm vccsm vccsm ap29 rsv rsv rsv rsv rsv rsv ap30 rsv rsv rsv rsv rsv rsv ap31 swe_a# swe_a# swe_a# swe_a# swe_a# swe_a# ap32 rsv rsv rsv rsv rsv rsv ap33 rsv rsv rsv rsv rsv rsv ap34 scs_b0# scs_b0# scs_b0# scs_b0# scs_b0# scs_b0# ap35 nc nc nc nc nc nc ar1 nc nc nc nc nc nc ar2 nc nc nc nc nc nc ar3 vss vss vss vss vss vss ar4 ? ? ? ? ? ? ar5 sdq_a17 sdq_a17 sdq_a17 sdq_a17 sdq_a17 sdq_a17 ar6 vss vss vss vss vss vss ar7 rsv rsv rsv rsv rsv rsv ar8 sdq_a22 sdq_a22 sdq_a22 sdq_a22 sdq_a22 sdq_a22 ar9 scke_b3 rsv scke_b3 scke_b3 scke_b3 rsv ar10 vccsm vccsm vccsm vccsm vccsm vccsm ar11 scke_a3 rsv scke_a3 scke_a3 scke_a3 rsv ar12 sma_b11 sma_b11 sma_b11 sma_b11 sma_b11 sma_b11 ar13 vss vss vss vss vss vss ar14 vccsm vccsm vccsm vccsm vccsm vccsm ar15 sma_b4 sma_b4 sma_b4 sma_b4 sma_b4 sma_b4 ar16 sma_b3 sma_b3 sma_b3 sma_b3 sma_b3 sma_b3 ar17 vss vss vss vss vss vss ar18 vccsm vccsm vccsm vccsm vccsm vccsm ballout and package information r 364 datasheet ball # intel ? 82915GL gmch 6 intel ? 82915pl mch 5 intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 intel ? 82910gl gmch 4 ar19 sbs_b1 sbs_b1 sbs_b1 sbs_b1 sbs_b1 sbs_b1 ar20 sma_a6 sma_a6 sma_a6 sma_a6 sma_a6 sma_a6 ar21 vss vss vss vss vss vss ar22 vccsm vccsm vccsm vccsm vccsm vccsm ar23 rsv rsv rsv rsv rsv rsv ar24 rsv rsv rsv rsv rsv rsv ar25 vss vss vss vss vss vss ar26 vccsm vccsm vccsm vccsm vccsm vccsm ar27 swe_b# swe_b# swe_b# swe_b# swe_b# swe_b# ar28 rsv rsv rsv rsv rsv rsv ar29 rsv rsv rsv rsv rsv rsv ar30 vss vss vss vss vss vss ar31 vccsm vccsm vccsm vccsm vccsm vccsm ar32 ? ? ? ? ? ? ar33 vccsm vccsm vccsm vccsm vccsm vccsm ar34 nc nc nc nc nc nc ar35 nc nc nc nc nc nc notes: 1. ddr, pci express* x16 graphics interface, no dac, no intel ? sdvo 2. ddr, pci express* x16 graphics interface, dac, intel ? sdvo 3. ddr, no pci express* x16 graphics interface, dac, intel ? sdvo 4. ddr (one dimm per channel), no pci expre ss* x16 graphics interface, dac, intel ? sdvo 5. ddr (one dimm per channel), pci express* x 16 graphics interface, no dac, no intel ? sdvo 6. ddr, no pci express* x16 graphics interface, dac, intel ? sdvo ballout and package information r datasheet 365 table 14-4. gmch/mch ballout for ddr systems (sorted by signal name) intel ? 82915GL gmch 6 intel ? 82915pl mch 5 intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 intel ? 82910gl gmch 4 ball # blue rsv rsv blue blue blue h14 blue# rsv rsv blue# blue# blue# j14 bsel0 bsel0 bsel0 bsel0 bsel0 bsel0 h16 bsel1 bsel1 bsel1 bsel1 bsel1 bsel1 e15 bsel2 bsel2 bsel2 bsel2 bsel2 bsel2 d17 ddc_clk rsv rsv ddc_clk ddc_clk ddc_clk m15 ddc_data rsv rsv ddc_data ddc_data ddc_data l14 dmi_rxn0 dmi_rxn0 dmi_rxn0 dmi_rxn0 dmi_rxn0 dmi_rxn0 u6 dmi_rxn1 dmi_rxn1 dmi_rxn1 dmi_rxn1 dmi_rxn1 dmi_rxn1 t8 dmi_rxn2 dmi_rxn2 dmi_rxn2 dmi_rxn2 dmi_rxn2 dmi_rxn2 v8 dmi_rxn3 dmi_rxn3 dmi_rxn3 dmi_rxn3 dmi_rxn3 dmi_rxn3 u10 dmi_rxp0 dmi_rxp0 dmi_rxp0 dmi_rxp0 dmi_rxp0 dmi_rxp0 u5 dmi_rxp1 dmi_rxp1 dmi_rxp1 dmi_rxp1 dmi_rxp1 dmi_rxp1 t9 dmi_rxp2 dmi_rxp2 dmi_rxp2 dmi_rxp2 dmi_rxp2 dmi_rxp2 v7 dmi_rxp3 dmi_rxp3 dmi_rxp3 dmi_rxp3 dmi_rxp3 dmi_rxp3 v10 dmi_txn0 dmi_txn0 dmi_txn0 dm i_txn0 dmi_txn0 dmi_txn0 t3 dmi_txn1 dmi_txn1 dmi_txn1 dm i_txn1 dmi_txn1 dmi_txn1 u1 dmi_txn2 dmi_txn2 dmi_txn2 dmi_txn2 dmi_txn2 dmi_txn2 v3 dmi_txn3 dmi_txn3 dmi_txn3 dmi_txn3 dmi_txn3 dmi_txn3 w5 dmi_txp0 dmi_txp0 dmi_txp0 dmi_txp0 dmi_txp0 dmi_txp0 r3 dmi_txp1 dmi_txp1 dmi_txp1 dmi_txp1 dmi_txp1 dmi_txp1 t1 dmi_txp2 dmi_txp2 dmi_txp2 dmi_txp2 dmi_txp2 dmi_txp2 u3 dmi_txp3 dmi_txp3 dmi_txp3 dmi_txp3 dmi_txp3 dmi_txp3 v5 drefclkn drefclkn drefclkn dre fclkn drefclkn drefclkn m12 drefclkp drefclkp drefclkp drefclkp drefclkp drefclkp m13 rsv exp_compi exp_compi exp_compi rsv rsv w10 rsv exp_compo exp_compo exp_compo rsv rsv y10 sdvoc_tvclkin- exp_rxn0 exp_rxn0 exp_rxn0 sdvoc_ tvclkin- sdvoc_ tvclkin- f11 sdvob_int- exp_rxn1 exp_rxn1 exp_rx n1 sdvob_int- sdvob_int- h11 sdvoc_stall- exp_rxn2 exp_rxn2 exp_rxn2 sdvoc_stall- sdvoc_stall- e9 rsv exp_rxn3 exp_rxn3 exp_rxn3 rsv rsv e7 rsv exp_rxn4 exp_rxn4 exp_rxn4 rsv rsv b4 sdvoc_int- exp_rxn5 exp_rxn5 exp_rxn5 sdvoc_int- sdvoc_int- e5 rsv exp_rxn6 exp_rxn6 exp_rxn6 rsv rsv g5 rsv exp_rxn7 exp_rxn7 exp_rxn7 rsv rsv h7 rsv exp_rxn8 exp_rxn8 exp_rxn8 rsv rsv j5 rsv exp_rxn9 exp_rxn9 exp_rxn9 rsv rsv k7 ballout and package information r 366 datasheet intel ? 82915GL gmch 6 intel ? 82915pl mch 5 intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 intel ? 82910gl gmch 4 ball # rsv exp_rxn10 exp_rxn10 exp_rxn10 rsv rsv l5 rsv exp_rxn11 exp_rxn11 exp_rxn11 rsv rsv r10 rsv exp_rxn12 exp_rxn12 exp_rxn12 rsv rsv m7 rsv exp_rxn13 exp_rxn13 exp_rxn13 rsv rsv n5 rsv exp_rxn14 exp_rxn14 exp_rxn14 rsv rsv p8 rsv exp_rxn15 exp_rxn15 exp_rxn15 rsv rsv r5 sdvoc_tvclkin+ exp_rxp0 exp_rxp0 exp_rxp0 sdvoc_ tvclkin+ sdvoc_ tvclkin+ e11 sdvob_int+ exp_rxp1 exp_rxp1 exp_r xp1 sdvob_int+ sdvob_int+ j11 sdvoc_stall+ exp_rxp2 exp_rxp2 exp_rxp2 sdvoc_stall+ sdvoc_stall+ f9 rsv exp_rxp3 exp_rxp3 exp_rxp3 rsv rsv f7 rsv exp_rxp4 exp_rxp4 exp_rxp4 rsv rsv b3 sdvoc_int+ exp_rxp5 exp_rxp5 exp_rxp5 sdvoc_int+ sdvoc_int+ d5 rsv exp_rxp6 exp_rxp6 exp_rxp6 rsv rsv g6 rsv exp_rxp7 exp_rxp7 exp_rxp7 rsv rsv h8 rsv exp_rxp8 exp_rxp8 exp_rxp8 rsv rsv j6 rsv exp_rxp9 exp_rxp9 exp_rxp9 rsv rsv k8 rsv exp_rxp10 exp_rxp10 exp_rxp10 rsv rsv l6 rsv exp_rxp11 exp_rxp11 exp_rxp11 rsv rsv p10 rsv exp_rxp12 exp_rxp12 exp_rxp12 rsv rsv m8 rsv exp_rxp13 exp_rxp13 exp_rxp13 rsv rsv n6 rsv exp_rxp14 exp_rxp14 exp_rxp14 rsv rsv p7 rsv exp_rxp15 exp_rxp15 exp_rxp15 rsv rsv r6 rsv exp_slr exp_slr exp_slr rsv rsv a16 sdvob_red- exp_txn0 exp_txn0 exp_txn0 sdvob_red- sdvob_red- c9 sdvob_green- exp_txn1 exp_txn1 exp_txn1 sdvob_green- sdvob_green- a8 sdvob_blue- exp_txn2 exp_txn2 exp_txn2 sdvob_blue- sdvob_blue- c7 sdvob_clk- exp_txn3 exp_txn3 exp_tx n3 sdvob_clk- sdvob_clk- a6 sdvoc_red-/ sdvob_alpha- exp_txn4 exp_txn4 exp_txn4 sdvoc_red-/ sdvob_alpha- sdvoc_red-/ sdvob_alpha- c5 sdvoc_green- exp_txn5 exp_txn5 exp_txn5 sdvoc_green- sdvoc_green- d2 sdvoc_blue- exp_txn6 exp_txn6 exp_txn6 sdvoc_blue- sdvoc_blue- f3 sdvoc_clk- exp_txn7 exp_txn7 exp_txn7 sdvoc_clk- sdvoc_clk- g1 rsv exp_txn8 exp_txn8 exp_txn8 rsv rsv h3 rsv exp_txn9 exp_txn9 exp_txn9 rsv rsv j1 rsv exp_txn10 exp_txn10 exp_txn10 rsv rsv k3 rsv exp_txn11 exp_txn11 exp_txn11 rsv rsv l1 rsv exp_txn12 exp_txn12 exp_txn12 rsv rsv m3 rsv exp_txn13 exp_txn13 exp_txn13 rsv rsv n1 rsv exp_txn14 exp_txn14 exp_txn14 rsv rsv p3 rsv exp_txn15 exp_txn15 exp_txn15 rsv rsv r1 ballout and package information r datasheet 367 intel ? 82915GL gmch 6 intel ? 82915pl mch 5 intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 intel ? 82910gl gmch 4 ball # sdvob_red+ exp_txp0 exp_txp0 exp_t xp0 sdvob_red+ sdvob_red+ c10 sdvob_green+ exp_txp1 exp_txp1 exp_txp1 sdvob_ green+ sdvob_ green+ a9 sdvob_blue+ exp_txp2 exp_txp2 exp_t xp2 sdvob_blue+ sdvob_blue+ c8 sdvob_clk+ exp_txp3 exp_txp3 exp_t xp3 sdvob_clk+ sdvob_clk+ a7 sdvoc_red+/ sdvob_alpha+ exp_txp4 exp_txp4 exp_txp4 sdvoc_red+/ sdvob_ alpha+ sdvoc_red+/ sdvob_ alpha+ c6 sdvoc_green+ exp_txp5 exp_txp5 exp_txp5 sdvoc_green + sdvoc_green + c2 sdvoc_blue+ exp_txp6 exp_txp6 exp_t xp6 sdvoc_blue+ sdvoc_blue+ e3 sdvoc_clk+ exp_txp7 exp_txp7 exp_t xp7 sdvoc_clk+ sdvoc_clk+ f1 rsv exp_txp8 exp_txp8 exp_txp8 rsv rsv g3 rsv exp_txp9 exp_txp9 exp_txp9 rsv rsv h1 rsv exp_txp10 exp_txp10 exp_txp10 rsv rsv j3 rsv exp_txp11 exp_txp11 exp_txp11 rsv rsv k1 rsv exp_txp12 exp_txp12 exp_txp12 rsv rsv l3 rsv exp_txp13 exp_txp13 exp_txp13 rsv rsv m1 rsv exp_txp14 exp_txp14 exp_txp14 rsv rsv n3 rsv exp_txp15 exp_txp15 exp_txp15 rsv rsv p1 extts# extts# extts# ex tts# extts# extts# k16 gclkn gclkn gclkn gclkn gclkn gclkn b11 gclkp gclkp gclkp gclkp gclkp gclkp a11 green rsv rsv green green green d14 green# rsv rsv green# green# green# e14 ha3# ha3# ha3# ha3# ha3# ha3# h29 ha4# ha4# ha4# ha4# ha4# ha4# k29 ha5# ha5# ha5# ha5# ha5# ha5# j29 ha6# ha6# ha6# ha6# ha6# ha6# g30 ha7# ha7# ha7# ha7# ha7# ha7# g32 ha8# ha8# ha8# ha8# ha8# ha8# k30 ha9# ha9# ha9# ha9# ha9# ha9# l29 ha10# ha10# ha10# ha10# ha10# ha10# m30 ha11# ha11# ha11# ha11# ha11# ha11# l31 ha12# ha12# ha12# ha12# ha12# ha12# l28 ha13# ha13# ha13# ha13# ha13# ha13# j28 ha14# ha14# ha14# ha14# ha14# ha14# k27 ha15# ha15# ha15# ha15# ha15# ha15# k33 ha16# ha16# ha16# ha16# ha16# ha16# m28 ha17# ha17# ha17# ha17# ha17# ha17# r29 ha18# ha18# ha18# ha18# ha18# ha18# l26 ballout and package information r 368 datasheet intel ? 82915GL gmch 6 intel ? 82915pl mch 5 intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 intel ? 82910gl gmch 4 ball # ha19# ha19# ha19# ha19# ha19# ha19# n26 ha20# ha20# ha20# ha20# ha20# ha20# m26 ha21# ha21# ha21# ha21# ha21# ha21# n31 ha22# ha22# ha22# ha22# ha22# ha22# p26 ha23# ha23# ha23# ha23# ha23# ha23# n29 ha24# ha24# ha24# ha24# ha24# ha24# p28 ha25# ha25# ha25# ha25# ha25# ha25# r28 ha26# ha26# ha26# ha26# ha26# ha26# n33 ha27# ha27# ha27# ha27# ha27# ha27# t27 ha28# ha28# ha28# ha28# ha28# ha28# t31 ha29# ha29# ha29# ha29# ha29# ha29# u28 ha30# ha30# ha30# ha30# ha30# ha30# t26 ha31# ha31# ha31# ha31# ha31# ha31# t29 hads# hads# hads# hads# hads# hads# m31 hadstb0# hadstb0# hadstb0# ha dstb0# hadstb0# hadstb0# j31 hadstb1# hadstb1# hadstb1# ha dstb1# hadstb1# hadstb1# n27 hbnr# hbnr# hbnr# hbnr# hbnr# hbnr# m35 hbpri# hbpri# hbpri# hbpri# hbpri# hbpri# e30 hbreq0# hbreq0# hbreq0# hb req0# hbreq0# hbreq0# r33 hclkn hclkn hclkn hclkn hclkn hclkn m22 hclkp hclkp hclkp hclkp hclkp hclkp m23 hcpurst# hcpurst# hcpurst# hcp urst# hcpurst# hcpurst# g24 hd0 hd0 hd0 hd0 hd0 hd0 j33 hd1 hd1 hd1 hd1 hd1 hd1 h33 hd2 hd2 hd2 hd2 hd2 hd2 j34 hd3 hd3 hd3 hd3 hd3 hd3 g35 hd4 hd4 hd4 hd4 hd4 hd4 h35 hd5 hd5 hd5 hd5 hd5 hd5 g34 hd6 hd6 hd6 hd6 hd6 hd6 f34 hd7 hd7 hd7 hd7 hd7 hd7 g33 hd8 hd8 hd8 hd8 hd8 hd8 d34 hd9 hd9 hd9 hd9 hd9 hd9 c33 hd10 hd10 hd10 hd10 hd10 hd10 d33 hd11 hd11 hd11 hd11 hd11 hd11 b34 hd12 hd12 hd12 hd12 hd12 hd12 c34 hd13 hd13 hd13 hd13 hd13 hd13 b33 hd14 hd14 hd14 hd14 hd14 hd14 c32 hd15 hd15 hd15 hd15 hd15 hd15 b32 hd16 hd16 hd16 hd16 hd16 hd16 e28 hd17 hd17 hd17 hd17 hd17 hd17 c30 ballout and package information r datasheet 369 intel ? 82915GL gmch 6 intel ? 82915pl mch 5 intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 intel ? 82910gl gmch 4 ball # hd18 hd18 hd18 hd18 hd18 hd18 d29 hd19 hd19 hd19 hd19 hd19 hd19 h28 hd20 hd20 hd20 hd20 hd20 hd20 g29 hd21 hd21 hd21 hd21 hd21 hd21 j27 hd22 hd22 hd22 hd22 hd22 hd22 f28 hd23 hd23 hd23 hd23 hd23 hd23 f27 hd24 hd24 hd24 hd24 hd24 hd24 e27 hd25 hd25 hd25 hd25 hd25 hd25 e25 hd26 hd26 hd26 hd26 hd26 hd26 g25 hd27 hd27 hd27 hd27 hd27 hd27 j25 hd28 hd28 hd28 hd28 hd28 hd28 k25 hd29 hd29 hd29 hd29 hd29 hd29 l25 hd30 hd30 hd30 hd30 hd30 hd30 l23 hd31 hd31 hd31 hd31 hd31 hd31 k23 hd32 hd32 hd32 hd32 hd32 hd32 j22 hd33 hd33 hd33 hd33 hd33 hd33 j24 hd34 hd34 hd34 hd34 hd34 hd34 k22 hd35 hd35 hd35 hd35 hd35 hd35 j21 hd36 hd36 hd36 hd36 hd36 hd36 m21 hd37 hd37 hd37 hd37 hd37 hd37 h23 hd38 hd38 hd38 hd38 hd38 hd38 m19 hd39 hd39 hd39 hd39 hd39 hd39 k21 hd40 hd40 hd40 hd40 hd40 hd40 h20 hd41 hd41 hd41 hd41 hd41 hd41 h19 hd42 hd42 hd42 hd42 hd42 hd42 m18 hd43 hd43 hd43 hd43 hd43 hd43 k18 hd44 hd44 hd44 hd44 hd44 hd44 k17 hd45 hd45 hd45 hd45 hd45 hd45 g18 hd46 hd46 hd46 hd46 hd46 hd46 h18 hd47 hd47 hd47 hd47 hd47 hd47 f17 hd48 hd48 hd48 hd48 hd48 hd48 a25 hd49 hd49 hd49 hd49 hd49 hd49 c27 hd50 hd50 hd50 hd50 hd50 hd50 c31 hd51 hd51 hd51 hd51 hd51 hd51 b30 hd52 hd52 hd52 hd52 hd52 hd52 b31 hd53 hd53 hd53 hd53 hd53 hd53 a31 hd54 hd54 hd54 hd54 hd54 hd54 b27 hd55 hd55 hd55 hd55 hd55 hd55 a29 hd56 hd56 hd56 hd56 hd56 hd56 c28 hd57 hd57 hd57 hd57 hd57 hd57 a28 ballout and package information r 370 datasheet intel ? 82915GL gmch 6 intel ? 82915pl mch 5 intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 intel ? 82910gl gmch 4 ball # hd58 hd58 hd58 hd58 hd58 hd58 c25 hd59 hd59 hd59 hd59 hd59 hd59 c26 hd60 hd60 hd60 hd60 hd60 hd60 d27 hd61 hd61 hd61 hd61 hd61 hd61 a27 hd62 hd62 hd62 hd62 hd62 hd62 e24 hd63 hd63 hd63 hd63 hd63 hd63 b25 hdbsy# hdbsy# hdbsy# hdbsy# hdbsy# hdbsy# l35 hdefer# hdefer# hdefer# hde fer# hdefer# hdefer# j35 hdinv0# hdinv0# hdinv0# hdinv0# hdinv0# hdinv0# e34 hdinv1# hdinv1# hdinv1# hdinv1# hdinv1# hdinv1# j26 hdinv2# hdinv2# hdinv2# hdinv2# hdinv2# hdinv2# k19 hdinv3# hdinv3# hdinv3# hdinv3# hdinv3# hdinv3# b26 hdrdy# hdrdy# hdrdy# hdrdy# hdrdy# hdrdy# m32 hdstbn0# hdstbn0# hdstbn0# hds tbn0# hdstbn0# hdstbn0# e35 hdstbn1# hdstbn1# hdstbn1# hds tbn1# hdstbn1# hdstbn1# f26 hdstbn2# hdstbn2# hdstbn2# hds tbn2# hdstbn2# hdstbn2# f19 hdstbn3# hdstbn3# hdstbn3# hds tbn3# hdstbn3# hdstbn3# c29 hdstbp0# hdstbp0# hdstbp0# hds tbp0# hdstbp0# hdstbp0# e33 hdstbp1# hdstbp1# hdstbp1# hds tbp1# hdstbp1# hdstbp1# h26 hdstbp2# hdstbp2# hdstbp2# hds tbp2# hdstbp2# hdstbp2# j19 hdstbp3# hdstbp3# hdstbp3# hds tbp3# hdstbp3# hdstbp3# b29 hedrdy# hedrdy# hedrdy# hedrdy# hedrdy# hedrdy# p33 hhit# hhit# hhit# hhit# hhit# hhit# l34 hhitm# hhitm# hhitm# hhitm# hhitm# hhitm# n35 hlock# hlock# hlock# hlock# hlock# hlock# l33 hpcreq# hpcreq# hpcreq# hp creq# hpcreq# hpcreq# e31 hrcomp hrcomp hrcomp hrcomp hrcomp hrcomp b23 hreq0# hreq0# hreq0# hre q0# hreq0# hreq0# f33 hreq1# hreq1# hreq1# hreq1# hreq1# hreq1# e32 hreq2# hreq2# hreq2# hreq2# hreq2# hreq2# h31 hreq3# hreq3# hreq3# hre q3# hreq3# hreq3# g31 hreq4# hreq4# hreq4# hre q4# hreq4# hreq4# f31 hrs0# hrs0# hrs0# hrs0# hrs0# hrs0# k34 hrs1# hrs1# hrs1# hrs1# hrs1# hrs1# p34 hrs2# hrs2# hrs2# hrs2# hrs2# hrs2# j32 hscomp hscomp hscomp hs comp hscomp hscomp d24 hswing hswing hswing hs wing hswing hswing a23 hsync rsv rsv hsync hsync hsync e12 htrdy# htrdy# htrdy# htrdy# htrdy# htrdy# n34 hvref hvref hvref hv ref hvref hvref a24 ballout and package information r datasheet 371 intel ? 82915GL gmch 6 intel ? 82915pl mch 5 intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 intel ? 82910gl gmch 4 ball # ich_sync# ich_sync# ich_sync# ich_sync# ich_sync# ich_sync# m14 mtype mtype mtype mtype mtype mtype c15 nc nc nc nc nc nc a2 nc nc nc nc nc nc a34 nc nc nc nc nc nc a35 nc nc nc nc nc nc aa12 nc nc nc nc nc nc ab12 nc nc nc nc nc nc ac23 nc nc nc nc nc nc ac24 nc nc nc nc nc nc ad30 nc nc nc nc nc nc ag6 nc nc nc nc nc nc ah24 nc nc nc nc nc nc aj14 nc nc nc nc nc nc al28 nc nc nc nc nc nc an19 nc nc nc nc nc nc ap1 nc nc nc nc nc nc ap35 nc nc nc nc nc nc ar1 nc nc nc nc nc nc ar2 nc nc nc nc nc nc ar34 nc nc nc nc nc nc ar35 nc nc nc nc nc nc b1 nc nc nc nc nc nc b35 nc nc nc nc nc nc c16 nc nc nc nc nc nc e16 nc nc nc nc nc nc f12 nc nc nc nc nc nc f24 nc nc nc nc nc nc g12 nc nc nc nc nc nc h12 nc nc nc nc nc nc h15 nc nc nc nc nc nc h17 nc nc nc nc nc nc j12 nc nc nc nc nc nc k12 nc nc nc nc nc nc l12 nc nc nc nc nc nc l19 nc nc nc nc nc nc n12 nc nc nc nc nc nc n22 nc nc nc nc nc nc n23 nc nc nc nc nc nc n24 nc nc nc nc nc nc p12 ballout and package information r 372 datasheet intel ? 82915GL gmch 6 intel ? 82915pl mch 5 intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 intel ? 82910gl gmch 4 ball # nc nc nc nc nc nc p23 nc nc nc nc nc nc p24 nc nc nc nc nc nc p30 nc nc nc nc nc nc r12 nc nc nc nc nc nc r24 nc nc nc nc nc nc t12 nc nc nc nc nc nc u12 nc nc nc nc nc nc v12 nc nc nc nc nc nc w12 nc nc nc nc nc nc y12 pwrok pwrok pwrok pwrok pwrok pwrok ag7 red rsv rsv red red red f14 red# rsv rsv red# red# red# g14 refset rsv rsv refset refset refset a15 rstin# rstin# rstin# rstin# rstin# rstin# af7 rsv rsv rsv rsv rsv rsv aa30 rsv rsv rsv rsv rsv rsv aa31 rsv rsv rsv rsv rsv rsv aa35 rsv rsv rsv rsv rsv rsv ab29 rsv rsv rsv rsv rsv rsv ac12 rsv rsv rsv rsv rsv rsv ac13 rsv rsv rsv rsv rsv rsv ac14 rsv rsv rsv rsv rsv rsv ac15 rsv rsv rsv rsv rsv rsv ac16 rsv rsv rsv rsv rsv rsv ac17 rsv rsv rsv rsv rsv rsv ac18 rsv rsv rsv rsv rsv rsv ac19 rsv rsv rsv rsv rsv rsv ac20 rsv rsv rsv rsv rsv rsv ac21 rsv rsv rsv rsv rsv rsv ac22 rsv rsv rsv rsv rsv rsv ac30 rsv rsv rsv rsv rsv rsv ae5 rsv rsv rsv rsv rsv rsv af20 rsv rsv rsv rsv rsv rsv af5 rsv rsv rsv rsv rsv rsv ag17 rsv rsv rsv rsv rsv rsv ag2 rsv rsv rsv rsv rsv rsv ag26 rsv rsv rsv rsv rsv rsv ag33 rsv rsv rsv rsv rsv rsv ah10 rsv rsv rsv rsv rsv rsv ah30 ballout and package information r datasheet 373 intel ? 82915GL gmch 6 intel ? 82915pl mch 5 intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 intel ? 82910gl gmch 4 ball # rsv rsv rsv rsv rsv rsv aj18 rsv rsv rsv rsv rsv rsv aj20 rsv rsv rsv rsv rsv rsv aj21 rsv rsv rsv rsv rsv rsv aj23 rsv rsv rsv rsv rsv rsv aj24 rsv rsv rsv rsv rsv rsv ak18 rsv rsv rsv rsv rsv rsv ak21 rsv rsv rsv rsv rsv rsv ak24 rsv rsv rsv rsv rsv rsv al14 rsv rsv rsv rsv rsv rsv al2 rsv rsv rsv rsv rsv rsv al20 rsv rsv rsv rsv rsv rsv al21 rsv rsv rsv rsv rsv rsv al24 rsv rsv rsv rsv rsv rsv al29 rsv rsv rsv rsv rsv rsv al4 rsv rsv rsv rsv rsv rsv an31 rsv rsv rsv rsv rsv rsv an32 rsv rsv rsv rsv rsv rsv ap23 rsv rsv rsv rsv rsv rsv ap29 rsv rsv rsv rsv rsv rsv ap30 rsv rsv rsv rsv rsv rsv ap32 rsv rsv rsv rsv rsv rsv ap33 rsv rsv rsv rsv rsv rsv ar23 rsv rsv rsv rsv rsv rsv ar24 rsv rsv rsv rsv rsv rsv ar28 rsv rsv rsv rsv rsv rsv ar29 rsv rsv rsv rsv rsv rsv ar7 rsv rsv rsv rsv rsv rsv b15 rsv rsv rsv rsv rsv rsv c14 rsv rsv rsv rsv rsv rsv f15 rsv rsv rsv rsv rsv rsv g16 rsv rsv rsv rsv rsv rsv k15 rsv rsv rsv rsv rsv rsv m16 rsv rsv rsv rsv rsv rsv r30 rsv rsv rsv rsv rsv rsv r31 rsv rsv rsv rsv rsv rsv r35 rsv rsv rsv rsv rsv rsv u30 rsv rsv rsv rsv rsv rsv u35 rsv rsv rsv rsv rsv rsv v30 rsv rsv rsv rsv rsv rsv v31 ballout and package information r 374 datasheet intel ? 82915GL gmch 6 intel ? 82915pl mch 5 intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 intel ? 82910gl gmch 4 ball # rsv rsv rsv rsv rsv rsv v32 rsv rsv rsv rsv rsv rsv y28 rsv rsv rsv rsv rsv rsv y30 rsv_tp0 rsv_tp0 rsv_tp0 rsv_tp0 rsv_tp0 rsv_tp0 ae16 rsv_tp1 rsv_tp1 rsv_tp1 rsv_tp1 rsv_tp1 rsv_tp1 ah15 rsv_tp2 rsv_tp2 rsv_tp2 rsv_tp2 rsv_tp2 rsv_tp2 an14 rsv_tp3 rsv_tp3 rsv_tp3 rsv_tp3 rsv_tp3 rsv_tp3 ak15 sbs_a0 sbs_a0 sbs_a0 sbs_a0 sbs_a0 sbs_a0 an28 sbs_a1 sbs_a1 sbs_a1 sbs_a1 sbs_a1 sbs_a1 ap26 sbs_b0 sbs_b0 sbs_b0 sbs_b0 sbs_b0 sbs_b0 am27 sbs_b1 sbs_b1 sbs_b1 sbs_b1 sbs_b1 sbs_b1 ar19 scas_a# scas_a# scas_a# sc as_a# scas_a# scas_a# al34 scas_b# scas_b# scas_b# sc as_b# scas_b# scas_b# an27 scke_a0 scke_a0 scke_a0 sc ke_a0 scke_a0 scke_a0 al12 scke_a1 scke_a1 scke_a1 sc ke_a1 scke_a1 scke_a1 an11 scke_a2 rsv scke_a2 scke_a2 scke_a2 rsv ap11 scke_a3 rsv scke_a3 scke_a3 scke_a3 rsv ar11 scke_b0 scke_b0 scke_b0 sc ke_b0 scke_b0 scke_b0 an10 scke_b1 scke_b1 scke_b1 sc ke_b1 scke_b1 scke_b1 am9 scke_b2 rsv scke_b2 scke_b2 scke_b2 rsv ap10 scke_b3 rsv scke_b3 scke_b3 scke_b3 rsv ar9 sclk_a0 sclk_a0 sclk_a0 sclk_a0 sclk_a0 sclk_a0 am24 sclk_a0# sclk_a0# sclk_a0# sclk_a0# sclk_a0# sclk_a0# an25 sclk_a1 sclk_a1 sclk_a1 sclk_a1 sclk_a1 sclk_a1 an2 sclk_a1# sclk_a1# sclk_a1# sclk_a1# sclk_a1# sclk_a1# an3 sclk_a2 sclk_a2 sclk_a2 sclk_a2 sclk_a2 sclk_a2 ab34 sclk_a2# sclk_a2# sclk_a2# sclk_a2# sclk_a2# sclk_a2# ac33 sclk_a3 rsv sclk_a3 sclk_a3 sclk_a3 rsv ap25 sclk_a3# rsv sclk_a3# sclk_a3# sclk_a3# rsv an26 sclk_a4 rsv sclk_a4 sclk_a4 sclk_a4 rsv am2 sclk_a4# rsv sclk_a4# sclk_a4# sclk_a4# rsv am3 sclk_a5 rsv sclk_a5 sclk_a5 sclk_a5 rsv ac35 sclk_a5# rsv sclk_a5# sclk_a5# sclk_a5# rsv ac34 sclk_b0 sclk_b0 sclk_b0 sclk_b0 sclk_b0 sclk_b0 ah22 sclk_b0# sclk_b0# sclk_b0# sclk_b0# sclk_b0# sclk_b0# ag23 sclk_b1 sclk_b1 sclk_b1 sclk_b1 sclk_b1 sclk_b1 al11 sclk_b1# sclk_b1# sclk_b1# sclk_b1# sclk_b1# sclk_b1# aj11 sclk_b2 sclk_b2 sclk_b2 sclk_b2 sclk_b2 sclk_b2 ae26 sclk_b2# sclk_b2# sclk_b2# sclk_b2# sclk_b2# sclk_b2# ae25 sclk_b3 rsv sclk_b3 sclk_b3 sclk_b3 rsv al23 ballout and package information r datasheet 375 intel ? 82915GL gmch 6 intel ? 82915pl mch 5 intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 intel ? 82910gl gmch 4 ball # sclk_b3# rsv sclk_b3# sclk_b3# sclk_b3# rsv ak22 sclk_b4 rsv sclk_b4 sclk_b4 sclk_b4 rsv ak9 sclk_b4# rsv sclk_b4# sclk_b4# sclk_b4# rsv al9 sclk_b5 rsv sclk_b5 sclk_b5 sclk_b5 rsv ad29 sclk_b5# rsv sclk_b5# sclk_b5# sclk_b5# rsv ad28 scs_a0# scs_a0# scs_a0# scs_a0# scs_a0# scs_a0# am34 scs_a1# scs_a1# scs_a1# scs_a1# scs_a1# scs_a1# al35 scs_a2# rsv scs_a2# scs_a2# scs_a2# rsv ak34 scs_a3# rsv scs_a3# scs_a3# scs_a3# rsv al33 scs_b0# scs_b0# scs_b0# scs_b0# scs_b0# scs_b0# ap34 scs_b1# scs_b1# scs_b1# scs_b1# scs_b1# scs_b1# an34 scs_b2# rsv scs_b2# scs_b2# scs_b2# rsv an33 scs_b3# rsv scs_b3# scs_b3# scs_b3# rsv am33 sdm_a0 sdm_a0 sdm_a0 sdm_a0 sdm_a0 sdm_a0 af2 sdm_a1 sdm_a1 sdm_a1 sdm_a1 sdm_a1 sdm_a1 al1 sdm_a2 sdm_a2 sdm_a2 sdm_a2 sdm_a2 sdm_a2 an7 sdm_a3 sdm_a3 sdm_a3 sdm_a3 sdm_a3 sdm_a3 ah16 sdm_a4 sdm_a4 sdm_a4 sdm_a4 sdm_a4 sdm_a4 ak29 sdm_a5 sdm_a5 sdm_a5 sdm_a5 sdm_a5 sdm_a5 ag34 sdm_a6 sdm_a6 sdm_a6 sdm_a6 sdm_a6 sdm_a6 aa33 sdm_a7 sdm_a7 sdm_a7 sdm_a7 sdm_a7 sdm_a7 u33 sdm_b0 sdm_b0 sdm_b0 sdm_b0 sdm_b0 sdm_b0 aj5 sdm_b1 sdm_b1 sdm_b1 sdm_b1 sdm_b1 sdm_b1 ah9 sdm_b2 sdm_b2 sdm_b2 sdm_b2 sdm_b2 sdm_b2 ah13 sdm_b3 sdm_b3 sdm_b3 sdm_b3 sdm_b3 sdm_b3 ag20 sdm_b4 sdm_b4 sdm_b4 sdm_b4 sdm_b4 sdm_b4 ag24 sdm_b5 sdm_b5 sdm_b5 sdm_b5 sdm_b5 sdm_b5 ah31 sdm_b6 sdm_b6 sdm_b6 sdm_b6 sdm_b6 sdm_b6 ad24 sdm_b7 sdm_b7 sdm_b7 sdm_b7 sdm_b7 sdm_b7 w31 sdq_a0 sdq_a0 sdq_a0 sdq_a0 sdq_a0 sdq_a0 ae3 sdq_a1 sdq_a1 sdq_a1 sdq_a1 sdq_a1 sdq_a1 af3 sdq_a2 sdq_a2 sdq_a2 sdq_a2 sdq_a2 sdq_a2 ah2 sdq_a3 sdq_a3 sdq_a3 sdq_a3 sdq_a3 sdq_a3 aj2 sdq_a4 sdq_a4 sdq_a4 sdq_a4 sdq_a4 sdq_a4 ae2 sdq_a5 sdq_a5 sdq_a5 sdq_a5 sdq_a5 sdq_a5 ae1 sdq_a6 sdq_a6 sdq_a6 sdq_a6 sdq_a6 sdq_a6 ag3 sdq_a7 sdq_a7 sdq_a7 sdq_a7 sdq_a7 sdq_a7 ah3 sdq_a8 sdq_a8 sdq_a8 sdq_a8 sdq_a8 sdq_a8 aj1 sdq_a9 sdq_a9 sdq_a9 sdq_a9 sdq_a9 sdq_a9 ak2 sdq_a10 sdq_a10 sdq_a10 sdq_a10 sdq_a10 sdq_a10 an4 ballout and package information r 376 datasheet intel ? 82915GL gmch 6 intel ? 82915pl mch 5 intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 intel ? 82910gl gmch 4 ball # sdq_a11 sdq_a11 sdq_a11 sdq_a11 sdq_a11 sdq_a11 ap4 sdq_a12 sdq_a12 sdq_a12 sdq_a12 sdq_a12 sdq_a12 aj3 sdq_a13 sdq_a13 sdq_a13 sdq_a13 sdq_a13 sdq_a13 ak3 sdq_a14 sdq_a14 sdq_a14 sdq_a14 sdq_a14 sdq_a14 ap2 sdq_a15 sdq_a15 sdq_a15 sdq_a15 sdq_a15 sdq_a15 ap3 sdq_a16 sdq_a16 sdq_a16 sdq_a16 sdq_a16 sdq_a16 ap5 sdq_a17 sdq_a17 sdq_a17 sdq_a17 sdq_a17 sdq_a17 ar5 sdq_a18 sdq_a18 sdq_a18 sdq_a18 sdq_a18 sdq_a18 an8 sdq_a19 sdq_a19 sdq_a19 sdq_a19 sdq_a19 sdq_a19 ap9 sdq_a20 sdq_a20 sdq_a20 sdq_a20 sdq_a20 sdq_a20 an5 sdq_a21 sdq_a21 sdq_a21 sdq_a21 sdq_a21 sdq_a21 ap6 sdq_a22 sdq_a22 sdq_a22 sdq_a22 sdq_a22 sdq_a22 ar8 sdq_a23 sdq_a23 sdq_a23 sdq_a23 sdq_a23 sdq_a23 an9 sdq_a24 sdq_a24 sdq_a24 sdq_a24 sdq_a24 sdq_a24 ak16 sdq_a25 sdq_a25 sdq_a25 sdq_a25 sdq_a25 sdq_a25 al17 sdq_a26 sdq_a26 sdq_a26 sdq_a26 sdq_a26 sdq_a26 ad17 sdq_a27 sdq_a27 sdq_a27 sdq_a27 sdq_a27 sdq_a27 af19 sdq_a28 sdq_a28 sdq_a28 sdq_a28 sdq_a28 sdq_a28 af16 sdq_a29 sdq_a29 sdq_a29 sdq_a29 sdq_a29 sdq_a29 aj17 sdq_a30 sdq_a30 sdq_a30 sdq_a30 sdq_a30 sdq_a30 ae19 sdq_a31 sdq_a31 sdq_a31 sdq_a31 sdq_a31 sdq_a31 ah18 sdq_a32 sdq_a32 sdq_a32 sdq_a32 sdq_a32 sdq_a32 ah27 sdq_a33 sdq_a33 sdq_a33 sdq_a33 sdq_a33 sdq_a33 ak27 sdq_a34 sdq_a34 sdq_a34 sdq_a34 sdq_a34 sdq_a34 an30 sdq_a35 sdq_a35 sdq_a35 sdq_a35 sdq_a35 sdq_a35 ak31 sdq_a36 sdq_a36 sdq_a36 sdq_a36 sdq_a36 sdq_a36 al27 sdq_a37 sdq_a37 sdq_a37 sdq_a37 sdq_a37 sdq_a37 aj28 sdq_a38 sdq_a38 sdq_a38 sdq_a38 sdq_a38 sdq_a38 al30 sdq_a39 sdq_a39 sdq_a39 sdq_a39 sdq_a39 sdq_a39 al31 sdq_a40 sdq_a40 sdq_a40 sdq_a40 sdq_a40 sdq_a40 aj34 sdq_a41 sdq_a41 sdq_a41 sdq_a41 sdq_a41 sdq_a41 ah35 sdq_a42 sdq_a42 sdq_a42 sdq_a42 sdq_a42 sdq_a42 ag32 sdq_a43 sdq_a43 sdq_a43 sdq_a43 sdq_a43 sdq_a43 af34 sdq_a44 sdq_a44 sdq_a44 sdq_a44 sdq_a44 sdq_a44 aj33 sdq_a45 sdq_a45 sdq_a45 sdq_a45 sdq_a45 sdq_a45 ah33 sdq_a46 sdq_a46 sdq_a46 sdq_a46 sdq_a46 sdq_a46 af33 sdq_a47 sdq_a47 sdq_a47 sdq_a47 sdq_a47 sdq_a47 ae33 sdq_a48 sdq_a48 sdq_a48 sdq_a48 sdq_a48 sdq_a48 ae35 sdq_a49 sdq_a49 sdq_a49 sdq_a49 sdq_a49 sdq_a49 ae34 sdq_a50 sdq_a50 sdq_a50 sdq_a50 sdq_a50 sdq_a50 y33 ballout and package information r datasheet 377 intel ? 82915GL gmch 6 intel ? 82915pl mch 5 intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 intel ? 82910gl gmch 4 ball # sdq_a51 sdq_a51 sdq_a51 sdq_a51 sdq_a51 sdq_a51 w34 sdq_a52 sdq_a52 sdq_a52 sdq_a52 sdq_a52 sdq_a52 ad31 sdq_a53 sdq_a53 sdq_a53 sdq_a53 sdq_a53 sdq_a53 ad35 sdq_a54 sdq_a54 sdq_a54 sdq_a54 sdq_a54 sdq_a54 aa32 sdq_a55 sdq_a55 sdq_a55 sdq_a55 sdq_a55 sdq_a55 y35 sdq_a56 sdq_a56 sdq_a56 sdq_a56 sdq_a56 sdq_a56 v34 sdq_a57 sdq_a57 sdq_a57 sdq_a57 sdq_a57 sdq_a57 v33 sdq_a58 sdq_a58 sdq_a58 sdq_a58 sdq_a58 sdq_a58 r32 sdq_a59 sdq_a59 sdq_a59 sdq_a59 sdq_a59 sdq_a59 r34 sdq_a60 sdq_a60 sdq_a60 sdq_a60 sdq_a60 sdq_a60 w35 sdq_a61 sdq_a61 sdq_a61 sdq_a61 sdq_a61 sdq_a61 w33 sdq_a62 sdq_a62 sdq_a62 sdq_a62 sdq_a62 sdq_a62 t33 sdq_a63 sdq_a63 sdq_a63 sdq_a63 sdq_a63 sdq_a63 t35 sdq_b0 sdq_b0 sdq_b0 sdq_b0 sdq_b0 sdq_b0 ah7 sdq_b1 sdq_b1 sdq_b1 sdq_b1 sdq_b1 sdq_b1 aj6 sdq_b2 sdq_b2 sdq_b2 sdq_b2 sdq_b2 sdq_b2 al5 sdq_b3 sdq_b3 sdq_b3 sdq_b3 sdq_b3 sdq_b3 an6 sdq_b4 sdq_b4 sdq_b4 sdq_b4 sdq_b4 sdq_b4 ag9 sdq_b5 sdq_b5 sdq_b5 sdq_b5 sdq_b5 sdq_b5 ah4 sdq_b6 sdq_b6 sdq_b6 sdq_b6 sdq_b6 sdq_b6 am5 sdq_b7 sdq_b7 sdq_b7 sdq_b7 sdq_b7 sdq_b7 al6 sdq_b8 sdq_b8 sdq_b8 sdq_b8 sdq_b8 sdq_b8 aj7 sdq_b9 sdq_b9 sdq_b9 sdq_b9 sdq_b9 sdq_b9 al7 sdq_b10 sdq_b10 sdq_b10 sdq_b10 sdq_b10 sdq_b10 af11 sdq_b11 sdq_b11 sdq_b11 sdq_b11 sdq_b11 sdq_b11 ae11 sdq_b12 sdq_b12 sdq_b12 sdq_b12 sdq_b12 sdq_b12 aj8 sdq_b13 sdq_b13 sdq_b13 sdq_b13 sdq_b13 sdq_b13 al8 sdq_b14 sdq_b14 sdq_b14 sdq_b14 sdq_b14 sdq_b14 ag10 sdq_b15 sdq_b15 sdq_b15 sdq_b15 sdq_b15 sdq_b15 ag11 sdq_b16 sdq_b16 sdq_b16 sdq_b16 sdq_b16 sdq_b16 ae13 sdq_b17 sdq_b17 sdq_b17 sdq_b17 sdq_b17 sdq_b17 af13 sdq_b18 sdq_b18 sdq_b18 sdq_b18 sdq_b18 sdq_b18 ag14 sdq_b19 sdq_b19 sdq_b19 sdq_b19 sdq_b19 sdq_b19 ad14 sdq_b20 sdq_b20 sdq_b20 sdq_b20 sdq_b20 sdq_b20 ad12 sdq_b21 sdq_b21 sdq_b21 sdq_b21 sdq_b21 sdq_b21 ah12 sdq_b22 sdq_b22 sdq_b22 sdq_b22 sdq_b22 sdq_b22 af14 sdq_b23 sdq_b23 sdq_b23 sdq_b23 sdq_b23 sdq_b23 ad15 sdq_b24 sdq_b24 sdq_b24 sdq_b24 sdq_b24 sdq_b24 ad18 sdq_b25 sdq_b25 sdq_b25 sdq_b25 sdq_b25 sdq_b25 ak19 sdq_b26 sdq_b26 sdq_b26 sdq_b26 sdq_b26 sdq_b26 ae22 ballout and package information r 378 datasheet intel ? 82915GL gmch 6 intel ? 82915pl mch 5 intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 intel ? 82910gl gmch 4 ball # sdq_b27 sdq_b27 sdq_b27 sdq_b27 sdq_b27 sdq_b27 ah21 sdq_b28 sdq_b28 sdq_b28 sdq_b28 sdq_b28 sdq_b28 al18 sdq_b29 sdq_b29 sdq_b29 sdq_b29 sdq_b29 sdq_b29 ah19 sdq_b30 sdq_b30 sdq_b30 sdq_b30 sdq_b30 sdq_b30 af22 sdq_b31 sdq_b31 sdq_b31 sdq_b31 sdq_b31 sdq_b31 ad21 sdq_b32 sdq_b32 sdq_b32 sdq_b32 sdq_b32 sdq_b32 af23 sdq_b33 sdq_b33 sdq_b33 sdq_b33 sdq_b33 sdq_b33 af25 sdq_b34 sdq_b34 sdq_b34 sdq_b34 sdq_b34 sdq_b34 al25 sdq_b35 sdq_b35 sdq_b35 sdq_b35 sdq_b35 sdq_b35 aj26 sdq_b36 sdq_b36 sdq_b36 sdq_b36 sdq_b36 sdq_b36 ad23 sdq_b37 sdq_b37 sdq_b37 sdq_b37 sdq_b37 sdq_b37 af24 sdq_b38 sdq_b38 sdq_b38 sdq_b38 sdq_b38 sdq_b38 aj25 sdq_b39 sdq_b39 sdq_b39 sdq_b39 sdq_b39 sdq_b39 al26 sdq_b40 sdq_b40 sdq_b40 sdq_b40 sdq_b40 sdq_b40 aj29 sdq_b41 sdq_b41 sdq_b41 sdq_b41 sdq_b41 sdq_b41 aj31 sdq_b42 sdq_b42 sdq_b42 sdq_b42 sdq_b42 sdq_b42 ag30 sdq_b43 sdq_b43 sdq_b43 sdq_b43 sdq_b43 sdq_b43 ag31 sdq_b44 sdq_b44 sdq_b44 sdq_b44 sdq_b44 sdq_b44 ak33 sdq_b45 sdq_b45 sdq_b45 sdq_b45 sdq_b45 sdq_b45 ak32 sdq_b46 sdq_b46 sdq_b46 sdq_b46 sdq_b46 sdq_b46 ag27 sdq_b47 sdq_b47 sdq_b47 sdq_b47 sdq_b47 sdq_b47 af28 sdq_b48 sdq_b48 sdq_b48 sdq_b48 sdq_b48 sdq_b48 ae31 sdq_b49 sdq_b49 sdq_b49 sdq_b49 sdq_b49 sdq_b49 af27 sdq_b50 sdq_b50 sdq_b50 sdq_b50 sdq_b50 sdq_b50 ab27 sdq_b51 sdq_b51 sdq_b51 sdq_b51 sdq_b51 sdq_b51 ab26 sdq_b52 sdq_b52 sdq_b52 sdq_b52 sdq_b52 sdq_b52 ae29 sdq_b53 sdq_b53 sdq_b53 sdq_b53 sdq_b53 sdq_b53 ae27 sdq_b54 sdq_b54 sdq_b54 sdq_b54 sdq_b54 sdq_b54 ac28 sdq_b55 sdq_b55 sdq_b55 sdq_b55 sdq_b55 sdq_b55 ac26 sdq_b56 sdq_b56 sdq_b56 sdq_b56 sdq_b56 sdq_b56 aa29 sdq_b57 sdq_b57 sdq_b57 sdq_b57 sdq_b57 sdq_b57 w29 sdq_b58 sdq_b58 sdq_b58 sdq_b58 sdq_b58 sdq_b58 u26 sdq_b59 sdq_b59 sdq_b59 sdq_b59 sdq_b59 sdq_b59 v29 sdq_b60 sdq_b60 sdq_b60 sdq_b60 sdq_b60 sdq_b60 y26 sdq_b61 sdq_b61 sdq_b61 sdq_b61 sdq_b61 sdq_b61 aa28 sdq_b62 sdq_b62 sdq_b62 sdq_b62 sdq_b62 sdq_b62 w26 sdq_b63 sdq_b63 sdq_b63 sdq_b63 sdq_b63 sdq_b63 v28 sdqs_a0 sdqs_a0 sdqs_a0 sd qs_a0 sdqs_a0 sdqs_a0 ag1 sdqs_a1 sdqs_a1 sdqs_a1 sd qs_a1 sdqs_a1 sdqs_a1 al3 sdqs_a2 sdqs_a2 sdqs_a2 sd qs_a2 sdqs_a2 sdqs_a2 ap7 ballout and package information r datasheet 379 intel ? 82915GL gmch 6 intel ? 82915pl mch 5 intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 intel ? 82910gl gmch 4 ball # sdqs_a3 sdqs_a3 sdqs_a3 sd qs_a3 sdqs_a3 sdqs_a3 af17 sdqs_a4 sdqs_a4 sdqs_a4 sd qs_a4 sdqs_a4 sdqs_a4 am30 sdqs_a5 sdqs_a5 sdqs_a5 sd qs_a5 sdqs_a5 sdqs_a5 ag35 sdqs_a6 sdqs_a6 sdqs_a6 sd qs_a6 sdqs_a6 sdqs_a6 aa34 sdqs_a7 sdqs_a7 sdqs_a7 sd qs_a7 sdqs_a7 sdqs_a7 u34 sdqs_b0 sdqs_b0 sdqs_b0 sd qs_b0 sdqs_b0 sdqs_b0 ak5 sdqs_b1 sdqs_b1 sdqs_b1 sd qs_b1 sdqs_b1 sdqs_b1 ak10 sdqs_b2 sdqs_b2 sdqs_b2 sd qs_b2 sdqs_b2 sdqs_b2 ak13 sdqs_b3 sdqs_b3 sdqs_b3 sd qs_b3 sdqs_b3 sdqs_b3 ad20 sdqs_b4 sdqs_b4 sdqs_b4 sd qs_b4 sdqs_b4 sdqs_b4 ah25 sdqs_b5 sdqs_b5 sdqs_b5 sd qs_b5 sdqs_b5 sdqs_b5 ah28 sdqs_b6 sdqs_b6 sdqs_b6 sd qs_b6 sdqs_b6 sdqs_b6 ab31 sdqs_b7 sdqs_b7 sdqs_b7 sd qs_b7 sdqs_b7 sdqs_b7 w27 sdvo_ctrlclk rsv rsv sdvo_ctrlc lk sdvo_ctrlclk sdvo_ctrlclk j13 sdvo_ctrldata rsv rsv sdvo_ctrld ata sdvo_ctrldat a sdvo_ctrldat a k13 sm_slewin0 sm_slewin0 sm_slewin0 sm_slewin0 sm_slewin0 sm_slewin0 aj12 sm_slewin1 sm_slewin1 sm_slewin1 sm_slewin1 sm_slewin1 sm_slewin1 af9 sm_slewout0 sm_slewou t0 sm_slewou t0 sm_slewou t0 sm_slewout0 sm_slewout0 ak12 sm_slewout1 sm_slewou t1 sm_slewou t1 sm_slewou t1 sm_slewout1 sm_slewout1 ae10 sma_a0 sma_a0 sma_a0 sma_a0 sma_a0 sma_a0 an22 sma_a1 sma_a1 sma_a1 sma_a1 sma_a1 sma_a1 ap22 sma_a2 sma_a2 sma_a2 sma_a2 sma_a2 sma_a2 an21 sma_a3 sma_a3 sma_a3 sma_a3 sma_a3 sma_a3 ap21 sma_a4 sma_a4 sma_a4 sma_a4 sma_a4 sma_a4 am21 sma_a5 sma_a5 sma_a5 sma_a5 sma_a5 sma_a5 ap19 sma_a6 sma_a6 sma_a6 sma_a6 sma_a6 sma_a6 ar20 sma_a7 sma_a7 sma_a7 sma_a7 sma_a7 sma_a7 an16 sma_a8 sma_a8 sma_a8 sma_a8 sma_a8 sma_a8 an18 sma_a9 sma_a9 sma_a9 sma_a9 sma_a9 sma_a9 am15 sma_a10 sma_a10 sma_a10 sma_a10 sma_a10 sma_a10 an23 sma_a11 sma_a11 sma_a11 sma_a11 sma_a11 sma_a11 ap15 sma_a12 sma_a12 sma_a12 sma_a12 sma_a12 sma_a12 ap13 sma_a13 sma_a13 sma_a13 sma_a13 sma_a13 sma_a13 ab33 sma_b0 sma_b0 sma_b0 sma_b0 sma_b0 sma_b0 am18 sma_b1 sma_b1 sma_b1 sma_b1 sma_b1 sma_b1 ap18 sma_b2 sma_b2 sma_b2 sma_b2 sma_b2 sma_b2 an17 sma_b3 sma_b3 sma_b3 sma_b3 sma_b3 sma_b3 ar16 ballout and package information r 380 datasheet intel ? 82915GL gmch 6 intel ? 82915pl mch 5 intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 intel ? 82910gl gmch 4 ball # sma_b4 sma_b4 sma_b4 sma_b4 sma_b4 sma_b4 ar15 sma_b5 sma_b5 sma_b5 sma_b5 sma_b5 sma_b5 an15 sma_b6 sma_b6 sma_b6 sma_b6 sma_b6 sma_b6 ap17 sma_b7 sma_b7 sma_b7 sma_b7 sma_b7 sma_b7 al15 sma_b8 sma_b8 sma_b8 sma_b8 sma_b8 sma_b8 ap14 sma_b9 sma_b9 sma_b9 sma_b9 sma_b9 sma_b9 an13 sma_b10 sma_b10 sma_b10 sma_b10 sma_b10 sma_b10 an20 sma_b11 sma_b11 sma_b11 sma_b11 sma_b11 sma_b11 ar12 sma_b12 sma_b12 sma_b12 sma_b12 sma_b12 sma_b12 am12 sma_b13 sma_b13 sma_b13 sma_b13 sma_b13 sma_b13 ad32 sras_a# sras_a# sras_a# sr as_a# sras_a# sras_a# an29 sras_b# sras_b# sras_b# sr as_b# sras_b# sras_b# ap27 srcomp0 srcomp0 srcomp0 s rcomp0 srcomp0 srcomp0 ag4 srcomp1 srcomp1 srcomp1 s rcomp1 srcomp1 srcomp1 ag8 svref0 svref0 svref0 svr ef0 svref0 svref0 ae7 svref1 svref1 svref1 svr ef1 svref1 svref1 ae8 swe_a# swe_a# swe_a# swe_a# swe_a# swe_a# ap31 swe_b# swe_b# swe_b# swe_b# swe_b# swe_b# ar27 vcc vcc vcc vcc vcc vcc aa13 vcc vcc vcc vcc vcc vcc aa14 vcc vcc vcc vcc vcc vcc aa16 vcc vcc vcc vcc vcc vcc aa18 vcc vcc vcc vcc vcc vcc aa20 vcc vcc vcc vcc vcc vcc aa21 vcc vcc vcc vcc vcc vcc aa22 vcc vcc vcc vcc vcc vcc aa23 vcc vcc vcc vcc vcc vcc aa24 vcc vcc vcc vcc vcc vcc ab1 vcc vcc vcc vcc vcc vcc ab10 vcc vcc vcc vcc vcc vcc ab11 vcc vcc vcc vcc vcc vcc ab13 vcc vcc vcc vcc vcc vcc ab14 vcc vcc vcc vcc vcc vcc ab15 vcc vcc vcc vcc vcc vcc ab16 vcc vcc vcc vcc vcc vcc ab17 vcc vcc vcc vcc vcc vcc ab18 vcc vcc vcc vcc vcc vcc ab19 vcc vcc vcc vcc vcc vcc ab2 vcc vcc vcc vcc vcc vcc ab20 vcc vcc vcc vcc vcc vcc ab21 ballout and package information r datasheet 381 intel ? 82915GL gmch 6 intel ? 82915pl mch 5 intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 intel ? 82910gl gmch 4 ball # vcc vcc vcc vcc vcc vcc ab22 vcc vcc vcc vcc vcc vcc ab23 vcc vcc vcc vcc vcc vcc ab24 vcc vcc vcc vcc vcc vcc ab3 vcc vcc vcc vcc vcc vcc ab4 vcc vcc vcc vcc vcc vcc ab5 vcc vcc vcc vcc vcc vcc ab6 vcc vcc vcc vcc vcc vcc ab7 vcc vcc vcc vcc vcc vcc ab8 vcc vcc vcc vcc vcc vcc ab9 vcc vcc vcc vcc vcc vcc ac1 vcc vcc vcc vcc vcc vcc ac10 vcc vcc vcc vcc vcc vcc ac11 vcc vcc vcc vcc vcc vcc ac2 vcc vcc vcc vcc vcc vcc ac3 vcc vcc vcc vcc vcc vcc ac4 vcc vcc vcc vcc vcc vcc ac5 vcc vcc vcc vcc vcc vcc ac6 vcc vcc vcc vcc vcc vcc ac7 vcc vcc vcc vcc vcc vcc ac8 vcc vcc vcc vcc vcc vcc ac9 vcc vcc vcc vcc vcc vcc ad1 vcc vcc vcc vcc vcc vcc ad10 vcc vcc vcc vcc vcc vcc ad2 vcc vcc vcc vcc vcc vcc ad3 vcc vcc vcc vcc vcc vcc ad4 vcc vcc vcc vcc vcc vcc ad5 vcc vcc vcc vcc vcc vcc ad6 vcc vcc vcc vcc vcc vcc ad7 vcc vcc vcc vcc vcc vcc ad8 vcc vcc vcc vcc vcc vcc ad9 vcc vcc vcc vcc vcc vcc l10 vcc vcc vcc vcc vcc vcc n13 vcc vcc vcc vcc vcc vcc n14 vcc vcc vcc vcc vcc vcc n15 vcc vcc vcc vcc vcc vcc n16 vcc vcc vcc vcc vcc vcc n18 vcc vcc vcc vcc vcc vcc n20 vcc vcc vcc vcc vcc vcc n21 vcc vcc vcc vcc vcc vcc p13 ballout and package information r 382 datasheet intel ? 82915GL gmch 6 intel ? 82915pl mch 5 intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 intel ? 82910gl gmch 4 ball # vcc vcc vcc vcc vcc vcc p14 vcc vcc vcc vcc vcc vcc p15 vcc vcc vcc vcc vcc vcc p17 vcc vcc vcc vcc vcc vcc p19 vcc vcc vcc vcc vcc vcc p21 vcc vcc vcc vcc vcc vcc p22 vcc vcc vcc vcc vcc vcc r13 vcc vcc vcc vcc vcc vcc r14 vcc vcc vcc vcc vcc vcc r15 vcc vcc vcc vcc vcc vcc r16 vcc vcc vcc vcc vcc vcc r18 vcc vcc vcc vcc vcc vcc r20 vcc vcc vcc vcc vcc vcc r22 vcc vcc vcc vcc vcc vcc r23 vcc vcc vcc vcc vcc vcc t13 vcc vcc vcc vcc vcc vcc t14 vcc vcc vcc vcc vcc vcc t15 vcc vcc vcc vcc vcc vcc t16 vcc vcc vcc vcc vcc vcc t17 vcc vcc vcc vcc vcc vcc t19 vcc vcc vcc vcc vcc vcc t20 vcc vcc vcc vcc vcc vcc t21 vcc vcc vcc vcc vcc vcc t23 vcc vcc vcc vcc vcc vcc t24 vcc vcc vcc vcc vcc vcc u13 vcc vcc vcc vcc vcc vcc u14 vcc vcc vcc vcc vcc vcc u16 vcc vcc vcc vcc vcc vcc u18 vcc vcc vcc vcc vcc vcc u20 vcc vcc vcc vcc vcc vcc u22 vcc vcc vcc vcc vcc vcc u24 vcc vcc vcc vcc vcc vcc v13 vcc vcc vcc vcc vcc vcc v14 vcc vcc vcc vcc vcc vcc v15 vcc vcc vcc vcc vcc vcc v17 vcc vcc vcc vcc vcc vcc v19 vcc vcc vcc vcc vcc vcc v21 vcc vcc vcc vcc vcc vcc v23 vcc vcc vcc vcc vcc vcc v24 vcc vcc vcc vcc vcc vcc w13 ballout and package information r datasheet 383 intel ? 82915GL gmch 6 intel ? 82915pl mch 5 intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 intel ? 82910gl gmch 4 ball # vcc vcc vcc vcc vcc vcc w14 vcc vcc vcc vcc vcc vcc w16 vcc vcc vcc vcc vcc vcc w18 vcc vcc vcc vcc vcc vcc w20 vcc vcc vcc vcc vcc vcc w22 vcc vcc vcc vcc vcc vcc w24 vcc vcc vcc vcc vcc vcc y13 vcc vcc vcc vcc vcc vcc y14 vcc vcc vcc vcc vcc vcc y15 vcc vcc vcc vcc vcc vcc y16 vcc vcc vcc vcc vcc vcc y17 vcc vcc vcc vcc vcc vcc y19 vcc vcc vcc vcc vcc vcc y20 vcc vcc vcc vcc vcc vcc y21 vcc vcc vcc vcc vcc vcc y23 vcc vcc vcc vcc vcc vcc y24 vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp w1 vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp w2 vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp w3 vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp w4 vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp w6 vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp w7 vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp w8 vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp w9 vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp y1 vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp y2 vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp y3 vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp y4 vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp y5 vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp y6 vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp y7 vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp y8 vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp y9 vcc2 vcc2 vcc2 vcc2 vcc2 vcc2 a13 vcca_dac rsv rsv vcca_dac vcca_dac vcca_dac d13 vcca_dac rsv rsv vcca_dac vcca_dac vcca_dac e13 vcca_dplla vcca_dplla vcca_dplla v cca_dplla vcca_dplla vcca_dplla a12 vcca_dpllb vcca_dpllb vcca_dpllb v cca_dpllb vcca_dpllb vcca_dpllb b13 vcca_exppll vcca_exppl l vcca_exppl l vcca_exppl l vcca_exppll vcca_exppll a14 ballout and package information r 384 datasheet intel ? 82915GL gmch 6 intel ? 82915pl mch 5 intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 intel ? 82910gl gmch 4 ball # vcca_hpll vcca_hpll vcca_hpll v cca_hpll vcca_hpll vcca_hpll a17 vcca_smpll vcca_smpll vcca_smpll v cca_smpll vcca_smpll vcca_smpll b17 vccsm vccsm vccsm vccsm vccsm vccsm ak35 vccsm vccsm vccsm vccsm vccsm vccsm am10 vccsm vccsm vccsm vccsm vccsm vccsm am11 vccsm vccsm vccsm vccsm vccsm vccsm am13 vccsm vccsm vccsm vccsm vccsm vccsm am14 vccsm vccsm vccsm vccsm vccsm vccsm am16 vccsm vccsm vccsm vccsm vccsm vccsm am17 vccsm vccsm vccsm vccsm vccsm vccsm am19 vccsm vccsm vccsm vccsm vccsm vccsm am20 vccsm vccsm vccsm vccsm vccsm vccsm am22 vccsm vccsm vccsm vccsm vccsm vccsm am23 vccsm vccsm vccsm vccsm vccsm vccsm am25 vccsm vccsm vccsm vccsm vccsm vccsm am26 vccsm vccsm vccsm vccsm vccsm vccsm am28 vccsm vccsm vccsm vccsm vccsm vccsm am32 vccsm vccsm vccsm vccsm vccsm vccsm an35 vccsm vccsm vccsm vccsm vccsm vccsm ap12 vccsm vccsm vccsm vccsm vccsm vccsm ap16 vccsm vccsm vccsm vccsm vccsm vccsm ap20 vccsm vccsm vccsm vccsm vccsm vccsm ap24 vccsm vccsm vccsm vccsm vccsm vccsm ap28 vccsm vccsm vccsm vccsm vccsm vccsm ar10 vccsm vccsm vccsm vccsm vccsm vccsm ar14 vccsm vccsm vccsm vccsm vccsm vccsm ar18 vccsm vccsm vccsm vccsm vccsm vccsm ar22 vccsm vccsm vccsm vccsm vccsm vccsm ar26 vccsm vccsm vccsm vccsm vccsm vccsm ar31 vccsm vccsm vccsm vccsm vccsm vccsm ar33 vss vss vss vss vss vss a10 vss vss vss vss vss vss a18 vss vss vss vss vss vss a26 vss vss vss vss vss vss a3 vss vss vss vss vss vss a30 vss vss vss vss vss vss a33 vss vss vss vss vss vss a5 vss vss vss vss vss vss aa1 vss vss vss vss vss vss aa10 vss vss vss vss vss vss aa11 ballout and package information r datasheet 385 intel ? 82915GL gmch 6 intel ? 82915pl mch 5 intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 intel ? 82910gl gmch 4 ball # vss vss vss vss vss vss aa15 vss vss vss vss vss vss aa17 vss vss vss vss vss vss aa19 vss vss vss vss vss vss aa2 vss vss vss vss vss vss aa25 vss vss vss vss vss vss aa26 vss vss vss vss vss vss aa27 vss vss vss vss vss vss aa3 vss vss vss vss vss vss aa4 vss vss vss vss vss vss aa5 vss vss vss vss vss vss aa6 vss vss vss vss vss vss aa7 vss vss vss vss vss vss aa8 vss vss vss vss vss vss aa9 vss vss vss vss vss vss ab25 vss vss vss vss vss vss ab28 vss vss vss vss vss vss ab30 vss vss vss vss vss vss ab32 vss vss vss vss vss vss ab35 vss vss vss vss vss vss ac25 vss vss vss vss vss vss ac27 vss vss vss vss vss vss ac29 vss vss vss vss vss vss ac31 vss vss vss vss vss vss ac32 vss vss vss vss vss vss ad11 vss vss vss vss vss vss ad13 vss vss vss vss vss vss ad16 vss vss vss vss vss vss ad19 vss vss vss vss vss vss ad22 vss vss vss vss vss vss ad25 vss vss vss vss vss vss ad26 vss vss vss vss vss vss ad27 vss vss vss vss vss vss ad34 vss vss vss vss vss vss ae12 vss vss vss vss vss vss ae14 vss vss vss vss vss vss ae15 vss vss vss vss vss vss ae17 vss vss vss vss vss vss ae18 vss vss vss vss vss vss ae20 vss vss vss vss vss vss ae21 ballout and package information r 386 datasheet intel ? 82915GL gmch 6 intel ? 82915pl mch 5 intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 intel ? 82910gl gmch 4 ball # vss vss vss vss vss vss ae23 vss vss vss vss vss vss ae24 vss vss vss vss vss vss ae28 vss vss vss vss vss vss ae30 vss vss vss vss vss vss ae32 vss vss vss vss vss vss ae4 vss vss vss vss vss vss ae6 vss vss vss vss vss vss ae9 vss vss vss vss vss vss af1 vss vss vss vss vss vss af10 vss vss vss vss vss vss af12 vss vss vss vss vss vss af15 vss vss vss vss vss vss af18 vss vss vss vss vss vss af21 vss vss vss vss vss vss af26 vss vss vss vss vss vss af29 vss vss vss vss vss vss af30 vss vss vss vss vss vss af31 vss vss vss vss vss vss af32 vss vss vss vss vss vss af35 vss vss vss vss vss vss af4 vss vss vss vss vss vss af6 vss vss vss vss vss vss af8 vss vss vss vss vss vss ag12 vss vss vss vss vss vss ag13 vss vss vss vss vss vss ag15 vss vss vss vss vss vss ag16 vss vss vss vss vss vss ag18 vss vss vss vss vss vss ag19 vss vss vss vss vss vss ag21 vss vss vss vss vss vss ag22 vss vss vss vss vss vss ag25 vss vss vss vss vss vss ag28 vss vss vss vss vss vss ag29 vss vss vss vss vss vss ag5 vss vss vss vss vss vss ah1 vss vss vss vss vss vss ah11 vss vss vss vss vss vss ah14 vss vss vss vss vss vss ah17 vss vss vss vss vss vss ah20 ballout and package information r datasheet 387 intel ? 82915GL gmch 6 intel ? 82915pl mch 5 intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 intel ? 82910gl gmch 4 ball # vss vss vss vss vss vss ah23 vss vss vss vss vss vss ah26 vss vss vss vss vss vss ah29 vss vss vss vss vss vss ah32 vss vss vss vss vss vss ah34 vss vss vss vss vss vss ah5 vss vss vss vss vss vss ah6 vss vss vss vss vss vss ah8 vss vss vss vss vss vss aj10 vss vss vss vss vss vss aj13 vss vss vss vss vss vss aj15 vss vss vss vss vss vss aj16 vss vss vss vss vss vss aj19 vss vss vss vss vss vss aj22 vss vss vss vss vss vss aj27 vss vss vss vss vss vss aj30 vss vss vss vss vss vss aj32 vss vss vss vss vss vss aj35 vss vss vss vss vss vss aj4 vss vss vss vss vss vss aj9 vss vss vss vss vss vss ak1 vss vss vss vss vss vss ak11 vss vss vss vss vss vss ak14 vss vss vss vss vss vss ak17 vss vss vss vss vss vss ak20 vss vss vss vss vss vss ak23 vss vss vss vss vss vss ak25 vss vss vss vss vss vss ak26 vss vss vss vss vss vss ak28 vss vss vss vss vss vss ak30 vss vss vss vss vss vss ak4 vss vss vss vss vss vss ak6 vss vss vss vss vss vss ak7 vss vss vss vss vss vss ak8 vss vss vss vss vss vss al10 vss vss vss vss vss vss al13 vss vss vss vss vss vss al16 vss vss vss vss vss vss al19 vss vss vss vss vss vss al22 vss vss vss vss vss vss al32 ballout and package information r 388 datasheet intel ? 82915GL gmch 6 intel ? 82915pl mch 5 intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 intel ? 82910gl gmch 4 ball # vss vss vss vss vss vss am29 vss vss vss vss vss vss am31 vss vss vss vss vss vss am4 vss vss vss vss vss vss am6 vss vss vss vss vss vss am7 vss vss vss vss vss vss am8 vss vss vss vss vss vss an1 vss vss vss vss vss vss ap8 vss vss vss vss vss vss ar13 vss vss vss vss vss vss ar17 vss vss vss vss vss vss ar21 vss vss vss vss vss vss ar25 vss vss vss vss vss vss ar3 vss vss vss vss vss vss ar30 vss vss vss vss vss vss ar6 vss vss vss vss vss vss b10 vss vss vss vss vss vss b12 vss vss vss vss vss vss b14 vss vss vss vss vss vss b16 vss vss vss vss vss vss b18 vss vss vss vss vss vss b2 vss vss vss vss vss vss b24 vss vss vss vss vss vss b28 vss vss vss vss vss vss b5 vss vss vss vss vss vss b6 vss vss vss vss vss vss b7 vss vss vss vss vss vss b8 vss vss vss vss vss vss b9 vss vss vss vss vss vss c1 vss vss vss vss vss vss c11 vss vss vss vss vss vss c13 vss vss vss vss vss vss c17 vss vss vss vss vss vss c18 vss vss vss vss vss vss c23 vss vss vss vss vss vss c3 vss vss vss vss vss vss c35 vss vss vss vss vss vss c4 vss vss vss vss vss vss d10 vss vss vss vss vss vss d11 vss vss vss vss vss vss d15 ballout and package information r datasheet 389 intel ? 82915GL gmch 6 intel ? 82915pl mch 5 intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 intel ? 82910gl gmch 4 ball # vss vss vss vss vss vss d16 vss vss vss vss vss vss d18 vss vss vss vss vss vss d23 vss vss vss vss vss vss d25 vss vss vss vss vss vss d26 vss vss vss vss vss vss d28 vss vss vss vss vss vss d3 vss vss vss vss vss vss d30 vss vss vss vss vss vss d31 vss vss vss vss vss vss d32 vss vss vss vss vss vss d4 vss vss vss vss vss vss d6 vss vss vss vss vss vss d7 vss vss vss vss vss vss d8 vss vss vss vss vss vss d9 vss vss vss vss vss vss e1 vss vss vss vss vss vss e10 vss vss vss vss vss vss e17 vss vss vss vss vss vss e18 vss vss vss vss vss vss e2 vss vss vss vss vss vss e23 vss vss vss vss vss vss e26 vss vss vss vss vss vss e29 vss vss vss vss vss vss e4 vss vss vss vss vss vss e6 vss vss vss vss vss vss e8 vss vss vss vss vss vss f10 vss vss vss vss vss vss f16 vss vss vss vss vss vss f18 vss vss vss vss vss vss f2 vss vss vss vss vss vss f23 vss vss vss vss vss vss f25 vss vss vss vss vss vss f29 vss vss vss vss vss vss f30 vss vss vss vss vss vss f32 vss vss vss vss vss vss f35 vss vss vss vss vss vss f4 vss vss vss vss vss vss f5 vss vss vss vss vss vss f6 vss vss vss vss vss vss f8 ballout and package information r 390 datasheet intel ? 82915GL gmch 6 intel ? 82915pl mch 5 intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 intel ? 82910gl gmch 4 ball # vss vss vss vss vss vss g10 vss vss vss vss vss vss g11 vss vss vss vss vss vss g13 vss vss vss vss vss vss g15 vss vss vss vss vss vss g17 vss vss vss vss vss vss g19 vss vss vss vss vss vss g2 vss vss vss vss vss vss g20 vss vss vss vss vss vss g23 vss vss vss vss vss vss g26 vss vss vss vss vss vss g27 vss vss vss vss vss vss g28 vss vss vss vss vss vss g4 vss vss vss vss vss vss g7 vss vss vss vss vss vss g8 vss vss vss vss vss vss g9 vss vss vss vss vss vss h10 vss vss vss vss vss vss h13 vss vss vss vss vss vss h2 vss vss vss vss vss vss h21 vss vss vss vss vss vss h24 vss vss vss vss vss vss h25 vss vss vss vss vss vss h27 vss vss vss vss vss vss h30 vss vss vss vss vss vss h32 vss vss vss vss vss vss h34 vss vss vss vss vss vss h4 vss vss vss vss vss vss h5 vss vss vss vss vss vss h6 vss vss vss vss vss vss h9 vss vss vss vss vss vss j10 vss vss vss vss vss vss j15 vss vss vss vss vss vss j16 vss vss vss vss vss vss j17 vss vss vss vss vss vss j18 vss vss vss vss vss vss j2 vss vss vss vss vss vss j20 vss vss vss vss vss vss j23 vss vss vss vss vss vss j30 vss vss vss vss vss vss j4 ballout and package information r datasheet 391 intel ? 82915GL gmch 6 intel ? 82915pl mch 5 intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 intel ? 82910gl gmch 4 ball # vss vss vss vss vss vss j7 vss vss vss vss vss vss j8 vss vss vss vss vss vss j9 vss vss vss vss vss vss k10 vss vss vss vss vss vss k11 vss vss vss vss vss vss k14 vss vss vss vss vss vss k2 vss vss vss vss vss vss k20 vss vss vss vss vss vss k24 vss vss vss vss vss vss k26 vss vss vss vss vss vss k28 vss vss vss vss vss vss k31 vss vss vss vss vss vss k32 vss vss vss vss vss vss k35 vss vss vss vss vss vss k4 vss vss vss vss vss vss k5 vss vss vss vss vss vss k6 vss vss vss vss vss vss k9 vss vss vss vss vss vss l11 vss vss vss vss vss vss l13 vss vss vss vss vss vss l15 vss vss vss vss vss vss l16 vss vss vss vss vss vss l17 vss vss vss vss vss vss l18 vss vss vss vss vss vss l2 vss vss vss vss vss vss l20 vss vss vss vss vss vss l21 vss vss vss vss vss vss l22 vss vss vss vss vss vss l24 vss vss vss vss vss vss l27 vss vss vss vss vss vss l30 vss vss vss vss vss vss l32 vss vss vss vss vss vss l4 vss vss vss vss vss vss l7 vss vss vss vss vss vss l8 vss vss vss vss vss vss l9 vss vss vss vss vss vss m10 vss vss vss vss vss vss m11 vss vss vss vss vss vss m17 vss vss vss vss vss vss m2 ballout and package information r 392 datasheet intel ? 82915GL gmch 6 intel ? 82915pl mch 5 intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 intel ? 82910gl gmch 4 ball # vss vss vss vss vss vss m20 vss vss vss vss vss vss m24 vss vss vss vss vss vss m25 vss vss vss vss vss vss m27 vss vss vss vss vss vss m29 vss vss vss vss vss vss m34 vss vss vss vss vss vss m4 vss vss vss vss vss vss m5 vss vss vss vss vss vss m6 vss vss vss vss vss vss m9 vss vss vss vss vss vss n10 vss vss vss vss vss vss n11 vss vss vss vss vss vss n17 vss vss vss vss vss vss n19 vss vss vss vss vss vss n2 vss vss vss vss vss vss n25 vss vss vss vss vss vss n28 vss vss vss vss vss vss n30 vss vss vss vss vss vss n32 vss vss vss vss vss vss n4 vss vss vss vss vss vss n7 vss vss vss vss vss vss n8 vss vss vss vss vss vss n9 vss vss vss vss vss vss p11 vss vss vss vss vss vss p16 vss vss vss vss vss vss p18 vss vss vss vss vss vss p2 vss vss vss vss vss vss p20 vss vss vss vss vss vss p25 vss vss vss vss vss vss p27 vss vss vss vss vss vss p29 vss vss vss vss vss vss p31 vss vss vss vss vss vss p32 vss vss vss vss vss vss p35 vss vss vss vss vss vss p4 vss vss vss vss vss vss p5 vss vss vss vss vss vss p6 vss vss vss vss vss vss p9 vss vss vss vss vss vss r11 vss vss vss vss vss vss r17 ballout and package information r datasheet 393 intel ? 82915GL gmch 6 intel ? 82915pl mch 5 intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 intel ? 82910gl gmch 4 ball # vss vss vss vss vss vss r19 vss vss vss vss vss vss r2 vss vss vss vss vss vss r21 vss vss vss vss vss vss r25 vss vss vss vss vss vss r26 vss vss vss vss vss vss r27 vss vss vss vss vss vss r4 vss vss vss vss vss vss r7 vss vss vss vss vss vss r8 vss vss vss vss vss vss r9 vss vss vss vss vss vss t10 vss vss vss vss vss vss t11 vss vss vss vss vss vss t18 vss vss vss vss vss vss t2 vss vss vss vss vss vss t22 vss vss vss vss vss vss t25 vss vss vss vss vss vss t28 vss vss vss vss vss vss t30 vss vss vss vss vss vss t32 vss vss vss vss vss vss t34 vss vss vss vss vss vss t4 vss vss vss vss vss vss t5 vss vss vss vss vss vss t6 vss vss vss vss vss vss t7 vss vss vss vss vss vss u11 vss vss vss vss vss vss u15 vss vss vss vss vss vss u17 vss vss vss vss vss vss u19 vss vss vss vss vss vss u2 vss vss vss vss vss vss u21 vss vss vss vss vss vss u23 vss vss vss vss vss vss u25 vss vss vss vss vss vss u27 vss vss vss vss vss vss u29 vss vss vss vss vss vss u31 vss vss vss vss vss vss u32 vss vss vss vss vss vss u4 vss vss vss vss vss vss u7 vss vss vss vss vss vss u8 vss vss vss vss vss vss u9 ballout and package information r 394 datasheet intel ? 82915GL gmch 6 intel ? 82915pl mch 5 intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 intel ? 82910gl gmch 4 ball # vss vss vss vss vss vss v1 vss vss vss vss vss vss v11 vss vss vss vss vss vss v16 vss vss vss vss vss vss v18 vss vss vss vss vss vss v2 vss vss vss vss vss vss v20 vss vss vss vss vss vss v22 vss vss vss vss vss vss v25 vss vss vss vss vss vss v26 vss vss vss vss vss vss v27 vss vss vss vss vss vss v35 vss vss vss vss vss vss v4 vss vss vss vss vss vss v6 vss vss vss vss vss vss v9 vss vss vss vss vss vss w11 vss vss vss vss vss vss w15 vss vss vss vss vss vss w17 vss vss vss vss vss vss w19 vss vss vss vss vss vss w21 vss vss vss vss vss vss w23 vss vss vss vss vss vss w25 vss vss vss vss vss vss w28 vss vss vss vss vss vss w30 vss vss vss vss vss vss w32 vss vss vss vss vss vss y11 vss vss vss vss vss vss y18 vss vss vss vss vss vss y22 vss vss vss vss vss vss y25 vss vss vss vss vss vss y27 vss vss vss vss vss vss y29 vss vss vss vss vss vss y31 vss vss vss vss vss vss y32 vss vss vss vss vss vss y34 vssa_dac rsv rsv vssa_dac vssa_dac vssa_dac f13 vsync vsync vsync vsync vsync vsync d12 vtt vtt vtt vtt vtt vtt a19 vtt vtt vtt vtt vtt vtt a20 vtt vtt vtt vtt vtt vtt a21 vtt vtt vtt vtt vtt vtt a22 vtt vtt vtt vtt vtt vtt b19 ballout and package information r datasheet 395 intel ? 82915GL gmch 6 intel ? 82915pl mch 5 intel ? 82915p mch 1 intel ? 82915g gmch 2 intel ? 82915gv gmch 3 intel ? 82910gl gmch 4 ball # vtt vtt vtt vtt vtt vtt b20 vtt vtt vtt vtt vtt vtt b21 vtt vtt vtt vtt vtt vtt b22 vtt vtt vtt vtt vtt vtt c19 vtt vtt vtt vtt vtt vtt c20 vtt vtt vtt vtt vtt vtt c21 vtt vtt vtt vtt vtt vtt c22 vtt vtt vtt vtt vtt vtt d19 vtt vtt vtt vtt vtt vtt d20 vtt vtt vtt vtt vtt vtt d21 vtt vtt vtt vtt vtt vtt d22 vtt vtt vtt vtt vtt vtt e19 vtt vtt vtt vtt vtt vtt e20 vtt vtt vtt vtt vtt vtt e21 vtt vtt vtt vtt vtt vtt e22 vtt vtt vtt vtt vtt vtt f20 vtt vtt vtt vtt vtt vtt f21 vtt vtt vtt vtt vtt vtt f22 vtt vtt vtt vtt vtt vtt g21 vtt vtt vtt vtt vtt vtt g22 vtt vtt vtt vtt vtt vtt h22 notes: 1. ddr, pci express* x16 graphics interface, no dac, no intel ? sdvo 2. ddr, pci express* x16 graphics interface, dac, intel ? sdvo 3. ddr, no pci express* x16 graphics interface, dac, intel ? sdvo 4. ddr (one dimm per channel), no pci expre ss* x16 graphics interface, dac, intel ? sdvo 5. ddr (one dimm per channel), pci express* x 16 graphics interface, no dac, no intel ? sdvo 6. ddr, no pci express* x16 graphics interface, dac, intel ? sdvo 14.3 package information the (g)mch package measures 37.5 mm 37.5 mm. the 1210 balls are located in a non-grid pattern. for example, the ball pitch varies from 31.8 mils to 43.0 mils, depending upon the x-axis or y-axis direction. figure 14-7 shows the physical dimensions of the package and figure 14-8 shows the (g)mch keep-out regions. ballout and package information r 396 datasheet figure 14-7. (g)mch package dimensions (g)mch ballout and package information r datasheet 397 figure 14-8. (g)mch component keep-out restrictions ballout and package information r 398 datasheet testability r datasheet 399 15 testability in the (g)mch, testability for automated test equipment (ate) board level testing has been implemented as an xor chain. an xor-tree is a chain of xor gates each with one input pin connected to it. 15.1 complimentary pins table 15-1 contains pins which must remain complimentary while performing xor testing. the first and third columns contain the pin and its compliment. the second and fourth columns specify which chain the a ssociated pins are on. note: the sdqsx# pins are only used in ddr2 mode. in ddr it is not necessary to drive sdqs_a[7:0]# or sdqs_b[7:0]#. table 15-1. complimentary pins to drive complimentary pin xor chain complimentary pin xor chain hdstbp0# fsb xor 1 h_dstbn0# fsb xor 1 hdstbp1# fsb xor 0 hdstbn1# fsb xor 0 hdstbp2# fsb xor 0 hdstbn2# fsb xor 0 hdstbp3# fsb xor 0 hdstbn3# fsb xor 0 sdqs_a0 sm xor 6 sdqs_a0# sm xor 4 sdqs_a1 sm xor 6 sdqs_a1# sm xor 4 sdqs_a2 sm xor 6 sdqs_a2# sm xor 4 sdqs_a3 sm xor 4 sdqs_a3# sm xor 6 sdqs_a4 sm xor 4 sdqs_a4 sm xor 2 sdqs_a5 sm xor 2 sdqs_a5# sm xor 4 sdqs_a6 sm xor 2 sdqs_a6# sm xor 4 sdqs_a7 sm xor 2 sdqs_a7# sm xor 4 sdqs_a8 sm xor 2 sdqs_a8# sm xor 4 sdqs_b0 sm xor 7 sdqs_b0# sm xor 5 sdqs_b1 sm xor 7 sdqs_b1# sm xor 5 sdqs_b2 sm xor 7 sdqs_b2# sm xor 5 sdqs_b3 sm xor 7 sdqs_b3# sm xor 5 sdqs_b4 sm xor 7 sdqs_b4# sm xor 5 sdqs_b5 sm xor 3 sdqs_b5# sm xor 5 sdqs_b6 sm xor 3 sdqs_b6# sm xor 5 sdqs_b7 sm xor 3 sdqs_b7# sm xor 5 sdqs_b8 sm xor 7 sdqs_b8# sm xor 5 testability r 400 datasheet 15.2 xor test mode initialization for ddr xor test mode (ddr) can be entered by pulling the reserved ballout rsv (located at f15) low through the de-assertion of external reset (rstin #). it was intended that no clocks should be required to enter this test mode; however, it is recommended that customers used the following sequence. on power up, hold pwrok, pcirst#, and reserved ballout rsv (located at f15) low and start external clocks, refer to the timing diagram below. after a few clock cycles, pull pwrok high. after ~3?4 clocks, de-assert pcirst# (pull it high). release reserved ballout rsv (located at f15). no external drive. allow the clocks to run for an additional 32 clocks. begin testing the xor chains. refer to timing diagram in below. 15.3 xor test mode initialization for ddr2 xor test mode (ddr2) can be entered by pulling reserved ballout rsv(located at f15) and mtype low through the de-assertion of external re set (rstin#). it was intended that no clocks should be required to enter this test mode; however, it is recommended that customers use the following sequence. on power up, hold pwrok, pcirst#, and reserved ballout rsv (located at f15) low and start external clocks. after a few clock cycles, pull pwrok high. after ~3-4 clocks, de-assert pcirst# (pull it high). release reserved ballout rsv (located at f15) and mtype. no external drive. allow the clocks to run for an additional 32 clocks. begin testing the xor chains. refer to figure 15-1. figure 15-1. xor test mode initialization cycles pwrok rsv_f15 mtype don?t care don?t care rstin# 1 if ddr1; 0 if ddr2 ~3-4 clocks 32 clocks start xor testing xor_chain_tim testability r datasheet 401 15.4 xor chain definition the 82915g/82915gv/82915GL/82910gl gmch, a nd the 82915p/ 82915pl mch each have 10 xor chains. the xor chain outputs are driven out on the following output pins. during full- width testing, xor chain outputs are visible on both pins. for example, xor_out0 is visible on bsel2. table 15-2. xor chain outputs for both ddr and ddr2 xor chain output pins coordinate location xor_out0 bsel2 d17 xor_out1 rsv m16 xor_out2 rsv f15 xor_out3 mtype c15 xor_out4 exp_slr a16 xor_out5 rsv b15 xor_out6 rsv c14 xor_out7 rsv k15 xor_out8 bsel0 h16 xor_out9 bsel1 e15 15.5 ddr xor chains the tables in this section show the ddr xor chains. the last section in this chapter has a pin exclusion list. the chain files are golden, if there is a pin missing from the chain files and exclusion list, it should be added to the exclusion list. note: the ddr xor chain information is based on the 82915g gmch. differences for the 82915gv/82915GL/82910gl gmch and 82915p/82915pl mch are indicated in the ?comments? column. testability r 402 datasheet table 15-3. ddr xor chain #0 pin count ball # ddr signal name comments 1 m15 ddc_clk rsv on the 82915p/82915pl mch 2 m14 ich_sync# 3 k16 extts# 4 l14 ddc_data rsv on the 82915p/82915pl mch 5 k13 sdvo_ctrldata rsv on the 82915p/82915pl mch 6 j13 sdvo_ctrlclk rsv on the 82915p/82915pl mch 7 g16 rsv 8 g24 hcpurst# 9 k17 hd44 10 m18 hd42 11 k18 hd43 12 f17 hd47 13 m19 hd38 14 k21 hd39 15 k19 hdinv2# 16 h18 hd46 17 j19 hdstbp2# 18 f19 hdstbn2# 19 g18 hd45 20 k22 hd34 21 m21 hd36 22 j21 hd35 23 h20 hd40 24 h19 hd41 25 j24 hd33 26 j22 hd32 27 h23 hd37 28 a25 hd48 29 a29 hd55 30 d27 hd60 31 b26 hdinv3# 32 b29 hdstbp3# 33 c29 hdstbn3# 34 c25 hd58 35 b30 hd51 36 e27 hd24 37 c30 hd17 38 e25 hd25 39 h28 hd19 40 f27 hd23 41 f28 hd22 42 h26 hdstbp1# testability r datasheet 403 pin count ball # ddr signal name comments 43 f26 hdstbn1# 44 j27 hd21 45 j25 hd27 46 k25 hd28 47 k23 hd31 48 l23 hd30 49 j26 hdinv1# 50 g25 hd26 51 l25 hd29 52 b32 hd15 53 g33 hd7 54 h33 hd1 55 h35 hd4 56 j34 hd2 57 g30 ha6# 58 h29 ha3# 59 j28 ha13# 60 j29 ha5# 61 k33 ha15# 62 f31 hreq4# 63 k29 ha4# 64 l31 ha11# 65 k27 ha14# 66 m30 ha10# 67 f33 hreq0# 68 e30 hbpri# 69 j35 hdefer# 70 p33 hedrdy# d17 bsel2 xor chain #0 output testability r 404 datasheet table 15-4. ddr xor chain #1 pin count ball # ddr signal name comments 1 a28 hd57 2 a27 hd61 3 b27 hd54 4 b25 hd63 5 e24 hd62 6 c26 hd59 7 c27 hd49 8 c28 hd56 9 a31 hd53 10 c31 hd50 11 b31 hd52 12 d29 hd18 13 e28 hd16 14 g29 hd20 15 b34 hd11 16 b33 hd13 17 c32 hd14 18 c33 hd9 19 c34 hd12 20 d34 hd8 21 d33 hd10 22 e34 hdinv0# 23 e33 hdstbp0# 24 e35 hdstbn0# 25 f34 hd6 26 g34 hd5 27 g35 hd3 28 j33 hd0 29 g32 ha7# 30 h31 hreq2# 31 k30 ha8# 32 j31 hadstb0# 33 g31 hreq3# 34 e31 hpcreq# 35 l29 ha9# 36 l28 ha12# 37 j32 hrs2# 38 k34 hrs0# 39 l33 hlock# 40 m32 hdrdy# 41 m31 hads# 42 l34 hhit# 43 m35 hbnr# 44 l35 hdbsy# 45 n35 hhitm# testability r datasheet 405 pin count ball # ddr signal name comments 46 p34 hrs1# 47 n34 htrdy# 48 r33 hbreq0# 49 n31 ha21# 50 n33 ha26# 51 t31 ha28# 52 e32 hreq1# 53 t27 ha27# 54 m26 ha20# 55 n26 ha19# 56 p28 ha24# 57 u28 ha29# 58 n27 hadstb1# 59 l26 ha18# 60 m28 ha16# 61 t29 ha31# 62 r28 ha25# 63 n29 ha23# 64 t26 ha30# 65 p26 ha22# 66 r29 ha17# m16 rsv xor chain #1 output testability r 406 datasheet table 15-5. ddr xor chain #2 pin count ball # ddr signal name comments 1 r32 sdq_a58 2 r34 sdq_a59 3 t35 sdq_a63 4 w35 sdq_a60 5 t33 sdq_a62 6 v34 sdq_a56 7 v33 sdq_a57 8 u33 sdm_a7 9 w33 sdq_a61 10 u34 sdqs_a7 11 aa34 sdqs_a6 12 w34 sdq_a51 13 y35 sdq_a55 14 y33 sdq_a50 15 ad35 sdq_a53 16 ae35 sdq_a48 17 ae34 sdq_a49 18 aa33 sdm_a6 19 aa32 sdq_a54 20 ad31 sdq_a52 21 ab33 sma_a13 22 ac35 sclk_a5 23 ab34 sclk_a2 24 ac33 sclk_a2# 25 af34 sdq_a43 26 ah35 sdq_a41 27 aj34 sdq_a40 28 ag34 sdm_a5 29 ae33 sdq_a47 30 af33 sdq_a46 31 ag32 sdq_a42 32 ah33 sdq_a45 33 aj33 sdq_a44 34 ag35 sdqs_a5 35 ar29 rsv 36 ap33 rsv 37 ap29 rsv 38 an32 rsv 39 ap30 rsv 40 al29 rsv f15 rsv xor chain #2 output testability r datasheet 407 table 15-6. ddr xor chain #3 pin count ball # ddr signal name comments 1 w26 sdq_b62 2 u26 sdq_b58 3 v28 sdq_b63 4 v29 sdq_b59 5 w29 sdq_b57 6 w31 sdm_b7 7 aa29 sdq_b56 8 aa28 sdq_b61 9 y26 sdq_b60 10 w27 sdqs_b7 11 ad32 sma_b13 12 ab31 sdqs_b6 13 ab27 sdq_b50 14 ae31 sdq_b48 15 ac26 sdq_b55 16 ae27 sdq_b53 17 ae29 sdq_b52 18 af27 sdq_b49 19 ab26 sdq_b51 20 ac28 sdq_b54 21 ad24 sdm_b6 22 ap34 scs_b0# 23 ad29 sclk_b5 24 ae25 sclk_b2# 25 ae26 sclk_b2 26 an34 scs_b1# 27 an33 scs_b2# 28 am34 scs_a0# 29 ak34 scs_a2# 30 al34 scas_a# 31 al35 scs_a1# 32 am33 scs_b3# 33 af28 sdq_b47 34 ak32 sdq_b45 35 ah31 sdm_b5 36 ak33 sdq_b44 37 aj31 sdq_b41 38 ag27 sdq_b46 39 aj29 sdq_b40 40 ag31 sdq_b43 41 ah28 sdqs_b5 42 al33 scs_a3# 43 aj25 sdq_b38 44 al25 sdq_b34 45 aj26 sdq_b35 46 al26 sdq_b39 47 af23 sdq_b32 48 af25 sdq_b33 c15 mtype xor chain #3 output testability r 408 datasheet table 15-7. ddr xor chain #4 pin count ball # ddr signal name comments 1 u35 rsv 2 aa35 rsv 3 ac34 sclk_a5# 4 ag33 rsv 5 ap32 rsv 6 an31 rsv 7 am30 sdqs_a4 8 ak31 sdq_a35 9 ah27 sdq_a32 10 ak29 sdm_a4 11 aj28 sdq_a37 12 al30 sdq_a38 13 al31 sdq_a39 14 an30 sdq_a34 15 al27 sdq_a36 16 ak27 sdq_a33 17 an29 sras_a# 18 an28 sbs_a0 19 ar28 rsv 20 an27 scas_b# 21 ap27 sras_b# 22 ar27 swe_b# 23 ap25 sclk_a3 24 an26 sclk_a3# 25 an25 sclk_a0# 26 am24 sclk_a0 27 al24 rsv 28 am27 sbs_b0 29 ap26 sbs_a1 30 ap31 swe_a# 31 ar24 rsv 32 ar23 rsv 33 ap23 rsv 34 an23 sma_a10 35 an22 sma_a0 36 af17 sdqs_a3 37 ah18 sdq_a31 38 af19 sdq_a27 39 aj17 sdq_a29 40 al17 sdq_a25 41 af16 sdq_a28 42 an18 sma_a8 43 ar7 rsv 44 am3 sclk_a4# 45 al2 rsv 46 ag2 rsv a16 exp_slr xor chain #4 output testability r datasheet 409 table 15-8. ddr xor chain #5 pin count ball # ddr signal name comments 1 y28 rsv 2 ac30 rsv 3 ad28 sclk_b5# 4 ag30 sdq_b42 5 ah30 rsv 6 ag24 sdm_b4 7 ad23 sdq_b36 8 af24 sdq_b37 9 ag26 rsv 10 af20 rsv 11 ae22 sdq_b26 12 al18 sdq_b28 13 ak19 sdq_b25 14 ag20 sdm_b3 15 ad21 sdq_b31 16 af22 sdq_b30 17 ah21 sdq_b27 18 ad18 sdq_b24 19 ah19 sdq_b29 20 ak22 sclk_b3# 21 ag23 sclk_b0# 22 ah22 sclk_b0 23 an17 sma_b2 24 ap18 sma_b1 25 ap17 sma_b6 26 ar16 sma_b3 27 an16 sma_a7 28 an15 sma_b5 29 am15 sma_a9 30 ap15 sma_a11 31 ar15 sma_b4 32 al15 sma_b7 33 ap14 sma_b8 34 ap10 scke_b2 35 al14 rsv 36 al9 sclk_b4# 37 ah10 rsv 38 al4 rsv b15 rsv xor chain #5 output testability r 410 datasheet table 15-9. ddr xor chain #6 pin count ball # ddr signal name comments 1 ag17 rsv 2 ah16 sdm_a3 3 ae19 sdq_a30 4 ad17 sdq_a26 5 ak16 sdq_a24 6 am18 sma_b0 7 am21 sma_a4 8 an21 sma_a2 9 ap22 sma_a1 10 an20 sma_b10 11 ap21 sma_a3 12 ar20 sma_a6 13 ap19 sma_a5 14 ar19 sbs_b1 15 ap7 sdqs_a2 16 ap9 sdq_a19 17 an9 sdq_a23 18 ar8 sdq_a22 19 an8 sdq_a18 20 an7 sdm_a2 21 ap6 sdq_a21 22 ar5 sdq_a17 23 ap5 sdq_a16 24 an5 sdq_a20 25 an2 sclk_a1 26 an3 sclk_a1# 27 am2 sclk_a4 28 ap4 sdq_a11 29 ap3 sdq_a15 30 ap2 sdq_a14 31 an4 sdq_a10 32 ak3 sdq_a13 33 ak2 sdq_a9 34 aj3 sdq_a12 35 aj1 sdq_a8 36 al1 sdm_a1 37 al3 sdqs_a1 38 ag1 sdqs_a0 39 ag3 sdq_a6 40 af2 sdm_a0 41 ah2 sdq_a2 42 ah3 sdq_a7 43 aj2 sdq_a3 44 af3 sdq_a1 45 ae3 sdq_a0 46 ae2 sdq_a4 47 ae1 sdq_a5 c14 rsv xor chain #6 output testability r datasheet 411 table 15-10. ddr xor chain #7 pin count ball # ddr signal name comments 1 ah25 sdqs_b4 2 ad20 sdqs_b3 3 al23 sclk_b3 4 ap13 sma_a12 5 ar12 sma_b11 6 an13 sma_b9 7 al12 scke_a0 8 ar11 scke_a3 9 ap11 scke_a2 10 an11 scke_a1 11 am12 sma_b12 12 ar9 scke_b3 13 an10 scke_b0 14 am9 scke_b1 15 ad15 sdq_b23 16 ad14 sdq_b19 17 ag14 sdq_b18 18 ah13 sdm_b2 19 ah12 sdq_b21 20 af14 sdq_b22 21 ad12 sdq_b20 22 af13 sdq_b17 23 ae13 sdq_b16 24 ak13 sdqs_b2 25 al11 sclk_b1 26 aj11 sclk_b1# 27 ak9 sclk_b4 28 al8 sdq_b13 29 al7 sdq_b9 30 aj7 sdq_b8 31 aj8 sdq_b12 32 af11 sdq_b10 33 ag11 sdq_b15 34 ag10 sdq_b14 35 ah9 sdm_b1 36 ae11 sdq_b11 37 ak10 sdqs_b1 38 ak5 sdqs_b0 39 ag9 sdq_b4 40 ah7 sdq_b0 41 aj6 sdq_b1 42 al6 sdq_b7 43 an6 sdq_b3 44 al5 sdq_b2 45 aj5 sdm_b0 46 ah4 sdq_b5 47 am5 sdq_b6 k15 rsv xor chain #7 output testability r 412 datasheet table 15-11. ddr xor chain #8 pin count ball # ddr signal name comments 1 f11 exp_rxn0 for sdvo interface signal name, see ballout table. 2 c9 exp_txn0 for sdvo interface signal name, see ballout table. 3 h11 exp_rxn1 for sdvo interface signal name, see ballout table. 4 a8 exp_txn1 for sdvo interface signal name, see ballout table. 5 e9 exp_rxn2 for sdvo interface signal name, see ballout table. 6 c7 exp_txn2 for sdvo interface signal name, see ballout table. 7 e7 exp_rxn3 for sdvo interface signal name, see ballout table. 8 a6 exp_txn3 for sdvo interface signal name, see ballout table. 9 b4 exp_rxn4 for sdvo interface signal name, see ballout table. 10 c5 exp_txn4 for sdvo interface signal name, see ballout table. 11 e5 exp_rxn5 for sdvo interface signal name, see ballout table. 12 d2 exp_txn5 for sdvo interface signal name, see ballout table. 13 g5 exp_rxn6 for sdvo interface signal name, see ballout table. 14 f3 exp_txn6 for sdvo interface signal name, see ballout table. 15 h7 exp_rxn7 for sdvo interface signal name, see ballout table. 16 g1 exp_txn7 for sdvo interface signal name, see ballout table. 17 j5 exp_rxn8 for sdvo interface signal name, see ballout table. 18 h3 exp_txn8 for sdvo interface signal name, see ballout table. 19 k7 exp_rxn9 for sdvo interface signal name, see ballout table. 20 j1 exp_txn9 for sdvo interface signal name, see ballout table. 21 l5 exp_rxn10 for sdvo interface signal name, see ballout table. 22 k3 exp_txn10 for sdvo interface signal name, see ballout table. 23 r10 exp_rxn11 for sdvo interface signal name, see ballout table. 24 l1 exp_txn11 for sdvo interface signal name, see ballout table. 25 m7 exp_rxn12 for sdvo interface signal name, see ballout table. 26 m3 exp_txn12 for sdvo interface signal name, see ballout table. 27 n5 exp_rxn13 for sdvo interface signal name, see ballout table. 28 n1 exp_txn13 for sdvo interface signal name, see ballout table. 29 p8 exp_rxn14 for sdvo interface signal name, see ballout table. 30 p3 exp_txn14 for sdvo interface signal name, see ballout table. 31 r5 exp_rxn15 for sdvo interface signal name, see ballout table. 32 r1 exp_txn15 for sdvo interface signal name, see ballout table. 33 e11 exp_rxp0 for sdvo interface signal name, see ballout table. 34 c10 exp_txp0 for sdvo interface signal name, see ballout table. 35 j11 exp_rxp1 for sdvo interface signal name, see ballout table. 36 a9 exp_txp1 for sdvo interface signal name, see ballout table. 37 f9 exp_rxp2 for sdvo interface signal name, see ballout table. 38 c8 exp_txp2 for sdvo interface signal name, see ballout table. 39 f7 exp_rxp3 for sdvo interface signal name, see ballout table. 40 a7 exp_txp3 for sdvo interface signal name, see ballout table. 41 b3 exp_rxp4 for sdvo interface signal name, see ballout table. 42 c6 exp_txp4 for sdvo interface signal name, see ballout table. 43 d5 exp_rxp5 for sdvo interface signal name, see ballout table. 44 c2 exp_txp5 for sdvo interface signal name, see ballout table. 45 g6 exp_rxp6 for sdvo interface signal name, see ballout table. testability r datasheet 413 pin count ball # ddr signal name comments 46 e3 exp_txp6 for sdvo interface signal name, see ballout table. 47 h8 exp_rxp7 for sdvo interface signal name, see ballout table. 48 f1 exp_txp7 for sdvo interface signal name, see ballout table. 49 j6 exp_rxp8 for sdvo interface signal name, see ballout table. 50 g3 exp_txp8 for sdvo interface signal name, see ballout table. 51 k8 exp_rxp9 for sdvo interface signal name, see ballout table. 52 h1 exp_txp9 for sdvo interface signal name, see ballout table. 53 l6 exp_rxp10 for sdvo interface signal name, see ballout table. 54 j3 exp_txp10 for sdvo interface signal name, see ballout table. 55 p10 exp_rxp11 for sdvo interface signal name, see ballout table. 56 k1 exp_txp11 for sdvo interface signal name, see ballout table. 57 m8 exp_rxp12 for sdvo interface signal name, see ballout table. 58 l3 exp_txp12 for sdvo interface signal name, see ballout table. 59 n6 exp_rxp13 for sdvo interface signal name, see ballout table. 60 m1 exp_txp13 for sdvo interface signal name, see ballout table. 61 p7 exp_rxp14 for sdvo interface signal name, see ballout table. 62 n3 exp_txp14 for sdvo interface signal name, see ballout table. 63 r6 exp_rxp15 for sdvo interface signal name, see ballout table. 64 p1 exp_txp15 for sdvo interface signal name, see ballout table. h16 bsel0 xor chain #8 output table 15-12. ddr xor chain #9 pin count ball # ddr signal name comments 1 u6 dmi_rxn0 2 u5 dmi_rxp0 3 t3 dmi_txn0 4 r3 dmi_txp0 5 t8 dmi_rxn1 6 t9 dmi_rxp1 7 u1 dmi_txn1 8 t1 dmi_txp1 9 v8 dmi_rxn2 10 v7 dmi_rxp2 11 v3 dmi_txn2 12 u3 dmi_txp2 13 u10 dmi_rxn3 14 v10 dmi_rxp3 15 w5 dmi_txn3 16 v5 dmi_txp3 e15 bsel1 xor chain #9 output testability r 414 datasheet 15.6 ddr2 xor chains the tables in this section list all of the pads used in ddr2 xor testing. any pads not listed in the table can be considered part of the exclude list. note: the ddr2 xor chain information is based on the 82915g gmch. differences for the 82915gv gmch and 82915p mch are indicated in the ?comments? column. table 15-13. ddr2 xor chain #0 pin count ball # ddr2 signal name comments 1 m15 ddc_clk rsv on the 82915p 2 m14 ich_sync# 3 k16 extts# 4 l14 ddc_data rsv on the 82915p 5 k13 sdvo_ctrldata rsv on the 82915p 6 j13 sdvo_ctrlclk rsv on the 82915p 7 g16 rsv 8 g24 hcpurst# 9 k17 hd44 10 m18 hd42 11 k18 hd43 12 f17 hd47 13 m19 hd38 14 k21 hd39 15 k19 hdinv2# 16 h18 hd46 17 j19 hdstbp2# 18 f19 hdstbn2# 19 g18 hd45 20 k22 hd34 21 m21 hd36 22 j21 hd35 23 h20 hd40 24 h19 hd41 25 j24 hd33 26 j22 hd32 27 h23 hd37 28 a25 hd48 29 a29 hd55 30 d27 hd60 31 b26 hdinv3# 32 b29 hdstbp3# 33 c29 hdstbn3# 34 c25 hd58 35 b30 hd51 36 e27 hd24 testability r datasheet 415 pin count ball # ddr2 signal name comments 37 c30 hd17 38 e25 hd25 39 h28 hd19 40 f27 hd23 41 f28 hd22 42 h26 hdstbp1# 43 f26 hdstbn1# 44 j27 hd21 45 j25 hd27 46 k25 hd28 47 k23 hd31 48 l23 hd30 49 j26 hdinv1# 50 g25 hd26 51 l25 hd29 52 b32 hd15 53 g33 hd7 54 h33 hd1 55 h35 hd4 56 j34 hd2 57 g30 ha6# 58 h29 ha3# 59 j28 ha13# 60 j29 ha5# 61 k33 ha15# 62 f31 hreq4# 63 k29 ha4# 64 l31 ha11# 65 k27 ha14# 66 m30 ha10# 67 f33 hreq0# 68 e30 hbpri# 69 j35 hdefer# 70 p33 hedrdy# d17 bsel2 xor chain #0 output testability r 416 datasheet table 15-14. ddr2 xor chain #1 pin count ball # ddr2 signal name comments 1 a28 hd57 2 a27 hd61 3 b27 hd54 4 b25 hd63 5 e24 hd62 6 c26 hd59 7 c27 hd49 8 c28 hd56 9 a31 hd53 10 c31 hd50 11 b31 hd52 12 d29 hd18 13 e28 hd16 14 g29 hd20 15 b34 hd11 16 b33 hd13 17 c32 hd14 18 c33 hd9 19 c34 hd12 20 d34 hd8 21 d33 hd10 22 e34 hdinv0# 23 e33 hdstbp0# 24 e35 hdstbn0# 25 f34 hd6 26 g34 hd5 27 g35 hd3 28 j33 hd0 29 g32 ha7# 30 h31 hreq2# 31 k30 ha8# 32 j31 hadstb0# 33 g31 hreq3# 34 e31 hpcreq# 35 l29 ha9# 36 l28 ha12# 37 j32 hrs2# 38 k34 hrs0# 39 l33 hlock# 40 m32 hdrdy# 41 m31 hads# 42 l34 hhit# 43 m35 hbnr# 44 l35 hdbsy# 45 n35 hhitm# testability r datasheet 417 pin count ball # ddr2 signal name comments 46 p34 hrs1# 47 n34 htrdy# 48 r33 hbreq0# 49 n31 ha21# 50 n33 ha26# 51 t31 ha28# 52 e32 hreq1# 53 t27 ha27# 54 m26 ha20# 55 n26 ha19# 56 p28 ha24# 57 u28 ha29# 58 n27 hadstb1# 59 l26 ha18# 60 m28 ha16# 61 t29 ha31# 62 r28 ha25# 63 n29 ha23# 64 t26 ha30# 65 p26 ha22# 66 r29 ha17# m16 rsv xor chain #1 output testability r 418 datasheet table 15-15. ddr2 xor chain #2 pin count ball # ddr2 signal name comments 1 r32 sdq_a58 2 r34 sdq_a59 3 t35 sdq_a63 4 w35 sdq_a60 5 t33 sdq_a62 6 v34 sdq_a56 7 v33 sdq_a57 8 u33 sdm_a7 9 w33 sdq_a61 10 u34 sdqs_a7 11 aa34 sdqs_a6 12 w34 sdq_a51 13 y35 sdq_a55 14 y33 sdq_a50 15 ad35 sdq_a49 16 ae35 sdq_a52 17 ae34 sdq_a53 18 aa33 sdm_a6 19 aa32 sdq_a54 20 ad31 sdq_a48 21 ab33 rsv 22 ac35 sclk_a2# 23 ab34 sclk_a5# 24 ac33 sclk_a5 25 af34 sdq_a47 26 ah35 sdq_a41 27 aj34 sdq_a45 28 ag34 sdm_a5 29 ae33 sdq_a43 30 af33 sdq_a42 31 ag32 sdq_a46 32 ah33 sdq_a40 33 aj33 sdq_a44 34 ag35 sdqs_a5 35 ar29 scs_a0# 36 ap33 sodt_a3 37 ap29 sodt_a2 38 an32 sodt_a1 39 ap30 sodt_a0 40 al29 sdqs_a4# f15 rsv xor chain #2 output testability r datasheet 419 table 15-16. ddr2 xor chain #3 pin count ball # ddr2 signal name comments 1 w26 sdq_b62 2 u26 sdq_b63 3 v28 sdq_b58 4 v29 sdq_b59 5 w29 sdq_b57 6 w31 sdm_b7 7 aa29 sdq_b61 8 aa28 sdq_b56 9 y26 sdq_b60 10 w27 sdqs_b7 11 ad32 rsv 12 ab31 sdqs_b6 13 ab27 sdq_b55 14 ae31 sdq_b52 15 ac26 sdq_b50 16 ae27 sdq_b49 17 ae29 sdq_b53 18 af27 sdq_b48 19 ab26 sdq_b51 20 ac28 sdq_b54 21 ad24 sdm_b6 22 ap34 scs_b2# 23 ad29 sclk_b5# 24 ae25 sclk_b2# 25 ae26 sclk_b2 26 an34 scs_b3# 27 an33 scs_b0# 28 am34 scs_b1# 29 ak34 sodt_b3 30 al34 sodt_b1 31 al35 sodt_b2 32 am33 sodt_b0 33 af28 sdq_b43 34 ak32 sdq_b40 35 ah31 sdm_b5 36 ak33 sdq_b45 37 aj31 sdq_b41 38 ag27 sdq_b47 39 aj29 sdq_b44 40 ag31 sdq_b42 41 ah28 sdqs_b5 42 al33 sma_b13 43 aj25 sdq_b39 44 al25 sdq_b38 45 aj26 sdq_b35 46 al26 sdq_b34 47 af23 sdq_b36 48 af25 sdq_b33 c15 mtype xor chain #3 output testability r 420 datasheet table 15-17. ddr2 xor chain #4 pin count ball # ddr2 signal name comments 1 u35 sdqs_a7# 2 aa35 sdqs_a6# 3 ac34 sclk_a2 4 ag33 sdqs_a5# 5 ap32 scs_a1# 6 an31 scs_a3# 7 am30 sdqs_a4 8 ak31 sdq_a35 9 ah27 sdq_a36 10 ak29 sdm_a4 11 aj28 sdq_a33 12 al30 sdq_a39 13 al31 sdq_a34 14 an30 sdq_a38 15 al27 sdq_a37 16 ak27 sdq_a32 17 an29 scas_a# 18 an28 swe_a# 19 ar28 scs_a2# 20 an27 sbs_a1 21 ap27 sras_a# 22 ar27 sbs_a0 23 ap25 sclk_a0# 24 an26 sclk_a0 25 an25 sclk_a3 26 am24 sclk_a3# 27 al24 sma_a2 28 am27 sma_a10 29 ap26 sma_a0 30 ap31 sma_a13 31 ar24 sma_a1 32 ar23 sma_a4 33 ap23 sma_a3 34 an23 sma_a6 35 an22 sma_a8 36 af17 sdqs_a3 37 ah18 sdq_a27 38 af19 sdq_a26 39 aj17 sdq_a25 40 al17 sdq_a24 41 af16 sdq_a29 42 an18 scke_a2 43 ar7 sdqs_a2# 44 am3 sclk_a1# 45 al2 sdqs_a1# 46 ag2 sdqs_a0# a16 exp_slr xor chain #4 output testability r datasheet 421 table 15-18. ddr2 xor chain #5 pin count ball # ddr2 signal name comments 1 y28 sdqs_b7# 2 ac30 sdqs_b6# 3 ad28 sclk_b5 4 ag30 sdq_b46 5 ah30 sdqs_b5# 6 ag24 sdm_b4 7 ad23 sdq_b37 8 af24 sdq_b32 9 ag26 sdqs_b4# 10 af20 sdqs_b3# 11 ae22 sdq_b30 12 al18 sdq_b29 13 ak19 sdq_b24 14 ag20 sdm_b3 15 ad21 sdq_b27 16 af22 sdq_b31 17 ah21 sdq_b26 18 ad18 sdq_b28 19 ah19 sdq_b25 20 ak22 sclk_b3# 21 ag23 sclk_b0# 22 ah22 sclk_b0 23 an17 sras_b# 24 ap18 scas_b# 25 ap17 swe_b# 26 ar16 sbs_b0 27 an16 sbs_b1 28 an15 sma_b2 29 am15 sma_b0 30 ap15 sma_b10 31 ar15 sma_b1 32 al15 sma_b3 33 ap14 sma_b4 34 ap10 scke_b0 35 al14 sdqs_b2# 36 al9 sclk_b1# 37 ah10 sdqs_b1# 38 al4 sdqs_b0# b15 rsv xor chain #5 output testability r 422 datasheet table 15-19. ddr2 xor chain #6 pin count ball # ddr2 signal name comments 1 ag17 sdqs_a3# 2 ah16 sdm_a3 3 ae19 sdq_a31 4 ad17 sdq_a30 5 ak16 sdq_a28 6 am18 scke_a1 7 am21 sma_a11 8 an21 sma_a9 9 ap22 sma_a5 10 an20 sbs_a2 11 ap21 sma_a7 12 ar20 sma_a12 13 ap19 scke_a0 14 ar19 scke_a3 15 ap7 sdqs_a2 16 ap9 sdq_a18 17 an9 sdq_a19 18 ar8 sdq_a23 19 an8 sdq_a22 20 an7 sdm_a2 21 ap6 sdq_a17 22 ar5 sdq_a16 23 ap5 sdq_a21 24 an5 sdq_a20 25 an2 sclk_a4# 26 an3 sclk_a4 27 am2 sclk_a1 28 ap4 sdq_a11 29 ap3 sdq_a15 30 ap2 sdq_a14 31 an4 sdq_a10 32 ak3 sdq_a9 33 ak2 sdq_a8 34 aj3 sdq_a13 35 aj1 sdq_a12 36 al1 sdm_a1 37 al3 sdqs_a1 38 ag1 sdqs_a0 39 ag3 sdq_a6 40 af2 sdm_a0 41 ah2 sdq_a7 42 ah3 sdq_a2 43 aj2 sdq_a3 44 af3 sdq_a1 45 ae3 sdq_a0 46 ae2 sdq_a4 47 ae1 sdq_a5 c14 rsv xor chain #6 output testability r datasheet 423 table 15-20. ddr2 xor chain #7 pin count ball # ddr2 signal name comments 1 ah25 sdqs_b4 2 ad20 sdqs_b3 3 al23 sclk_b3 4 ap13 sma_b6 5 ar12 sma_b9 6 an13 sma_b8 7 al12 sma_b7 8 ar11 sma_b12 9 ap11 sma_b11 10 an11 sbs_b2 11 am12 sma_b5 12 ar9 scke_b2 13 an10 scke_b1 14 am9 scke_b3 15 ad15 sdq_b19 16 ad14 sdq_b18 17 ag14 sdq_b22 18 ah13 sdm_b2 19 ah12 sdq_b17 20 af14 sdq_b23 21 ad12 sdq_b20 22 af13 sdq_b16 23 ae13 sdq_b21 24 ak13 sdqs_b2 25 al11 sclk_b4# 26 aj11 sclk_b4 27 ak9 sclk_b1 28 al8 sdq_b9 29 al7 sdq_b13 30 aj7 sdq_b12 31 aj8 sdq_b8 32 af11 sdq_b10 33 ag11 sdq_b15 34 ag10 sdq_b14 35 ah9 sdm_b1 36 ae11 sdq_b11 37 ak10 sdqs_b1 38 ak5 sdqs_b0 39 ag9 sdq_b4 40 ah7 sdq_b5 41 aj6 sdq_b1 42 al6 sdq_b2 43 an6 sdq_b3 44 al5 sdq_b6 45 aj5 sdm_b0 46 ah4 sdq_b0 47 am5 sdq_b7 k15 rsv xor chain #7 output testability r 424 datasheet table 15-21. ddr2 xor chain #8 pin count ball # ddr2 signal name comments 1 f11 exp_rxn0 for sdvo interface signal name, see ballout table. 2 c9 exp_txn0 for sdvo interface signal name, see ballout table. 3 h11 exp_rxn1 for sdvo interface signal name, see ballout table. 4 a8 exp_txn1 for sdvo interface signal name, see ballout table. 5 e9 exp_rxn2 for sdvo interface signal name, see ballout table. 6 c7 exp_txn2 for sdvo interface signal name, see ballout table. 7 e7 exp_rxn3 for sdvo interface signal name, see ballout table. 8 a6 exp_txn3 for sdvo interface signal name, see ballout table. 9 b4 exp_rxn4 for sdvo interface signal name, see ballout table. 10 c5 exp_txn4 for sdvo interface signal name, see ballout table. 11 e5 exp_rxn5 for sdvo interface signal name, see ballout table. 12 d2 exp_txn5 for sdvo interface signal name, see ballout table. 13 g5 exp_rxn6 for sdvo interface signal name, see ballout table. 14 f3 exp_txn6 for sdvo interface signal name, see ballout table. 15 h7 exp_rxn7 for sdvo interface signal name, see ballout table. 16 g1 exp_txn7 for sdvo interface signal name, see ballout table. 17 j5 exp_rxn8 for sdvo interface signal name, see ballout table. 18 h3 exp_txn8 for sdvo interface signal name, see ballout table. 19 k7 exp_rxn9 for sdvo interface signal name, see ballout table. 20 j1 exp_txn9 for sdvo interface signal name, see ballout table. 21 l5 exp_rxn10 for sdvo interface signal name, see ballout table. 22 k3 exp_txn10 for sdvo interface signal name, see ballout table. 23 r10 exp_rxn11 for sdvo interface signal name, see ballout table. 24 l1 exp_txn11 for sdvo interface signal name, see ballout table. 25 m7 exp_rxn12 for sdvo interface signal name, see ballout table. 26 m3 exp_txn12 for sdvo interface signal name, see ballout table. 27 n5 exp_rxn13 for sdvo interface signal name, see ballout table. 28 n1 exp_txn13 for sdvo interface signal name, see ballout table. 29 p8 exp_rxn14 for sdvo interface signal name, see ballout table. 30 p3 exp_txn14 for sdvo interface signal name, see ballout table. 31 r5 exp_rxn15 for sdvo interface signal name, see ballout table. 32 r1 exp_txn15 for sdvo interface signal name, see ballout table. 33 e11 exp_rxp0 for sdvo interface signal name, see ballout table. 34 c10 exp_txp0 for sdvo interface signal name, see ballout table. 35 j11 exp_rxp1 for sdvo interface signal name, see ballout table. 36 a9 exp_txp1 for sdvo interface signal name, see ballout table. 37 f9 exp_rxp2 for sdvo interface signal name, see ballout table. 38 c8 exp_txp2 for sdvo interface signal name, see ballout table. 39 f7 exp_rxp3 for sdvo interface signal name, see ballout table. 40 a7 exp_txp3 for sdvo interface signal name, see ballout table. 41 b3 exp_rxp4 for sdvo interface signal name, see ballout table. 42 c6 exp_txp4 for sdvo interface signal name, see ballout table. 43 d5 exp_rxp5 for sdvo interface signal name, see ballout table. 44 c2 exp_txp5 for sdvo interface signal name, see ballout table. 45 g6 exp_rxp6 for sdvo interface signal name, see ballout table. testability r datasheet 425 pin count ball # ddr2 signal name comments 46 e3 exp_txp6 for sdvo interface signal name, see ballout table. 47 h8 exp_rxp7 for sdvo interface signal name, see ballout table. 48 f1 exp_txp7 for sdvo interface signal name, see ballout table. 49 j6 exp_rxp8 for sdvo interface signal name, see ballout table. 50 g3 exp_txp8 for sdvo interface signal name, see ballout table. 51 k8 exp_rxp9 for sdvo interface signal name, see ballout table. 52 h1 exp_txp9 for sdvo interface signal name, see ballout table. 53 l6 exp_rxp10 for sdvo interface signal name, see ballout table. 54 j3 exp_txp10 for sdvo interface signal name, see ballout table. 55 p10 exp_rxp11 for sdvo interface signal name, see ballout table. 56 k1 exp_txp11 for sdvo interface signal name, see ballout table. 57 m8 exp_rxp12 for sdvo interface signal name, see ballout table. 58 l3 exp_txp12 for sdvo interface signal name, see ballout table. 59 n6 exp_rxp13 for sdvo interface signal name, see ballout table. 60 m1 exp_txp13 for sdvo interface signal name, see ballout table. 61 p7 exp_rxp14 for sdvo interface signal name, see ballout table. 62 n3 exp_txp14 for sdvo interface signal name, see ballout table. 63 r6 exp_rxp15 for sdvo interface signal name, see ballout table. 64 p1 exp_txp15 for sdvo interface signal name, see ballout table. h16 bsel0 xor chain #8 output table 15-22. ddr2 xor chain #9 pin count ball # ddr2 signal name comments 1 u6 dmi_rxn0 2 u5 dmi_rxp0 3 t3 dmi_txn0 4 r3 dmi_txp0 5 t8 dmi_rxn1 6 t9 dmi_rxp1 7 u1 dmi_txn1 8 t1 dmi_txp1 9 v8 dmi_rxn2 10 v7 dmi_rxp2 11 v3 dmi_txn2 12 u3 dmi_txp2 13 u10 dmi_rxn3 14 v10 dmi_rxp3 15 w5 dmi_txn3 16 v5 dmi_txp3 e15 bsel1 xor chain #9 output testability r 426 datasheet 15.7 pads excluded from xor mode(s) a large number of pads do not support xor testing. the majority of the pads that fall into this category are analog related pins (see table 15-23). table 15-23. xor pad exclusion list pci express* host interface system memory misc gclkn hclkn srcomp1 drefclkn gclkp hclkp srcomp0 drefclkp exp_compo hrcomp smvref1 blue exp_compi hscomp smvref0 blue# hvref socomp1 green hswing socomp0 green# sm_slewout1 red sm_slewout0 red# sm_slewin1 rstin# sm_slewin0 hsync vsync refset |
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